#define regno(x) ((x) & 0x3F)
#define is_ir_num(x) (((x) & ~0x3F) == 0)
-#define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2))
+#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
+#define is_spfp_p(op) (((sc) == SPX))
+#define is_dpfp_p(op) (((sc) == DPX))
+#define is_fpuda_p(op) (((sc) == DPA))
#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
#define is_kernel_insn_p(op) (((op)->class == KERNEL))
bfd_boolean has_delay_slot;
} arc_last_insns[2];
+/* Structure to hold an entry in ARC_OPCODE_HASH. */
+struct arc_opcode_hash_entry
+{
+ /* The number of pointers in the OPCODE list. */
+ size_t count;
+
+ /* Points to a list of opcode pointers. */
+ const struct arc_opcode **opcode;
+};
+
+/* Structure used for iterating through an arc_opcode_hash_entry. */
+struct arc_opcode_hash_entry_iterator
+{
+ /* Index into the OPCODE element of the arc_opcode_hash_entry. */
+ size_t index;
+
+ /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
+ returned by this iterator. */
+ const struct arc_opcode *opcode;
+};
+
/* Forward declaration. */
static void assemble_insn
(const struct arc_opcode *, const expressionS *, int,
const struct arc_flags *, int, struct arc_insn *);
/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
E_ARC_MACH_ARC600, 0x00},
{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
E_ARC_MACH_ARC700, 0x00},
+ { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
+ E_ARC_MACH_NPS400, 0x00},
{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
- { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
- 0x00, 0x00 },
{ 0, 0, 0, 0, 0 }
};
/* Functions implementation. */
+/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
+ ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
+ are no matching entries in ARC_OPCODE_HASH. */
+
+static const struct arc_opcode_hash_entry *
+arc_find_opcode (const char *name)
+{
+ const struct arc_opcode_hash_entry *entry;
+
+ entry = hash_find (arc_opcode_hash, name);
+ return entry;
+}
+
+/* Initialise the iterator ITER. */
+
+static void
+arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
+{
+ iter->index = 0;
+ iter->opcode = NULL;
+}
+
+/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
+ calls to this function. Return NULL when all ARC_OPCODE entries have
+ been returned. */
+
+static const struct arc_opcode *
+arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
+ struct arc_opcode_hash_entry_iterator *iter)
+{
+ if (iter->opcode == NULL && iter->index == 0)
+ {
+ gas_assert (entry->count > 0);
+ iter->opcode = entry->opcode[iter->index];
+ }
+ else if (iter->opcode != NULL)
+ {
+ const char *old_name = iter->opcode->name;
+
+ iter->opcode++;
+ if ((iter->opcode - arc_opcodes >= (int) arc_num_opcodes)
+ || (strcmp (old_name, iter->opcode->name) != 0))
+ {
+ iter->index++;
+ if (iter->index == entry->count)
+ iter->opcode = NULL;
+ else
+ iter->opcode = entry->opcode[iter->index];
+ }
+ }
+
+ return iter->opcode;
+}
+
/* Like md_number_to_chars but used for limms. The 4-byte limm value,
is encoded as 'middle-endian' for a little-endian target. FIXME!
this function is used for regular 4 byte instructions as well. */
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = 0;
+ int i;
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcasecmp (cpu_types[i].name, arg))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+ gas_assert (cpu_flags != 0);
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
lab = symbol_find_or_make (lab_name);
restore_line_pointer (c);
}
+
+ /* These relocations exist as a mechanism for the compiler to tell the
+ linker how to patch the code if the tls model is optimised. However,
+ the relocation itself does not require any space within the assembler
+ fragment, and so we pass a size of 0.
+
+ The lines that generate these relocations look like this:
+
+ .tls_gd_ld @.tdata`bl __tls_get_addr@plt
+
+ The '.tls_gd_ld @.tdata' is processed first and generates the
+ additional relocation, while the 'bl __tls_get_addr@plt' is processed
+ second and generates the additional branch.
+
+ It is possible that the additional relocation generated by the
+ '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
+ while the 'bl __tls_get_addr@plt' will be generated as the first thing
+ in the next fragment. This will be fine; both relocations will still
+ appear to be at the same address in the generated object file.
+ However, this only works as the additional relocation is generated
+ with size of 0 bytes. */
fixS *fixP
= fix_new (frag_now, /* Which frag? */
frag_now_fix (), /* Where in that frag? */
- 2, /* size: 1, 2, or 4 usually. */
+ 0, /* size: 1, 2, or 4 usually. */
sym, /* X_add_symbol. */
0, /* X_add_number. */
FALSE, /* TRUE if PC-relative relocation. */
md_parse_option (OPTION_MCPU, "archs");
}
else
- as_fatal ("could not find the architecture");
+ as_fatal (_("could not find the architecture"));
if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
- as_fatal ("could not set architecture and machine");
+ as_fatal (_("could not set architecture and machine"));
}
else
if (arc_mach_type != mach)
- as_warn ("Command-line value overrides \".cpu\" directive");
+ as_warn (_("Command-line value overrides \".cpu\" directive"));
restore_line_pointer (c);
demand_empty_rest_of_line ();
bad_cpu:
restore_line_pointer (c);
- as_bad ("invalid identifier for \".cpu\"");
+ as_bad (_("invalid identifier for \".cpu\""));
ignore_rest_of_line ();
}
if (num_flags >= nflg)
goto err;
- flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz");
- if (flgnamelen > MAX_FLAG_NAME_LENGHT)
+ flgnamelen = strspn (input_line_pointer,
+ "abcdefghijklmnopqrstuvwxyz0123456789");
+ if (flgnamelen > MAX_FLAG_NAME_LENGTH)
goto err;
memcpy (flags->name, input_line_pointer, flgnamelen);
return allocate_tok (tok, ntok - 1, cidx);
}
+/* Check if an particular ARC feature is enabled. */
+
+static bfd_boolean
+check_cpu_feature (insn_subclass_t sc)
+{
+ if (!(arc_features & ARC_CD)
+ && is_code_density_p (sc))
+ return FALSE;
+
+ if (!(arc_features & ARC_SPFP)
+ && is_spfp_p (sc))
+ return FALSE;
+
+ if (!(arc_features & ARC_DPFP)
+ && is_dpfp_p (sc))
+ return FALSE;
+
+ if (!(arc_features & ARC_FPUDA)
+ && is_fpuda_p (sc))
+ return FALSE;
+
+ return TRUE;
+}
+
/* Search forward through all variants of an opcode looking for a
syntax match. */
static const struct arc_opcode *
-find_opcode_match (const struct arc_opcode *first_opcode,
+find_opcode_match (const struct arc_opcode_hash_entry *entry,
expressionS *tok,
int *pntok,
struct arc_flags *first_pflag,
int nflgs,
int *pcpumatch)
{
- const struct arc_opcode *opcode = first_opcode;
+ const struct arc_opcode *opcode;
+ struct arc_opcode_hash_entry_iterator iter;
int ntok = *pntok;
int got_cpu_match = 0;
expressionS bktok[MAX_INSN_ARGS];
int bkntok;
expressionS emptyE;
+ arc_opcode_hash_entry_iterator_init (&iter);
memset (&emptyE, 0, sizeof (emptyE));
memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
bkntok = ntok;
- do
+ for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
+ opcode != NULL;
+ opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
{
const unsigned char *opidx;
const unsigned char *flgidx;
- int tokidx = 0;
+ int tokidx = 0, lnflg, i;
const expressionS *t = &emptyE;
pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
if (!(opcode->cpu & arc_target))
goto match_failed;
- if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
+ if (!check_cpu_feature (opcode->subclass))
goto match_failed;
got_cpu_match = 1;
++ntok;
break;
+ case O_symbol:
+ {
+ const char *p;
+ size_t len;
+ const struct arc_aux_reg *auxr;
+ unsigned j;
+
+ if (opcode->class != AUXREG)
+ goto de_fault;
+ p = S_GET_NAME (tok[tokidx].X_add_symbol);
+ len = strlen (p);
+
+ auxr = &arc_aux_regs[0];
+ for (j = 0; j < arc_num_aux_regs; j++, auxr++)
+ if (len == auxr->length
+ && strcasecmp (auxr->name, p) == 0
+ && ((auxr->subclass == NONE)
+ || check_cpu_feature (auxr->subclass)))
+ {
+ /* We modify the token array here, safe in the
+ knowledge, that if this was the wrong choice
+ then the original contents will be restored
+ from BKTOK. */
+ tok[tokidx].X_op = O_constant;
+ tok[tokidx].X_add_number = auxr->address;
+ ARC_SET_FLAG (tok[i].X_add_symbol, ARC_FLAG_AUX);
+ break;
+ }
+
+ if (tok[tokidx].X_op != O_constant)
+ goto de_fault;
+ }
+ /* Fall-through */
case O_constant:
/* Check the range. */
if (operand->bits != 32
break;
}
default:
+ de_fault:
if (operand->default_reloc == 0)
goto match_failed; /* The operand needs relocation. */
}
pr_debug ("opr ");
- /* Check the flags. Iterate over the valid flag classes. */
- int lnflg = nflgs;
+ /* Setup ready for flag parsing. */
+ lnflg = nflgs;
+ for (i = 0; i < nflgs; i++)
+ first_pflag [i].code = 0;
- for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
+ /* Check the flags. Iterate over the valid flag classes. */
+ for (flgidx = opcode->flags; *flgidx; ++flgidx)
{
/* Get a valid flag class. */
const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
const unsigned *flgopridx;
+ int cl_matches = 0;
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
const struct arc_flag_operand *flg_operand;
struct arc_flags *pflag = first_pflag;
- int i;
flg_operand = &arc_flag_operands[*flgopridx];
for (i = 0; i < nflgs; i++, pflag++)
/* Match against the parsed flags. */
if (!strcmp (flg_operand->name, pflag->name))
{
- /*TODO: Check if it is duplicated. */
+ if (pflag->code != 0)
+ goto match_failed;
+ cl_matches++;
pflag->code = *flgopridx;
lnflg--;
break; /* goto next flag class and parsed flag. */
}
}
}
+
+ if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
+ goto match_failed;
+ if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
+ goto match_failed;
}
/* Did I check all the parsed flags? */
if (lnflg)
memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
ntok = bkntok;
}
- while (++opcode - arc_opcodes < (int) arc_num_opcodes
- && !strcmp (opcode->name, first_opcode->name));
if (*pcpumatch)
*pcpumatch = got_cpu_match;
/* Assumes the expressionS *tok is of sufficient size. */
-static const struct arc_opcode *
+static const struct arc_opcode_hash_entry *
find_special_case_pseudo (const char *opname,
int *ntok,
expressionS *tok,
break;
}
- return (const struct arc_opcode *)
- hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r);
+ return arc_find_opcode (pseudo_insn->mnemonic_r);
}
-static const struct arc_opcode *
+static const struct arc_opcode_hash_entry *
find_special_case_flag (const char *opname,
int *nflgs,
struct arc_flags *pflags)
unsigned flag_idx, flag_arr_idx;
size_t flaglen, oplen;
const struct arc_flag_special *arc_flag_special_opcode;
- const struct arc_opcode *opcode;
+ const struct arc_opcode_hash_entry *entry;
/* Search for special case instruction. */
for (i = 0; i < arc_num_flag_special; i++)
flaglen = strlen (flagnm);
if (strcmp (opname + oplen, flagnm) == 0)
{
- opcode = (const struct arc_opcode *)
- hash_find (arc_opcode_hash,
- arc_flag_special_opcode->name);
+ entry = arc_find_opcode (arc_flag_special_opcode->name);
if (*nflgs + 1 > MAX_INSN_FLGS)
break;
memcpy (pflags[*nflgs].name, flagnm, flaglen);
pflags[*nflgs].name[flaglen] = '\0';
(*nflgs)++;
- return opcode;
+ return entry;
}
}
}
/* Used to find special case opcode. */
-static const struct arc_opcode *
+static const struct arc_opcode_hash_entry *
find_special_case (const char *opname,
int *nflgs,
struct arc_flags *pflags,
expressionS *tok,
int *ntok)
{
- const struct arc_opcode *opcode;
+ const struct arc_opcode_hash_entry *entry;
- opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
+ entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
- if (opcode == NULL)
- opcode = find_special_case_flag (opname, nflgs, pflags);
+ if (entry == NULL)
+ entry = find_special_case_flag (opname, nflgs, pflags);
- return opcode;
-}
-
-static void
-preprocess_operands (const struct arc_opcode *opcode,
- expressionS *tok,
- int ntok)
-{
- int i;
- size_t len;
- const char *p;
- unsigned j;
- const struct arc_aux_reg *auxr;
-
- for (i = 0; i < ntok; i++)
- {
- switch (tok[i].X_op)
- {
- case O_illegal:
- case O_absent:
- break; /* Throw and error. */
-
- case O_symbol:
- if (opcode->class != AUXREG)
- break;
- /* Convert the symbol to a constant if possible. */
- p = S_GET_NAME (tok[i].X_add_symbol);
- len = strlen (p);
-
- auxr = &arc_aux_regs[0];
- for (j = 0; j < arc_num_aux_regs; j++, auxr++)
- if (len == auxr->length
- && strcasecmp (auxr->name, p) == 0)
- {
- tok[i].X_op = O_constant;
- tok[i].X_add_number = auxr->address;
- break;
- }
- break;
- default:
- break;
- }
- }
+ return entry;
}
/* Given an opcode name, pre-tockenized set of argumenst and the
int nflgs)
{
bfd_boolean found_something = FALSE;
- const struct arc_opcode *opcode;
+ const struct arc_opcode_hash_entry *entry;
int cpumatch = 1;
/* Search opcodes. */
- opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname);
+ entry = arc_find_opcode (opname);
/* Couldn't find opcode conventional way, try special cases. */
- if (!opcode)
- opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
+ if (entry == NULL)
+ entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
- if (opcode)
+ if (entry != NULL)
{
- pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
- frag_now->fr_file, frag_now->fr_line, opcode->name,
- opcode->opcode);
-
- preprocess_operands (opcode, tok, ntok);
+ const struct arc_opcode *opcode;
+ pr_debug ("%s:%d: assemble_tokens: %s\n",
+ frag_now->fr_file, frag_now->fr_line, opname);
found_something = TRUE;
- opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
- if (opcode)
+ opcode = find_opcode_match (entry, tok, &ntok, pflags,
+ nflgs, &cpumatch);
+ if (opcode != NULL)
{
struct arc_insn insn;
+
assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
emit_insn (&insn);
return;
/* Callback to insert a register into the hash table. */
static void
-declare_register (char *name, int number)
+declare_register (const char *name, int number)
{
const char *err;
symbolS *regS = symbol_create (name, reg_section,
err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
if (err)
- as_fatal ("Inserting \"%s\" into register table failed: %s",
+ as_fatal (_("Inserting \"%s\" into register table failed: %s"),
name, err);
}
{
unsigned int i;
+ if (!mach_type_specified_p)
+ arc_select_cpu ("arc700");
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
for (i = 0; i < arc_num_opcodes;)
{
const char *name, *retval;
+ struct arc_opcode_hash_entry *entry;
name = arc_opcodes[i].name;
- retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]);
- if (retval)
- as_fatal (_("internal error: can't hash opcode '%s': %s"),
- name, retval);
+
+ entry = hash_find (arc_opcode_hash, name);
+ if (entry == NULL)
+ {
+ entry = xmalloc (sizeof (*entry));
+ entry->count = 0;
+ entry->opcode = NULL;
+
+ retval = hash_insert (arc_opcode_hash, name, (void *) entry);
+ if (retval)
+ as_fatal (_("internal error: can't hash opcode '%s': %s"),
+ name, retval);
+ }
+
+ entry->opcode = xrealloc (entry->opcode,
+ sizeof (const struct arc_opcode *)
+ * entry->count + 1);
+ entry->opcode [entry->count] = &arc_opcodes[i];
+ entry->count++;
while (++i < arc_num_opcodes
&& (arc_opcodes[i].name == name
of LITTLENUMS emitted is stored in *sizeP. An error message is
returned, or NULL on OK. */
-char *
+const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, target_big_endian);
arc700, av2em, av2hs. */
int
-md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
/* This option has an effect only on ARC EM. */
if (arc_target & ARC_OPCODE_ARCv2EM)
arc_features |= ARC_CD;
+ else
+ as_warn (_("Code density option invalid for selected CPU"));
break;
case OPTION_RELAX:
case OPTION_EA:
case OPTION_MUL64:
case OPTION_SIMD:
+ /* Dummy options are accepted but have no effect. */
+ break;
+
case OPTION_SPFP:
+ arc_features |= ARC_SPFP;
+ break;
+
case OPTION_DPFP:
+ arc_features |= ARC_DPFP;
+ break;
+
case OPTION_XMAC_D16:
case OPTION_XMAC_24:
case OPTION_DSP_PACKA:
case OPTION_LOCK:
case OPTION_SWAPE:
case OPTION_RTSC:
- case OPTION_FPUDA:
/* Dummy options are accepted but have no effect. */
break;
+ case OPTION_FPUDA:
+ /* This option has an effect only on ARC EM. */
+ if (arc_target & ARC_OPCODE_ARCv2EM)
+ arc_features |= ARC_FPUDA;
+ else
+ as_warn (_("FPUDA invalid for selected CPU"));
+ break;
+
default:
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
switch (t->X_md)
{
case O_plt:
+ if (opcode->class == JUMP)
+ as_bad_where (frag_now->fr_file, frag_now->fr_line,
+ _("Unable to use @plt relocatio for insn %s"),
+ opcode->name);
needGOTSymbol = TRUE;
reloc = find_reloc ("plt", opcode->name,
pflags, nflg,
break;
case O_pcl:
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
- if (ARC_SHORT (opcode->mask))
+ if (ARC_SHORT (opcode->mask) || opcode->class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
_("Unable to use @pcl relocation for insn %s"),
opcode->name);
break;
}
- return 0; /* FIXME! return 1, fix it in the linker. */
+ return 1;
}
/* Compute the reloc type of an expression EXP. */
end of the ZOL label @%s"), S_GET_NAME (s));
/* Fall through. */
+ case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
if (arc_last_insns[0].has_delay_slot)
as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
return -1;
}
+
+/* Adjust the symbol table. Delete found AUX register symbols. */
+
+void
+arc_adjust_symtab (void)
+{
+ symbolS * sym;
+
+ for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
+ {
+ /* I've created a symbol during parsing process. Now, remove
+ the symbol as it is found to be an AUX register. */
+ if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
+ symbol_remove (sym, &symbol_rootP, &symbol_lastP);
+ }
+
+ /* Now do generic ELF adjustments. */
+ elf_adjust_symtab ();
+}