#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
-#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
- (SUB_OPCODE (x) == 0x28))
+#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
+ && (SUB_OPCODE (x) == 0x28))
/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
+#ifndef TARGET_WITH_CPU
+#define TARGET_WITH_CPU "arc700"
+#endif /* TARGET_WITH_CPU */
+
/* Enum used to enumerate the relaxable ins operands. */
enum rlx_operand_type
{
#define is_spfp_p(op) (((sc) == SPX))
#define is_dpfp_p(op) (((sc) == DPX))
#define is_fpuda_p(op) (((sc) == DPA))
-#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
-#define is_kernel_insn_p(op) (((op)->class == KERNEL))
+#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
+ || (op)->insn_class == JUMP))
+#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
+#define is_nps400_p(op) (((sc) == NPS400))
/* Generic assembler global variables which must be defined by all
targets. */
OPTION_MCPU,
OPTION_CD,
OPTION_RELAX,
+ OPTION_NPS400,
+
+ OPTION_SPFP,
+ OPTION_DPFP,
+ OPTION_FPUDA,
/* The following options are deprecated and provided here only for
compatibility reasons. */
OPTION_EA,
OPTION_MUL64,
OPTION_SIMD,
- OPTION_SPFP,
- OPTION_DPFP,
OPTION_XMAC_D16,
OPTION_XMAC_24,
OPTION_DSP_PACKA,
OPTION_XYMEMORY,
OPTION_LOCK,
OPTION_SWAPE,
- OPTION_RTSC,
- OPTION_FPUDA
+ OPTION_RTSC
};
struct option md_longopts[] =
{ "mHS", no_argument, NULL, OPTION_ARCHS },
{ "mcode-density", no_argument, NULL, OPTION_CD },
{ "mrelax", no_argument, NULL, OPTION_RELAX },
+ { "mnps400", no_argument, NULL, OPTION_NPS400 },
+
+ /* Floating point options */
+ { "mspfp", no_argument, NULL, OPTION_SPFP},
+ { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
+ { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
+ { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
+ { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
+ { "mdpfp", no_argument, NULL, OPTION_DPFP},
+ { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
+ { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
+ { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
+ { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
+ { "mfpuda", no_argument, NULL, OPTION_FPUDA},
/* The following options are deprecated and provided here only for
compatibility reasons. */
{ "mEA", no_argument, NULL, OPTION_EA },
{ "mmul64", no_argument, NULL, OPTION_MUL64 },
{ "msimd", no_argument, NULL, OPTION_SIMD},
- { "mspfp", no_argument, NULL, OPTION_SPFP},
- { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
- { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
- { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
- { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
- { "mdpfp", no_argument, NULL, OPTION_DPFP},
- { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
- { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
- { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
- { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
{ "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
{ "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
{ "mmac-24", no_argument, NULL, OPTION_XMAC_24},
{ "mlock", no_argument, NULL, OPTION_LOCK},
{ "mswape", no_argument, NULL, OPTION_SWAPE},
{ "mrtsc", no_argument, NULL, OPTION_RTSC},
- { "mfpuda", no_argument, NULL, OPTION_FPUDA},
{ NULL, no_argument, NULL, 0 }
};
struct arc_insn
{
- unsigned int insn;
+ unsigned long long int insn;
int nfixups;
struct arc_fixup fixups[MAX_INSN_FIXUPS];
long limm;
- bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
- short. */
+ unsigned int len; /* Length of instruction in bytes. */
bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
valid. */
bfd_boolean relax; /* Boolean value: TRUE if needs
{
const char *name;
int len;
- int class;
+ int attr_class;
} attributes_t;
static const attributes_t suffixclass[] =
(const struct arc_opcode *, const expressionS *, int,
const struct arc_flags *, int, struct arc_insn *);
-/* The cpu for which we are generating code. */
-static unsigned arc_target;
-static const char *arc_target_name;
-static unsigned arc_features;
+/* The selection of the machine type can come from different sources. This
+ enum is used to track how the selection was made in order to perform
+ error checks. */
+enum mach_selection_type
+ {
+ MACH_SELECTION_NONE,
+ MACH_SELECTION_FROM_DEFAULT,
+ MACH_SELECTION_FROM_CPU_DIRECTIVE,
+ MACH_SELECTION_FROM_COMMAND_LINE
+ };
-/* The default architecture. */
-static int arc_mach_type;
-
-/* TRUE if the cpu type has been explicitly specified. */
-static bfd_boolean mach_type_specified_p = FALSE;
+/* How the current machine type was selected. */
+static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
/* The hash table of instruction opcodes. */
static struct hash_control *arc_opcode_hash;
/* The hash table of aux register symbols. */
static struct hash_control *arc_aux_hash;
+/* The hash table of address types. */
+static struct hash_control *arc_addrtype_hash;
+
/* A table of CPU names and opcode sets. */
static const struct cpu_type
{
E_ARC_MACH_ARC600, 0x00},
{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
E_ARC_MACH_ARC700, 0x00},
- { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
- E_ARC_MACH_NPS400, 0x00},
+ { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
+ E_ARC_MACH_ARC700, ARC_NPS400},
{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
- EF_ARC_CPU_ARCV2EM, ARC_CD},
+ EF_ARC_CPU_ARCV2EM, 0x00},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
{ 0, 0, 0, 0, 0 }
};
+/* Information about the cpu/variant we're assembling for. */
+static struct cpu_type selected_cpu = { 0, 0, 0, 0, 0 };
+
+/* A table with options. */
+static const struct feature_type
+{
+ unsigned feature;
+ unsigned cpus;
+ const char *name;
+}
+ feature_list[] =
+{
+ { ARC_CD, ARC_OPCODE_ARCV2, "code-density" },
+ { ARC_NPS400, ARC_OPCODE_ARC700, "nps400" },
+ { ARC_SPFP, ARC_OPCODE_ARCFPX, "single-precision FPX" },
+ { ARC_DPFP, ARC_OPCODE_ARCFPX, "double-precision FPX" },
+ { ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
+};
+
/* Used by the arc_reloc_op table. Order is important. */
#define O_gotoff O_md1 /* @gotoff relocation. */
#define O_gotpc O_md2 /* @gotpc relocation. */
/* Used to define a bracket as operand in tokens. */
#define O_bracket O_md32
+/* Used to define a colon as an operand in tokens. */
+#define O_colon O_md31
+
+/* Used to define address types in nps400. */
+#define O_addrtype O_md30
+
/* Dummy relocation, to be sorted out. */
#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
- DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
+ DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
};
static const int arc_num_reloc_op
/* BL_S s13 ->
BL s25. */
- RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL),
- RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
+ RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
/* B_S s10 ->
B s25. */
- RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B),
- RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
+ RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
/* ADD_S c,b, u3 ->
ADD<.f> a,b,u6 ->
ADD<.f> a,b,limm. */
- RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6),
- RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
+ RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
/* LD_S a, [b, u7] ->
LD<zz><.x><.aa><.di> a, [b, s9] ->
LD<zz><.x><.aa><.di> a, [b, limm] */
- RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9),
- RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM),
- RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
+ RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
+ RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
/* MOV_S b, u8 ->
MOV<.f> b, s12 ->
MOV<.f> b, limm. */
- RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12),
- RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
+ RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
/* SUB_S c, b, u3 ->
SUB<.f> a, b, u6 ->
SUB<.f> a, b, limm. */
- RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6),
- RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
+ RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
/* MPY<.f> a, b, u6 ->
MPY<.f> a, b, limm. */
- RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
/* MOV<.f><.cc> b, u6 ->
MOV<.f><.cc> b, limm. */
- RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
/* ADD<.f><.cc> b, b, u6 ->
ADD<.f><.cc> b, b, limm. */
- RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM),
- RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
+ RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
+ RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
};
/* Order of this table's entries matters! */
const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
/* Flags to set in the elf header. */
-static flagword arc_eflag = 0x00;
+static const flagword arc_initial_eflag = 0x00;
/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
symbolS * GOT_symbol = 0;
const char *old_name = iter->opcode->name;
iter->opcode++;
- if (iter->opcode->name
- && (strcmp (old_name, iter->opcode->name) != 0))
+ if (iter->opcode->name == NULL
+ || strcmp (old_name, iter->opcode->name) != 0)
{
iter->index++;
if (iter->index == entry->count)
}
-/* Like md_number_to_chars but used for limms. The 4-byte limm value,
- is encoded as 'middle-endian' for a little-endian target. FIXME!
- this function is used for regular 4 byte instructions as well. */
+/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
+ value, is encoded as 'middle-endian' for a little-endian target. This
+ function is used for regular 4, 6, and 8 byte instructions as well. */
static void
-md_number_to_chars_midend (char *buf, valueT val, int n)
+md_number_to_chars_midend (char *buf, unsigned long long val, int n)
{
- if (n == 4)
+ switch (n)
{
+ case 2:
+ md_number_to_chars (buf, val, n);
+ break;
+ case 6:
+ md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
+ md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
+ break;
+ case 4:
md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
md_number_to_chars (buf + 2, (val & 0xffff), 2);
+ break;
+ case 8:
+ md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
+ md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
+ break;
+ default:
+ abort ();
}
- else
+}
+
+/* Check if a feature is allowed for a specific CPU. */
+
+static void
+arc_check_feature (void)
+{
+ unsigned i;
+
+ if (!selected_cpu.features
+ || !selected_cpu.name)
+ return;
+ for (i = 0; (i < ARRAY_SIZE (feature_list)); i++)
{
- md_number_to_chars (buf, val, n);
+ if ((selected_cpu.features & feature_list[i].feature)
+ && !(selected_cpu.flags & feature_list[i].cpus))
+ {
+ as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
+ selected_cpu.name);
+ }
}
}
/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
- the relevant static global variables. */
+ the relevant static global variables. Parameter SEL describes where
+ this selection originated from. */
static void
-arc_select_cpu (const char *arg)
+arc_select_cpu (const char *arg, enum mach_selection_type sel)
{
int cpu_flags = 0;
int i;
+ /* We should only set a default if we've not made a selection from some
+ other source. */
+ gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
+ || mach_selection_mode == MACH_SELECTION_NONE);
+
+ if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
+ && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
+ as_bad (_("Multiple .cpu directives found"));
+
+ /* Look for a matching entry in CPU_TYPES array. */
for (i = 0; cpu_types[i].name; ++i)
{
if (!strcasecmp (cpu_types[i].name, arg))
{
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
+ /* If a previous selection was made on the command line, then we
+ allow later selections on the command line to override earlier
+ ones. However, a selection from a '.cpu NAME' directive must
+ match the command line selection, or we give a warning. */
+ if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
+ {
+ gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
+ || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
+ if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
+ && selected_cpu.mach != cpu_types[i].mach)
+ {
+ as_warn (_("Command-line value overrides \".cpu\" directive"));
+ }
+ return;
+ }
+
+ /* Initialise static global data about selected machine type. */
+ selected_cpu.flags = cpu_types[i].flags;
+ selected_cpu.name = cpu_types[i].name;
+ selected_cpu.features |= cpu_types[i].features;
+ selected_cpu.mach = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
break;
}
}
if (!cpu_types[i].name)
as_fatal (_("unknown architecture: %s\n"), arg);
+
+ /* Check if set features are compatible with the chosen CPU. */
+ arc_check_feature ();
gas_assert (cpu_flags != 0);
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ mach_selection_mode = sel;
}
/* Here ends all the ARCompact extension instruction assembling
static void
arc_option (int ignore ATTRIBUTE_UNUSED)
{
- int mach = -1;
char c;
char *cpu;
+ const char *cpu_name;
c = get_symbol_name (&cpu);
- mach = arc_get_mach (cpu);
- if (mach == -1)
- goto bad_cpu;
+ if ((!strcmp ("ARC600", cpu))
+ || (!strcmp ("ARC601", cpu))
+ || (!strcmp ("A6", cpu)))
+ cpu_name = "arc600";
+ else if ((!strcmp ("ARC700", cpu))
+ || (!strcmp ("A7", cpu)))
+ cpu_name = "arc700";
+ else if (!strcmp ("EM", cpu))
+ cpu_name = "arcem";
+ else if (!strcmp ("HS", cpu))
+ cpu_name = "archs";
+ else if (!strcmp ("NPS400", cpu))
+ cpu_name = "nps400";
+ else
+ cpu_name = NULL;
- if (!mach_type_specified_p)
- {
- if ((!strcmp ("ARC600", cpu))
- || (!strcmp ("ARC601", cpu))
- || (!strcmp ("A6", cpu)))
- {
- md_parse_option (OPTION_MCPU, "arc600");
- }
- else if ((!strcmp ("ARC700", cpu))
- || (!strcmp ("A7", cpu)))
- {
- md_parse_option (OPTION_MCPU, "arc700");
- }
- else if (!strcmp ("EM", cpu))
- {
- md_parse_option (OPTION_MCPU, "arcem");
- }
- else if (!strcmp ("HS", cpu))
- {
- md_parse_option (OPTION_MCPU, "archs");
- }
- else if (!strcmp ("NPS400", cpu))
- {
- md_parse_option (OPTION_MCPU, "nps400");
- }
- else
- as_fatal (_("could not find the architecture"));
+ if (cpu_name != NULL)
+ arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
+ else
+ as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
- as_fatal (_("could not set architecture and machine"));
+ if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
+ as_fatal (_("could not set architecture and machine"));
- /* Set elf header flags. */
- bfd_set_private_flags (stdoutput, arc_eflag);
- }
- else
- if (arc_mach_type != mach)
- as_warn (_("Command-line value overrides \".cpu\" directive"));
+ /* Set elf header flags. */
+ bfd_set_private_flags (stdoutput, selected_cpu.eflags);
restore_line_pointer (c);
demand_empty_rest_of_line ();
- return;
-
- bad_cpu:
- restore_line_pointer (c);
- as_bad (_("invalid identifier for \".cpu\""));
- ignore_rest_of_line ();
}
/* Smartly print an expression. */
case O_logical_or: name = "O_logical_or"; break;
case O_index: name = "O_index"; break;
case O_bracket: name = "O_bracket"; break;
+ case O_colon: name = "O_colon"; break;
+ case O_addrtype: name = "O_addrtype"; break;
}
switch (t->X_md)
++num_args;
break;
+ case ':':
+ input_line_pointer++;
+ if (!saw_arg || num_args == ntok)
+ goto err;
+ tok->X_op = O_colon;
+ saw_arg = FALSE;
+ ++tok;
+ ++num_args;
+ break;
+
case '@':
/* We have labels, function names and relocations, all
starting with @ symbol. Sort them out. */
restore_line_pointer (c);
tmpE.X_add_number = 0;
}
- else if ((*input_line_pointer != '+')
+ if ((*input_line_pointer != '+')
&& (*input_line_pointer != '-'))
{
tmpE.X_add_number = 0;
/* FIXME! the reloc size is wrong in the BFD file.
When it is fixed please delete me. */
- size = (insn->short_insn && !fixup->islong) ? 2 : 4;
+ size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
if (fixup->islong)
- offset = (insn->short_insn) ? 2 : 4;
+ offset = insn->len;
/* Some fixups are only used internally, thus no howto. */
if ((int) fixup->reloc == 0)
{
/* FIXME! the reloc size is wrong in the BFD file.
When it is fixed please enable me.
- size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
+ size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
pcrel = fixup->pcrel;
}
else
emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
{
char *f = where;
+ size_t total_len;
- pr_debug ("Emit insn : 0x%x\n", insn->insn);
- pr_debug ("\tShort : 0x%d\n", insn->short_insn);
+ pr_debug ("Emit insn : 0x%llx\n", insn->insn);
+ pr_debug ("\tLength : 0x%d\n", insn->len);
pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
/* Write out the instruction. */
- if (insn->short_insn)
- {
- if (insn->has_limm)
- {
- if (!relax)
- f = frag_more (6);
- md_number_to_chars (f, insn->insn, 2);
- md_number_to_chars_midend (f + 2, insn->limm, 4);
- dwarf2_emit_insn (6);
- }
- else
- {
- if (!relax)
- f = frag_more (2);
- md_number_to_chars (f, insn->insn, 2);
- dwarf2_emit_insn (2);
- }
- }
- else
- {
- if (insn->has_limm)
- {
- if (!relax)
- f = frag_more (8);
- md_number_to_chars_midend (f, insn->insn, 4);
- md_number_to_chars_midend (f + 4, insn->limm, 4);
- dwarf2_emit_insn (8);
- }
- else
- {
- if (!relax)
- f = frag_more (4);
- md_number_to_chars_midend (f, insn->insn, 4);
- dwarf2_emit_insn (4);
- }
- }
+ total_len = insn->len + (insn->has_limm ? 4 : 0);
+ if (!relax)
+ f = frag_more (total_len);
+
+ md_number_to_chars_midend(f, insn->insn, insn->len);
+
+ if (insn->has_limm)
+ md_number_to_chars_midend (f + insn->len, insn->limm, 4);
+ dwarf2_emit_insn (total_len);
if (!relax)
apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
static bfd_boolean
check_cpu_feature (insn_subclass_t sc)
{
- if (!(arc_features & ARC_CD)
- && is_code_density_p (sc))
+ if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD))
+ return FALSE;
+
+ if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP))
return FALSE;
- if (!(arc_features & ARC_SPFP)
- && is_spfp_p (sc))
+ if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP))
return FALSE;
- if (!(arc_features & ARC_DPFP)
- && is_dpfp_p (sc))
+ if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA))
return FALSE;
- if (!(arc_features & ARC_FPUDA)
- && is_fpuda_p (sc))
+ if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400))
return FALSE;
return TRUE;
}
+/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
+ operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
+ array and returns TRUE if the flag operands all match, otherwise,
+ returns FALSE, in which case the FIRST_PFLAG array may have been
+ modified. */
+
+static bfd_boolean
+parse_opcode_flags (const struct arc_opcode *opcode,
+ int nflgs,
+ struct arc_flags *first_pflag)
+{
+ int lnflg, i;
+ const unsigned char *flgidx;
+
+ lnflg = nflgs;
+ for (i = 0; i < nflgs; i++)
+ first_pflag[i].flgp = NULL;
+
+ /* Check the flags. Iterate over the valid flag classes. */
+ for (flgidx = opcode->flags; *flgidx; ++flgidx)
+ {
+ /* Get a valid flag class. */
+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+ const unsigned *flgopridx;
+ int cl_matches = 0;
+ struct arc_flags *pflag = NULL;
+
+ /* Check for extension conditional codes. */
+ if (ext_condcode.arc_ext_condcode
+ && cl_flags->flag_class & F_CLASS_EXTEND)
+ {
+ struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
+ while (pf->name)
+ {
+ pflag = first_pflag;
+ for (i = 0; i < nflgs; i++, pflag++)
+ {
+ if (!strcmp (pf->name, pflag->name))
+ {
+ if (pflag->flgp != NULL)
+ return FALSE;
+ /* Found it. */
+ cl_matches++;
+ pflag->flgp = pf;
+ lnflg--;
+ break;
+ }
+ }
+ pf++;
+ }
+ }
+
+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+ {
+ const struct arc_flag_operand *flg_operand;
+
+ pflag = first_pflag;
+ flg_operand = &arc_flag_operands[*flgopridx];
+ for (i = 0; i < nflgs; i++, pflag++)
+ {
+ /* Match against the parsed flags. */
+ if (!strcmp (flg_operand->name, pflag->name))
+ {
+ if (pflag->flgp != NULL)
+ return FALSE;
+ cl_matches++;
+ pflag->flgp = flg_operand;
+ lnflg--;
+ break; /* goto next flag class and parsed flag. */
+ }
+ }
+ }
+
+ if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
+ return FALSE;
+ if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
+ return FALSE;
+ }
+
+ /* Did I check all the parsed flags? */
+ return lnflg ? FALSE : TRUE;
+}
+
+
/* Search forward through all variants of an opcode looking for a
syntax match. */
int *pntok,
struct arc_flags *first_pflag,
int nflgs,
- int *pcpumatch)
+ int *pcpumatch,
+ const char **errmsg)
{
const struct arc_opcode *opcode;
struct arc_opcode_hash_entry_iterator iter;
opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
{
const unsigned char *opidx;
- const unsigned char *flgidx;
- int tokidx = 0, lnflg, i;
+ int tokidx = 0;
const expressionS *t = &emptyE;
- pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
+ pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
frag_now->fr_file, frag_now->fr_line, opcode->opcode);
/* Don't match opcodes that don't exist on this
architecture. */
- if (!(opcode->cpu & arc_target))
+ if (!(opcode->cpu & selected_cpu.flags))
goto match_failed;
if (!check_cpu_feature (opcode->subclass))
const struct arc_operand *operand = &arc_operands[*opidx];
/* Only take input from real operands. */
- if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ if (ARC_OPERAND_IS_FAKE (operand))
continue;
/* When we expect input, make sure we have it. */
/* Match operand type with expression type. */
switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
{
+ case ARC_OPERAND_ADDRTYPE:
+ {
+ *errmsg = NULL;
+
+ /* Check to be an address type. */
+ if (tok[tokidx].X_op != O_addrtype)
+ goto match_failed;
+
+ /* All address type operands need to have an insert
+ method in order to check that we have the correct
+ address type. */
+ gas_assert (operand->insert != NULL);
+ (*operand->insert) (0, tok[tokidx].X_add_number,
+ errmsg);
+ if (*errmsg != NULL)
+ goto match_failed;
+ }
+ break;
+
case ARC_OPERAND_IR:
/* Check to be a register. */
if ((tok[tokidx].X_op != O_register
/* Special handling? */
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
regno (tok[tokidx].X_add_number),
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
{
if (operand->flags & ARC_OPERAND_IGNORE)
{
goto match_failed;
break;
+ case ARC_OPERAND_COLON:
+ /* Check if colon is also in opcode table as operand. */
+ if (tok[tokidx].X_op != O_colon)
+ goto match_failed;
+ break;
+
case ARC_OPERAND_LIMM:
case ARC_OPERAND_SIGNED:
case ARC_OPERAND_UNSIGNED:
const char *p;
const struct arc_aux_reg *auxr;
- if (opcode->class != AUXREG)
+ if (opcode->insn_class != AUXREG)
goto de_fault;
p = S_GET_NAME (tok[tokidx].X_add_symbol);
if (tok[tokidx].X_op != O_constant)
goto de_fault;
}
- /* Fall-through */
+ /* Fall through. */
case O_constant:
/* Check the range. */
if (operand->bits != 32
{
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
tok[tokidx].X_add_number,
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
goto match_failed;
}
- else
+ else if (!(operand->flags & ARC_OPERAND_IGNORE))
goto match_failed;
}
break;
regs |= get_register (tok[tokidx].X_op_symbol);
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
regs,
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
goto match_failed;
}
else
goto match_failed;
break;
}
+ /* Fall through. */
default:
de_fault:
if (operand->default_reloc == 0)
case O_tlsie:
if (!(operand->flags & ARC_OPERAND_LIMM))
goto match_failed;
+ /* Fall through. */
case O_absent:
if (!generic_reloc_p (operand->default_reloc))
goto match_failed;
+ break;
default:
break;
}
pr_debug ("opr ");
/* Setup ready for flag parsing. */
- lnflg = nflgs;
- for (i = 0; i < nflgs; i++)
- first_pflag[i].flgp = NULL;
-
- /* Check the flags. Iterate over the valid flag classes. */
- for (flgidx = opcode->flags; *flgidx; ++flgidx)
- {
- /* Get a valid flag class. */
- const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
- const unsigned *flgopridx;
- int cl_matches = 0;
- struct arc_flags *pflag = NULL;
-
- /* Check for extension conditional codes. */
- if (ext_condcode.arc_ext_condcode
- && cl_flags->class & F_CLASS_EXTEND)
- {
- struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
- while (pf->name)
- {
- pflag = first_pflag;
- for (i = 0; i < nflgs; i++, pflag++)
- {
- if (!strcmp (pf->name, pflag->name))
- {
- if (pflag->flgp != NULL)
- goto match_failed;
- /* Found it. */
- cl_matches++;
- pflag->flgp = pf;
- lnflg--;
- break;
- }
- }
- pf++;
- }
- }
-
- for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
- {
- const struct arc_flag_operand *flg_operand;
-
- pflag = first_pflag;
- flg_operand = &arc_flag_operands[*flgopridx];
- for (i = 0; i < nflgs; i++, pflag++)
- {
- /* Match against the parsed flags. */
- if (!strcmp (flg_operand->name, pflag->name))
- {
- if (pflag->flgp != NULL)
- goto match_failed;
- cl_matches++;
- pflag->flgp = (struct arc_flag_operand *) flg_operand;
- lnflg--;
- break; /* goto next flag class and parsed flag. */
- }
- }
- }
-
- if ((cl_flags->class & F_CLASS_REQUIRED) && cl_matches == 0)
- goto match_failed;
- if ((cl_flags->class & F_CLASS_OPTIONAL) && cl_matches > 1)
- goto match_failed;
- }
- /* Did I check all the parsed flags? */
- if (lnflg)
+ if (!parse_opcode_flags (opcode, nflgs, first_pflag))
goto match_failed;
pr_debug ("flg");
case O_symbol:
/* Handle all symbols as long immediates or signed 9. */
- if (operand_real->flags & ARC_OPERAND_LIMM ||
- ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
+ if (operand_real->flags & ARC_OPERAND_LIMM
+ || ((operand_real->flags & ARC_OPERAND_SIGNED)
+ && operand_real->bits == 9))
ret = TRUE;
break;
operand_pseudo = &pseudo_insn->operand[i];
operand_real = &arc_operands[operand_pseudo->operand_idx];
- if (operand_real->flags & ARC_OPERAND_BRAKET &&
- !operand_pseudo->needs_insert)
+ if (operand_real->flags & ARC_OPERAND_BRAKET
+ && !operand_pseudo->needs_insert)
continue;
/* Has to be inserted (i.e. this token does not exist yet). */
bfd_boolean found_something = FALSE;
const struct arc_opcode_hash_entry *entry;
int cpumatch = 1;
+ const char *errmsg = NULL;
/* Search opcodes. */
entry = arc_find_opcode (opname);
frag_now->fr_file, frag_now->fr_line, opname);
found_something = TRUE;
opcode = find_opcode_match (entry, tok, &ntok, pflags,
- nflgs, &cpumatch);
+ nflgs, &cpumatch, &errmsg);
if (opcode != NULL)
{
struct arc_insn insn;
if (found_something)
{
if (cpumatch)
- as_bad (_("inappropriate arguments for opcode '%s'"), opname);
+ if (errmsg)
+ as_bad (_("%s for instruction '%s'"), errmsg, opname);
+ else
+ as_bad (_("inappropriate arguments for opcode '%s'"), opname);
else
as_bad (_("opcode '%s' not supported for target %s"), opname,
- arc_target_name);
+ selected_cpu.name);
}
else
as_bad (_("unknown opcode '%s'"), opname);
}
}
+/* Construct a symbol for an address type. */
+
+static void
+declare_addrtype (const char *name, int number)
+{
+ const char *err;
+ symbolS *addrtypeS = symbol_create (name, undefined_section,
+ number, &zero_address_frag);
+
+ err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
+ (void *) addrtypeS);
+ if (err)
+ as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
+ name, err);
+}
+
/* Port-specific assembler initialization. This function is called
once, at assembler startup time. */
{
const struct arc_opcode *opcode = arc_opcodes;
- if (!mach_type_specified_p)
- arc_select_cpu ("arc700");
+ if (mach_selection_mode == MACH_SELECTION_NONE)
+ arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
+ if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
as_warn (_("could not set architecture and machine"));
/* Set elf header flags. */
- bfd_set_private_flags (stdoutput, arc_eflag);
+ bfd_set_private_flags (stdoutput, selected_cpu.eflags);
/* Set up a hash table for the instructions. */
arc_opcode_hash = hash_new ();
declare_register ("ilink2", 30);
declare_register ("blink", 31);
+ /* XY memory registers. */
+ declare_register ("x0_u0", 32);
+ declare_register ("x0_u1", 33);
+ declare_register ("x1_u0", 34);
+ declare_register ("x1_u1", 35);
+ declare_register ("x2_u0", 36);
+ declare_register ("x2_u1", 37);
+ declare_register ("x3_u0", 38);
+ declare_register ("x3_u1", 39);
+ declare_register ("y0_u0", 40);
+ declare_register ("y0_u1", 41);
+ declare_register ("y1_u0", 42);
+ declare_register ("y1_u1", 43);
+ declare_register ("y2_u0", 44);
+ declare_register ("y2_u1", 45);
+ declare_register ("y3_u0", 46);
+ declare_register ("y3_u1", 47);
+ declare_register ("x0_nu", 48);
+ declare_register ("x1_nu", 49);
+ declare_register ("x2_nu", 50);
+ declare_register ("x3_nu", 51);
+ declare_register ("y0_nu", 52);
+ declare_register ("y1_nu", 53);
+ declare_register ("y2_nu", 54);
+ declare_register ("y3_nu", 55);
+
declare_register ("mlo", 57);
declare_register ("mmid", 58);
declare_register ("mhi", 59);
{
const char *retval;
- if (!(auxr->cpu & arc_target))
+ if (!(auxr->cpu & selected_cpu.flags))
continue;
if ((auxr->subclass != NONE)
as_fatal (_("internal error: can't hash aux register '%s': %s"),
auxr->name, retval);
}
+
+ /* Address type declaration. */
+ arc_addrtype_hash = hash_new ();
+ if (arc_addrtype_hash == NULL)
+ as_fatal (_("Virtual memory exhausted"));
+
+ declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
+ declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
+ declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
+ declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
+ declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
+ declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
+ declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
+ declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
+ declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
+ declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
+ declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
+ declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
+ declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
+ declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
+ declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
+ declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
}
/* Write a value out to the object file, using the appropriate
/* The hardware calculates relative to the start of the
insn, but this relocation is relative to location of the
LIMM, compensate. The base always needs to be
- substracted by 4 as we do not support this type of PCrel
+ subtracted by 4 as we do not support this type of PCrel
relocation for short instructions. */
base -= 4;
/* Fall through. */
}
}
- pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
+ pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
+ "symbol: %s (%"BFD_VMA_FMT"x)\n",
fixP->fx_frag->fr_address, fixP->fx_where, base,
fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
/* Insert an operand value into an instruction. */
-static unsigned
-insert_operand (unsigned insn,
+static unsigned long long
+insert_operand (unsigned long long insn,
const struct arc_operand *operand,
- offsetT val,
+ long long val,
const char *file,
unsigned line)
{
val, min, max, file, line);
}
- pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
+ pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
min, val, max, insn);
if ((operand->flags & ARC_OPERAND_ALIGNED32)
bits of a 32-bit negative value read in by the parser are set,
so that the correct comparisons are made. */
if (value & 0x80000000)
- value |= (-1L << 31);
+ value |= (-1UL << 31);
reloc = fixP->fx_r_type;
switch (reloc)
case BFD_RELOC_ARC_TLS_LE_32:
gas_assert (!fixP->fx_addsy);
gas_assert (!fixP->fx_subsy);
+ /* Fall through. */
case BFD_RELOC_ARC_GOTOFF:
case BFD_RELOC_ARC_32_ME:
case BFD_RELOC_ARC_S21W_PCREL_PLT:
reloc = BFD_RELOC_ARC_S21W_PCREL;
+ /* Fall through. */
case BFD_RELOC_ARC_S25W_PCREL:
case BFD_RELOC_ARC_S21W_PCREL:
gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
- if (code == BFD_RELOC_ARC_TLS_DTPOFF
- || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
- {
- asymbol *sym
- = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
- /* We just want to store a 24 bit index, but we have to wait
- till after write_contents has been called via
- bfd_map_over_sections before we can get the index from
- _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
- function is elf32-arc.c has to pick up the slack.
- Unfortunately, this leads to problems with hosts that have
- pointers wider than long (bfd_vma). There would be various
- ways to handle this, all error-prone :-( */
- reloc->addend = (bfd_vma) sym;
- if ((asymbol *) reloc->addend != sym)
- {
- as_bad ("Can't store pointer\n");
- return NULL;
- }
- }
- else
- reloc->addend = fixP->fx_offset;
+ reloc->addend = fixP->fx_offset;
return reloc;
}
dest = fragP->fr_literal + fix;
table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
- pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
+ pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
+ "var: %"BFD_VMA_FMT"d\n",
fragP->fr_file, fragP->fr_line,
fragP->fr_subtype, fix, fragP->fr_var);
apply_fixups (&insn, fragP, fix);
- size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
+ size = insn.len + (insn.has_limm ? 4 : 0);
gas_assert (table_entry->rlx_length == size);
emit_insn0 (&insn, dest, TRUE);
if (!assembling_insn)
return FALSE;
- /* Handle only registers. */
- if (e->X_op != O_absent)
+ if (e->X_op == O_symbol)
return FALSE;
sym = hash_find (arc_reg_hash, name);
e->X_add_number = S_GET_VALUE (sym);
return TRUE;
}
+
+ sym = hash_find (arc_addrtype_hash, name);
+ if (sym)
+ {
+ e->X_op = O_addrtype;
+ e->X_add_number = S_GET_VALUE (sym);
+ return TRUE;
+ }
+
return FALSE;
}
-mrelax Enable relaxation
The following CPU names are recognized:
- arc700, av2em, av2hs. */
+ arc600, arc700, arcem, archs, nps400. */
int
md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- arc_select_cpu (arg);
- mach_type_specified_p = TRUE;
+ arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
break;
}
break;
case OPTION_CD:
- /* This option has an effect only on ARC EM. */
- if (arc_target & ARC_OPCODE_ARCv2EM)
- arc_features |= ARC_CD;
- else
- as_warn (_("Code density option invalid for selected CPU"));
+ selected_cpu.features |= ARC_CD;
+ arc_check_feature ();
break;
case OPTION_RELAX:
relaxation_state = 1;
break;
+ case OPTION_NPS400:
+ selected_cpu.features |= ARC_NPS400;
+ arc_check_feature ();
+ break;
+
+ case OPTION_SPFP:
+ selected_cpu.features |= ARC_SPFP;
+ arc_check_feature ();
+ break;
+
+ case OPTION_DPFP:
+ selected_cpu.features |= ARC_DPFP;
+ arc_check_feature ();
+ break;
+
+ case OPTION_FPUDA:
+ selected_cpu.features |= ARC_FPUDA;
+ arc_check_feature ();
+ break;
+
+ /* Dummy options are accepted but have no effect. */
case OPTION_USER_MODE:
case OPTION_LD_EXT_MASK:
case OPTION_SWAP:
case OPTION_EA:
case OPTION_MUL64:
case OPTION_SIMD:
- /* Dummy options are accepted but have no effect. */
- break;
-
- case OPTION_SPFP:
- arc_features |= ARC_SPFP;
- break;
-
- case OPTION_DPFP:
- arc_features |= ARC_DPFP;
- break;
-
case OPTION_XMAC_D16:
case OPTION_XMAC_24:
case OPTION_DSP_PACKA:
case OPTION_LOCK:
case OPTION_SWAPE:
case OPTION_RTSC:
- /* Dummy options are accepted but have no effect. */
- break;
-
- case OPTION_FPUDA:
- /* This option has an effect only on ARC EM. */
- if (arc_target & ARC_OPCODE_ARCv2EM)
- arc_features |= ARC_FPUDA;
- else
- as_warn (_("FPUDA invalid for selected CPU"));
break;
default:
{
fprintf (stream, _("ARC-specific assembler options:\n"));
- fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
+ fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
+ "(default: %s)\n", TARGET_WITH_CPU);
+ fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
+ fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
+ fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
+ fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
+ fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
+
+ fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
+ fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n");
+ fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n");
+ fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
+ "point\n\t\t\t instructions for ARC EM\n");
+
fprintf (stream,
" -mcode-density\t enable code density option for ARC EM\n");
fprintf (stream, _("\
-EL assemble code for a little-endian cpu\n"));
fprintf (stream, _("\
- -mrelax Enable relaxation\n"));
-
+ -mrelax enable relaxation\n"));
+
+ fprintf (stream, _("The following ARC-specific assembler options are "
+ "deprecated and are accepted\nfor compatibility only:\n"));
+
+ fprintf (stream, _(" -mEA\n"
+ " -mbarrel-shifter\n"
+ " -mbarrel_shifter\n"
+ " -mcrc\n"
+ " -mdsp-packa\n"
+ " -mdsp_packa\n"
+ " -mdvbf\n"
+ " -mld-extension-reg-mask\n"
+ " -mlock\n"
+ " -mmac-24\n"
+ " -mmac-d16\n"
+ " -mmac_24\n"
+ " -mmac_d16\n"
+ " -mmin-max\n"
+ " -mmin_max\n"
+ " -mmul64\n"
+ " -mno-mpy\n"
+ " -mnorm\n"
+ " -mrtsc\n"
+ " -msimd\n"
+ " -mswap\n"
+ " -mswape\n"
+ " -mtelephony\n"
+ " -muser-mode-only\n"
+ " -mxy\n"));
}
/* Find the proper relocation for the given opcode. */
struct arc_insn *insn)
{
const expressionS *reloc_exp = NULL;
- unsigned image;
+ unsigned long long image;
const unsigned char *argidx;
int i;
int tokidx = 0;
memset (insn, 0, sizeof (*insn));
image = opcode->opcode;
- pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
+ pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
frag_now->fr_file, frag_now->fr_line, opcode->name,
opcode->opcode);
const struct arc_operand *operand = &arc_operands[*argidx];
const expressionS *t = (const expressionS *) 0;
- if ((operand->flags & ARC_OPERAND_FAKE)
- && !(operand->flags & ARC_OPERAND_BRAKET))
+ if (ARC_OPERAND_IS_FAKE (operand))
continue;
if (operand->flags & ARC_OPERAND_DUPLICATE)
break;
case O_bracket:
- /* Ignore brackets. */
+ case O_colon:
+ case O_addrtype:
+ /* Ignore brackets, colons, and address types. */
break;
case O_absent:
image = insert_operand (image, operand, regs, NULL, 0);
break;
}
+ /* Fall through. */
default:
/* This operand needs a relocation. */
switch (t->X_md)
{
case O_plt:
- if (opcode->class == JUMP)
+ if (opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
_("Unable to use @plt relocatio for insn %s"),
opcode->name);
break;
case O_pcl:
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
- if (ARC_SHORT (opcode->mask) || opcode->class == JUMP)
+ if (arc_opcode_len (opcode) == 2
+ || opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
_("Unable to use @pcl relocation for insn %s"),
opcode->name);
insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
- /* Short instruction? */
- insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
+ /* Instruction length. */
+ insn->len = arc_opcode_len (opcode);
insn->insn = image;
static void
check_zol (symbolS *s)
{
- switch (arc_mach_type)
+ switch (selected_cpu.mach)
{
case bfd_mach_arc_arcv2:
- if (arc_target & ARC_OPCODE_ARCv2EM)
+ if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
return;
if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
end of the ZOL label @%s"), S_GET_NAME (s));
/* Fall through. */
- case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
if (arc_last_insns[0].has_delay_slot)
as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
tc_arc_frame_initial_instructions (void)
{
/* Stack pointer is register 28. */
- cfi_add_CFA_def_cfa_register (28);
+ cfi_add_CFA_def_cfa (28, 0);
}
int
if (!strncmp (suffixclass[i].name, input_line_pointer,
suffixclass[i].len))
{
- suffix_class |= suffixclass[i].class;
+ suffix_class |= suffixclass[i].attr_class;
input_line_pointer += suffixclass[i].len;
break;
}
input_line_pointer,
syntaxclassmod[i].len))
{
- syntax_class_modifiers |= syntaxclassmod[i].class;
+ syntax_class_modifiers |= syntaxclassmod[i].attr_class;
input_line_pointer += syntaxclassmod[i].len;
break;
}
input_line_pointer,
syntaxclass[i].len))
{
- syntax_class |= syntaxclass[i].class;
+ syntax_class |= syntaxclass[i].attr_class;
input_line_pointer += syntaxclass[i].len;
break;
}
/* Check the opcode ranges. */
moplow = 0x05;
- mophigh = (arc_target & (ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
+ mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
if ((einsn.major > mophigh) || (einsn.major < moplow))
as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
break;
}
- arc_ext_opcodes = arcExtMap_genOpcode (&einsn, arc_target, &errmsg);
+ arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
if (arc_ext_opcodes == NULL)
{
if (errmsg)
/* Auxiliary register. */
auxr = XNEW (struct arc_aux_reg);
auxr->name = ereg.name;
- auxr->cpu = arc_target;
+ auxr->cpu = selected_cpu.flags;
auxr->subclass = NONE;
auxr->address = ereg.number;
retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);