/* tc-arm.c -- Assemble for the ARM
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modified by David Taylor (dtaylor@armltd.co.uk)
#include "dwarf2dbg.h"
#endif
+/* XXX Set this to 1 after the next binutils release */
+#define WARN_DEPRECATED 0
+
/* The following bitmasks control CPU extensions: */
#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */
#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
-/* Processor specific extensions. */
-#define ARM_EXT_XSCALE 0x00000800 /* Allow MIA etc. */
-#define ARM_EXT_MAVERICK 0x00001000 /* Use Cirrus/DSP coprocessor. */
+#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
+#define ARM_EXT_V6 0x00001000 /* ARM V6. */
+
+/* Co-processor space extensions. */
+#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
+#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */
+#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP)
#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E)
+#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J)
+#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6)
+
/* Processors with specific extensions in the co-processor space. */
-#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
+#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
+#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
/* Some useful combinations: */
-#define ARM_ANY 0x00ffffff
-#define ARM_ALL ARM_ANY
+#define ARM_ANY 0x0000ffff /* Any basic core. */
+#define ARM_ALL 0x00ffffff /* Any core + co-processor */
+#define CPROC_ANY 0x00ff0000 /* Any co-processor */
+#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */
+
-#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */
-#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */
-#define FPU_NONE 0
+#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */
+#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */
+#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */
+#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
+#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
+#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
+#define FPU_NONE 0
#define FPU_ARCH_FPE FPU_FPA_EXT_V1
#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2)
-/* Some useful combinations. */
-#define FPU_ANY 0xff000000 /* Note this is ~ARM_ANY. */
+#define FPU_ARCH_VFP FPU_VFP_EXT_NONE
+#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
+#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
+#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
/* Types of processor to assemble for. */
#define ARM_1 ARM_ARCH_V1
#if defined __thumb__
#define CPU_DEFAULT (ARM_ARCH_V5T)
#else
-#define CPU_DEFAULT ARM_ALL
+#define CPU_DEFAULT ARM_ANY
+#endif
+#endif
+#endif
+
+#ifdef TE_LINUX
+#define FPU_DEFAULT FPU_ARCH_FPA
#endif
+
+#ifdef TE_NetBSD
+#ifdef OBJ_ELF
+#define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
+#else
+/* Legacy a.out format. */
+#define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
#endif
#endif
+/* For backwards compatibility we default to the FPA. */
#ifndef FPU_DEFAULT
#define FPU_DEFAULT FPU_ARCH_FPA
#endif
#define streq(a, b) (strcmp (a, b) == 0)
#define skip_whitespace(str) while (*(str) == ' ') ++(str)
-static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
+static unsigned long cpu_variant;
static int target_oabi = 0;
-#if defined OBJ_COFF || defined OBJ_ELF
/* Flags stored in private area of BFD structure. */
-static boolean uses_apcs_26 = false;
-static boolean atpcs = false;
-static boolean support_interwork = false;
-static boolean uses_apcs_float = false;
-static boolean pic_code = false;
-#endif
+static int uses_apcs_26 = FALSE;
+static int atpcs = FALSE;
+static int support_interwork = FALSE;
+static int uses_apcs_float = FALSE;
+static int pic_code = FALSE;
+
+/* Variables that we set while parsing command-line options. Once all
+ options have been read we re-process these values to set the real
+ assembly flags. */
+static int legacy_cpu = -1;
+static int legacy_fpu = -1;
+
+static int mcpu_cpu_opt = -1;
+static int mcpu_fpu_opt = -1;
+static int march_cpu_opt = -1;
+static int march_fpu_opt = -1;
+static int mfpu_opt = -1;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
{ "RRX", shift_properties + SHIFT_RRX }
};
+/* Any kind of shift is accepted. */
#define NO_SHIFT_RESTRICT 1
-#define SHIFT_RESTRICT 0
+/* The shift operand must be an immediate value, not a register. */
+#define SHIFT_IMMEDIATE 0
+/* The shift must be LSL or ASR and the operand must be an immediate. */
+#define SHIFT_LSL_OR_ASR_IMMEDIATE 2
+/* The shift must be ASR and the operand must be an immediate. */
+#define SHIFT_ASR_IMMEDIATE 3
+/* The shift must be LSL and the operand must be an immediate. */
+#define SHIFT_LSL_IMMEDIATE 4
#define NUM_FLOAT_VALS 8
#define FAIL (-1)
#define SUCCESS (0)
+/* Whether a Co-processor load/store operation accepts write-back forms. */
+#define CP_WB_OK 1
+#define CP_NO_WB 0
+
#define SUFF_S 1
#define SUFF_D 2
#define SUFF_E 3
struct asm_psr
{
- const char * template;
- boolean cpsr;
+ const char *template;
+ bfd_boolean cpsr;
unsigned long field;
};
-/* The bit that distnguishes CPSR and SPSR. */
+/* The bit that distinguishes CPSR and SPSR. */
#define SPSR_BIT (1 << 22)
/* How many bits to shift the PSR_xxx bits up by. */
static const struct asm_psr psrs[] =
{
- {"CPSR", true, PSR_c | PSR_f},
- {"CPSR_all", true, PSR_c | PSR_f},
- {"SPSR", false, PSR_c | PSR_f},
- {"SPSR_all", false, PSR_c | PSR_f},
- {"CPSR_flg", true, PSR_f},
- {"CPSR_f", true, PSR_f},
- {"SPSR_flg", false, PSR_f},
- {"SPSR_f", false, PSR_f},
- {"CPSR_c", true, PSR_c},
- {"CPSR_ctl", true, PSR_c},
- {"SPSR_c", false, PSR_c},
- {"SPSR_ctl", false, PSR_c},
- {"CPSR_x", true, PSR_x},
- {"CPSR_s", true, PSR_s},
- {"SPSR_x", false, PSR_x},
- {"SPSR_s", false, PSR_s},
+ {"CPSR", TRUE, PSR_c | PSR_f},
+ {"CPSR_all", TRUE, PSR_c | PSR_f},
+ {"SPSR", FALSE, PSR_c | PSR_f},
+ {"SPSR_all", FALSE, PSR_c | PSR_f},
+ {"CPSR_flg", TRUE, PSR_f},
+ {"CPSR_f", TRUE, PSR_f},
+ {"SPSR_flg", FALSE, PSR_f},
+ {"SPSR_f", FALSE, PSR_f},
+ {"CPSR_c", TRUE, PSR_c},
+ {"CPSR_ctl", TRUE, PSR_c},
+ {"SPSR_c", FALSE, PSR_c},
+ {"SPSR_ctl", FALSE, PSR_c},
+ {"CPSR_x", TRUE, PSR_x},
+ {"CPSR_s", TRUE, PSR_s},
+ {"SPSR_x", FALSE, PSR_x},
+ {"SPSR_s", FALSE, PSR_s},
/* Combinations of flags. */
- {"CPSR_fs", true, PSR_f | PSR_s},
- {"CPSR_fx", true, PSR_f | PSR_x},
- {"CPSR_fc", true, PSR_f | PSR_c},
- {"CPSR_sf", true, PSR_s | PSR_f},
- {"CPSR_sx", true, PSR_s | PSR_x},
- {"CPSR_sc", true, PSR_s | PSR_c},
- {"CPSR_xf", true, PSR_x | PSR_f},
- {"CPSR_xs", true, PSR_x | PSR_s},
- {"CPSR_xc", true, PSR_x | PSR_c},
- {"CPSR_cf", true, PSR_c | PSR_f},
- {"CPSR_cs", true, PSR_c | PSR_s},
- {"CPSR_cx", true, PSR_c | PSR_x},
- {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
- {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
- {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
- {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
- {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
- {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
- {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
- {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
- {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
- {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
- {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
- {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
- {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
- {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
- {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
- {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
- {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
- {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
- {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
- {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
- {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
- {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
- {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
- {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
- {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
- {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
- {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
- {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
- {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
- {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
- {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
- {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
- {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
- {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
- {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
- {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
- {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
- {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
- {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
- {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
- {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
- {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
- {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
- {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
- {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
- {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
- {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
- {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
- {"SPSR_fs", false, PSR_f | PSR_s},
- {"SPSR_fx", false, PSR_f | PSR_x},
- {"SPSR_fc", false, PSR_f | PSR_c},
- {"SPSR_sf", false, PSR_s | PSR_f},
- {"SPSR_sx", false, PSR_s | PSR_x},
- {"SPSR_sc", false, PSR_s | PSR_c},
- {"SPSR_xf", false, PSR_x | PSR_f},
- {"SPSR_xs", false, PSR_x | PSR_s},
- {"SPSR_xc", false, PSR_x | PSR_c},
- {"SPSR_cf", false, PSR_c | PSR_f},
- {"SPSR_cs", false, PSR_c | PSR_s},
- {"SPSR_cx", false, PSR_c | PSR_x},
- {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
- {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
- {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
- {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
- {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
- {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
- {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
- {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
- {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
- {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
- {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
- {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
- {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
- {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
- {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
- {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
- {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
- {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
- {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
- {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
- {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
- {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
- {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
- {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
- {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
- {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
- {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
- {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
- {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
- {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
- {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
- {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
- {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
- {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
- {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
- {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
- {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
- {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
- {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
- {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
- {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
- {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
- {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
- {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
- {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
- {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
- {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
- {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
+ {"CPSR_fs", TRUE, PSR_f | PSR_s},
+ {"CPSR_fx", TRUE, PSR_f | PSR_x},
+ {"CPSR_fc", TRUE, PSR_f | PSR_c},
+ {"CPSR_sf", TRUE, PSR_s | PSR_f},
+ {"CPSR_sx", TRUE, PSR_s | PSR_x},
+ {"CPSR_sc", TRUE, PSR_s | PSR_c},
+ {"CPSR_xf", TRUE, PSR_x | PSR_f},
+ {"CPSR_xs", TRUE, PSR_x | PSR_s},
+ {"CPSR_xc", TRUE, PSR_x | PSR_c},
+ {"CPSR_cf", TRUE, PSR_c | PSR_f},
+ {"CPSR_cs", TRUE, PSR_c | PSR_s},
+ {"CPSR_cx", TRUE, PSR_c | PSR_x},
+ {"CPSR_fsx", TRUE, PSR_f | PSR_s | PSR_x},
+ {"CPSR_fsc", TRUE, PSR_f | PSR_s | PSR_c},
+ {"CPSR_fxs", TRUE, PSR_f | PSR_x | PSR_s},
+ {"CPSR_fxc", TRUE, PSR_f | PSR_x | PSR_c},
+ {"CPSR_fcs", TRUE, PSR_f | PSR_c | PSR_s},
+ {"CPSR_fcx", TRUE, PSR_f | PSR_c | PSR_x},
+ {"CPSR_sfx", TRUE, PSR_s | PSR_f | PSR_x},
+ {"CPSR_sfc", TRUE, PSR_s | PSR_f | PSR_c},
+ {"CPSR_sxf", TRUE, PSR_s | PSR_x | PSR_f},
+ {"CPSR_sxc", TRUE, PSR_s | PSR_x | PSR_c},
+ {"CPSR_scf", TRUE, PSR_s | PSR_c | PSR_f},
+ {"CPSR_scx", TRUE, PSR_s | PSR_c | PSR_x},
+ {"CPSR_xfs", TRUE, PSR_x | PSR_f | PSR_s},
+ {"CPSR_xfc", TRUE, PSR_x | PSR_f | PSR_c},
+ {"CPSR_xsf", TRUE, PSR_x | PSR_s | PSR_f},
+ {"CPSR_xsc", TRUE, PSR_x | PSR_s | PSR_c},
+ {"CPSR_xcf", TRUE, PSR_x | PSR_c | PSR_f},
+ {"CPSR_xcs", TRUE, PSR_x | PSR_c | PSR_s},
+ {"CPSR_cfs", TRUE, PSR_c | PSR_f | PSR_s},
+ {"CPSR_cfx", TRUE, PSR_c | PSR_f | PSR_x},
+ {"CPSR_csf", TRUE, PSR_c | PSR_s | PSR_f},
+ {"CPSR_csx", TRUE, PSR_c | PSR_s | PSR_x},
+ {"CPSR_cxf", TRUE, PSR_c | PSR_x | PSR_f},
+ {"CPSR_cxs", TRUE, PSR_c | PSR_x | PSR_s},
+ {"CPSR_fsxc", TRUE, PSR_f | PSR_s | PSR_x | PSR_c},
+ {"CPSR_fscx", TRUE, PSR_f | PSR_s | PSR_c | PSR_x},
+ {"CPSR_fxsc", TRUE, PSR_f | PSR_x | PSR_s | PSR_c},
+ {"CPSR_fxcs", TRUE, PSR_f | PSR_x | PSR_c | PSR_s},
+ {"CPSR_fcsx", TRUE, PSR_f | PSR_c | PSR_s | PSR_x},
+ {"CPSR_fcxs", TRUE, PSR_f | PSR_c | PSR_x | PSR_s},
+ {"CPSR_sfxc", TRUE, PSR_s | PSR_f | PSR_x | PSR_c},
+ {"CPSR_sfcx", TRUE, PSR_s | PSR_f | PSR_c | PSR_x},
+ {"CPSR_sxfc", TRUE, PSR_s | PSR_x | PSR_f | PSR_c},
+ {"CPSR_sxcf", TRUE, PSR_s | PSR_x | PSR_c | PSR_f},
+ {"CPSR_scfx", TRUE, PSR_s | PSR_c | PSR_f | PSR_x},
+ {"CPSR_scxf", TRUE, PSR_s | PSR_c | PSR_x | PSR_f},
+ {"CPSR_xfsc", TRUE, PSR_x | PSR_f | PSR_s | PSR_c},
+ {"CPSR_xfcs", TRUE, PSR_x | PSR_f | PSR_c | PSR_s},
+ {"CPSR_xsfc", TRUE, PSR_x | PSR_s | PSR_f | PSR_c},
+ {"CPSR_xscf", TRUE, PSR_x | PSR_s | PSR_c | PSR_f},
+ {"CPSR_xcfs", TRUE, PSR_x | PSR_c | PSR_f | PSR_s},
+ {"CPSR_xcsf", TRUE, PSR_x | PSR_c | PSR_s | PSR_f},
+ {"CPSR_cfsx", TRUE, PSR_c | PSR_f | PSR_s | PSR_x},
+ {"CPSR_cfxs", TRUE, PSR_c | PSR_f | PSR_x | PSR_s},
+ {"CPSR_csfx", TRUE, PSR_c | PSR_s | PSR_f | PSR_x},
+ {"CPSR_csxf", TRUE, PSR_c | PSR_s | PSR_x | PSR_f},
+ {"CPSR_cxfs", TRUE, PSR_c | PSR_x | PSR_f | PSR_s},
+ {"CPSR_cxsf", TRUE, PSR_c | PSR_x | PSR_s | PSR_f},
+ {"SPSR_fs", FALSE, PSR_f | PSR_s},
+ {"SPSR_fx", FALSE, PSR_f | PSR_x},
+ {"SPSR_fc", FALSE, PSR_f | PSR_c},
+ {"SPSR_sf", FALSE, PSR_s | PSR_f},
+ {"SPSR_sx", FALSE, PSR_s | PSR_x},
+ {"SPSR_sc", FALSE, PSR_s | PSR_c},
+ {"SPSR_xf", FALSE, PSR_x | PSR_f},
+ {"SPSR_xs", FALSE, PSR_x | PSR_s},
+ {"SPSR_xc", FALSE, PSR_x | PSR_c},
+ {"SPSR_cf", FALSE, PSR_c | PSR_f},
+ {"SPSR_cs", FALSE, PSR_c | PSR_s},
+ {"SPSR_cx", FALSE, PSR_c | PSR_x},
+ {"SPSR_fsx", FALSE, PSR_f | PSR_s | PSR_x},
+ {"SPSR_fsc", FALSE, PSR_f | PSR_s | PSR_c},
+ {"SPSR_fxs", FALSE, PSR_f | PSR_x | PSR_s},
+ {"SPSR_fxc", FALSE, PSR_f | PSR_x | PSR_c},
+ {"SPSR_fcs", FALSE, PSR_f | PSR_c | PSR_s},
+ {"SPSR_fcx", FALSE, PSR_f | PSR_c | PSR_x},
+ {"SPSR_sfx", FALSE, PSR_s | PSR_f | PSR_x},
+ {"SPSR_sfc", FALSE, PSR_s | PSR_f | PSR_c},
+ {"SPSR_sxf", FALSE, PSR_s | PSR_x | PSR_f},
+ {"SPSR_sxc", FALSE, PSR_s | PSR_x | PSR_c},
+ {"SPSR_scf", FALSE, PSR_s | PSR_c | PSR_f},
+ {"SPSR_scx", FALSE, PSR_s | PSR_c | PSR_x},
+ {"SPSR_xfs", FALSE, PSR_x | PSR_f | PSR_s},
+ {"SPSR_xfc", FALSE, PSR_x | PSR_f | PSR_c},
+ {"SPSR_xsf", FALSE, PSR_x | PSR_s | PSR_f},
+ {"SPSR_xsc", FALSE, PSR_x | PSR_s | PSR_c},
+ {"SPSR_xcf", FALSE, PSR_x | PSR_c | PSR_f},
+ {"SPSR_xcs", FALSE, PSR_x | PSR_c | PSR_s},
+ {"SPSR_cfs", FALSE, PSR_c | PSR_f | PSR_s},
+ {"SPSR_cfx", FALSE, PSR_c | PSR_f | PSR_x},
+ {"SPSR_csf", FALSE, PSR_c | PSR_s | PSR_f},
+ {"SPSR_csx", FALSE, PSR_c | PSR_s | PSR_x},
+ {"SPSR_cxf", FALSE, PSR_c | PSR_x | PSR_f},
+ {"SPSR_cxs", FALSE, PSR_c | PSR_x | PSR_s},
+ {"SPSR_fsxc", FALSE, PSR_f | PSR_s | PSR_x | PSR_c},
+ {"SPSR_fscx", FALSE, PSR_f | PSR_s | PSR_c | PSR_x},
+ {"SPSR_fxsc", FALSE, PSR_f | PSR_x | PSR_s | PSR_c},
+ {"SPSR_fxcs", FALSE, PSR_f | PSR_x | PSR_c | PSR_s},
+ {"SPSR_fcsx", FALSE, PSR_f | PSR_c | PSR_s | PSR_x},
+ {"SPSR_fcxs", FALSE, PSR_f | PSR_c | PSR_x | PSR_s},
+ {"SPSR_sfxc", FALSE, PSR_s | PSR_f | PSR_x | PSR_c},
+ {"SPSR_sfcx", FALSE, PSR_s | PSR_f | PSR_c | PSR_x},
+ {"SPSR_sxfc", FALSE, PSR_s | PSR_x | PSR_f | PSR_c},
+ {"SPSR_sxcf", FALSE, PSR_s | PSR_x | PSR_c | PSR_f},
+ {"SPSR_scfx", FALSE, PSR_s | PSR_c | PSR_f | PSR_x},
+ {"SPSR_scxf", FALSE, PSR_s | PSR_c | PSR_x | PSR_f},
+ {"SPSR_xfsc", FALSE, PSR_x | PSR_f | PSR_s | PSR_c},
+ {"SPSR_xfcs", FALSE, PSR_x | PSR_f | PSR_c | PSR_s},
+ {"SPSR_xsfc", FALSE, PSR_x | PSR_s | PSR_f | PSR_c},
+ {"SPSR_xscf", FALSE, PSR_x | PSR_s | PSR_c | PSR_f},
+ {"SPSR_xcfs", FALSE, PSR_x | PSR_c | PSR_f | PSR_s},
+ {"SPSR_xcsf", FALSE, PSR_x | PSR_c | PSR_s | PSR_f},
+ {"SPSR_cfsx", FALSE, PSR_c | PSR_f | PSR_s | PSR_x},
+ {"SPSR_cfxs", FALSE, PSR_c | PSR_f | PSR_x | PSR_s},
+ {"SPSR_csfx", FALSE, PSR_c | PSR_s | PSR_f | PSR_x},
+ {"SPSR_csxf", FALSE, PSR_c | PSR_s | PSR_x | PSR_f},
+ {"SPSR_cxfs", FALSE, PSR_c | PSR_x | PSR_f | PSR_s},
+ {"SPSR_cxsf", FALSE, PSR_c | PSR_x | PSR_s | PSR_f},
};
-enum cirrus_regtype
+enum wreg_type
{
- CIRRUS_REGTYPE_MVF = 1,
- CIRRUS_REGTYPE_MVFX = 2,
- CIRRUS_REGTYPE_MVD = 3,
- CIRRUS_REGTYPE_MVDX = 4,
- CIRRUS_REGTYPE_MVAX = 5,
- CIRRUS_REGTYPE_DSPSC = 6,
- CIRRUS_REGTYPE_ANY = 7
+ IWMMXT_REG_WR = 0,
+ IWMMXT_REG_WC = 1,
+ IWMMXT_REG_WR_OR_WC = 2,
+ IWMMXT_REG_WCG
};
+enum iwmmxt_insn_type
+{
+ check_rd,
+ check_wr,
+ check_wrwr,
+ check_wrwrwr,
+ check_wrwrwcg,
+ check_tbcst,
+ check_tmovmsk,
+ check_tmia,
+ check_tmcrr,
+ check_tmrrc,
+ check_tmcr,
+ check_tmrc,
+ check_tinsr,
+ check_textrc,
+ check_waligni,
+ check_textrm,
+ check_wshufh
+};
+
+enum vfp_dp_reg_pos
+{
+ VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
+};
+
+enum vfp_sp_reg_pos
+{
+ VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
+};
+
+enum vfp_ldstm_type
+{
+ VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
+};
+
+/* VFP system registers. */
+struct vfp_reg
+{
+ const char *name;
+ unsigned long regno;
+};
+
+static const struct vfp_reg vfp_regs[] =
+{
+ {"fpsid", 0x00000000},
+ {"FPSID", 0x00000000},
+ {"fpscr", 0x00010000},
+ {"FPSCR", 0x00010000},
+ {"fpexc", 0x00080000},
+ {"FPEXC", 0x00080000}
+};
+
+/* Structure for a hash table entry for a register. */
+struct reg_entry
+{
+ const char * name;
+ int number;
+ bfd_boolean builtin;
+};
+
+/* Some well known registers that we refer to directly elsewhere. */
+#define REG_SP 13
+#define REG_LR 14
+#define REG_PC 15
+
+#define wr_register(reg) ((reg ^ WR_PREFIX) >= 0 && (reg ^ WR_PREFIX) <= 15)
+#define wc_register(reg) ((reg ^ WC_PREFIX) >= 0 && (reg ^ WC_PREFIX) <= 15)
+#define wcg_register(reg) ((reg ^ WC_PREFIX) >= 8 && (reg ^ WC_PREFIX) <= 11)
+
+/* These are the standard names. Users can add aliases with .req.
+ and delete them with .unreq. */
+
+/* Integer Register Numbers. */
+static const struct reg_entry rn_table[] =
+{
+ {"r0", 0, TRUE}, {"r1", 1, TRUE}, {"r2", 2, TRUE}, {"r3", 3, TRUE},
+ {"r4", 4, TRUE}, {"r5", 5, TRUE}, {"r6", 6, TRUE}, {"r7", 7, TRUE},
+ {"r8", 8, TRUE}, {"r9", 9, TRUE}, {"r10", 10, TRUE}, {"r11", 11, TRUE},
+ {"r12", 12, TRUE}, {"r13", REG_SP, TRUE}, {"r14", REG_LR, TRUE}, {"r15", REG_PC, TRUE},
+ /* ATPCS Synonyms. */
+ {"a1", 0, TRUE}, {"a2", 1, TRUE}, {"a3", 2, TRUE}, {"a4", 3, TRUE},
+ {"v1", 4, TRUE}, {"v2", 5, TRUE}, {"v3", 6, TRUE}, {"v4", 7, TRUE},
+ {"v5", 8, TRUE}, {"v6", 9, TRUE}, {"v7", 10, TRUE}, {"v8", 11, TRUE},
+ /* Well-known aliases. */
+ {"wr", 7, TRUE}, {"sb", 9, TRUE}, {"sl", 10, TRUE}, {"fp", 11, TRUE},
+ {"ip", 12, TRUE}, {"sp", REG_SP, TRUE}, {"lr", REG_LR, TRUE}, {"pc", REG_PC, TRUE},
+ {NULL, 0, TRUE}
+};
+
+#define WR_PREFIX 0x200
+#define WC_PREFIX 0x400
+
+static const struct reg_entry iwmmxt_table[] =
+{
+ /* Intel Wireless MMX technology register names. */
+ { "wr0", 0x0 | WR_PREFIX, TRUE}, {"wr1", 0x1 | WR_PREFIX, TRUE},
+ { "wr2", 0x2 | WR_PREFIX, TRUE}, {"wr3", 0x3 | WR_PREFIX, TRUE},
+ { "wr4", 0x4 | WR_PREFIX, TRUE}, {"wr5", 0x5 | WR_PREFIX, TRUE},
+ { "wr6", 0x6 | WR_PREFIX, TRUE}, {"wr7", 0x7 | WR_PREFIX, TRUE},
+ { "wr8", 0x8 | WR_PREFIX, TRUE}, {"wr9", 0x9 | WR_PREFIX, TRUE},
+ { "wr10", 0xa | WR_PREFIX, TRUE}, {"wr11", 0xb | WR_PREFIX, TRUE},
+ { "wr12", 0xc | WR_PREFIX, TRUE}, {"wr13", 0xd | WR_PREFIX, TRUE},
+ { "wr14", 0xe | WR_PREFIX, TRUE}, {"wr15", 0xf | WR_PREFIX, TRUE},
+ { "wcid", 0x0 | WC_PREFIX, TRUE}, {"wcon", 0x1 | WC_PREFIX, TRUE},
+ {"wcssf", 0x2 | WC_PREFIX, TRUE}, {"wcasf", 0x3 | WC_PREFIX, TRUE},
+ {"wcgr0", 0x8 | WC_PREFIX, TRUE}, {"wcgr1", 0x9 | WC_PREFIX, TRUE},
+ {"wcgr2", 0xa | WC_PREFIX, TRUE}, {"wcgr3", 0xb | WC_PREFIX, TRUE},
+
+ { "wR0", 0x0 | WR_PREFIX, TRUE}, {"wR1", 0x1 | WR_PREFIX, TRUE},
+ { "wR2", 0x2 | WR_PREFIX, TRUE}, {"wR3", 0x3 | WR_PREFIX, TRUE},
+ { "wR4", 0x4 | WR_PREFIX, TRUE}, {"wR5", 0x5 | WR_PREFIX, TRUE},
+ { "wR6", 0x6 | WR_PREFIX, TRUE}, {"wR7", 0x7 | WR_PREFIX, TRUE},
+ { "wR8", 0x8 | WR_PREFIX, TRUE}, {"wR9", 0x9 | WR_PREFIX, TRUE},
+ { "wR10", 0xa | WR_PREFIX, TRUE}, {"wR11", 0xb | WR_PREFIX, TRUE},
+ { "wR12", 0xc | WR_PREFIX, TRUE}, {"wR13", 0xd | WR_PREFIX, TRUE},
+ { "wR14", 0xe | WR_PREFIX, TRUE}, {"wR15", 0xf | WR_PREFIX, TRUE},
+ { "wCID", 0x0 | WC_PREFIX, TRUE}, {"wCon", 0x1 | WC_PREFIX, TRUE},
+ {"wCSSF", 0x2 | WC_PREFIX, TRUE}, {"wCASF", 0x3 | WC_PREFIX, TRUE},
+ {"wCGR0", 0x8 | WC_PREFIX, TRUE}, {"wCGR1", 0x9 | WC_PREFIX, TRUE},
+ {"wCGR2", 0xa | WC_PREFIX, TRUE}, {"wCGR3", 0xb | WC_PREFIX, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* Co-processor Numbers. */
+static const struct reg_entry cp_table[] =
+{
+ {"p0", 0, TRUE}, {"p1", 1, TRUE}, {"p2", 2, TRUE}, {"p3", 3, TRUE},
+ {"p4", 4, TRUE}, {"p5", 5, TRUE}, {"p6", 6, TRUE}, {"p7", 7, TRUE},
+ {"p8", 8, TRUE}, {"p9", 9, TRUE}, {"p10", 10, TRUE}, {"p11", 11, TRUE},
+ {"p12", 12, TRUE}, {"p13", 13, TRUE}, {"p14", 14, TRUE}, {"p15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* Co-processor Register Numbers. */
+static const struct reg_entry cn_table[] =
+{
+ {"c0", 0, TRUE}, {"c1", 1, TRUE}, {"c2", 2, TRUE}, {"c3", 3, TRUE},
+ {"c4", 4, TRUE}, {"c5", 5, TRUE}, {"c6", 6, TRUE}, {"c7", 7, TRUE},
+ {"c8", 8, TRUE}, {"c9", 9, TRUE}, {"c10", 10, TRUE}, {"c11", 11, TRUE},
+ {"c12", 12, TRUE}, {"c13", 13, TRUE}, {"c14", 14, TRUE}, {"c15", 15, TRUE},
+ /* Not really valid, but kept for back-wards compatibility. */
+ {"cr0", 0, TRUE}, {"cr1", 1, TRUE}, {"cr2", 2, TRUE}, {"cr3", 3, TRUE},
+ {"cr4", 4, TRUE}, {"cr5", 5, TRUE}, {"cr6", 6, TRUE}, {"cr7", 7, TRUE},
+ {"cr8", 8, TRUE}, {"cr9", 9, TRUE}, {"cr10", 10, TRUE}, {"cr11", 11, TRUE},
+ {"cr12", 12, TRUE}, {"cr13", 13, TRUE}, {"cr14", 14, TRUE}, {"cr15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* FPA Registers. */
+static const struct reg_entry fn_table[] =
+{
+ {"f0", 0, TRUE}, {"f1", 1, TRUE}, {"f2", 2, TRUE}, {"f3", 3, TRUE},
+ {"f4", 4, TRUE}, {"f5", 5, TRUE}, {"f6", 6, TRUE}, {"f7", 7, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* VFP SP Registers. */
+static const struct reg_entry sn_table[] =
+{
+ {"s0", 0, TRUE}, {"s1", 1, TRUE}, {"s2", 2, TRUE}, {"s3", 3, TRUE},
+ {"s4", 4, TRUE}, {"s5", 5, TRUE}, {"s6", 6, TRUE}, {"s7", 7, TRUE},
+ {"s8", 8, TRUE}, {"s9", 9, TRUE}, {"s10", 10, TRUE}, {"s11", 11, TRUE},
+ {"s12", 12, TRUE}, {"s13", 13, TRUE}, {"s14", 14, TRUE}, {"s15", 15, TRUE},
+ {"s16", 16, TRUE}, {"s17", 17, TRUE}, {"s18", 18, TRUE}, {"s19", 19, TRUE},
+ {"s20", 20, TRUE}, {"s21", 21, TRUE}, {"s22", 22, TRUE}, {"s23", 23, TRUE},
+ {"s24", 24, TRUE}, {"s25", 25, TRUE}, {"s26", 26, TRUE}, {"s27", 27, TRUE},
+ {"s28", 28, TRUE}, {"s29", 29, TRUE}, {"s30", 30, TRUE}, {"s31", 31, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* VFP DP Registers. */
+static const struct reg_entry dn_table[] =
+{
+ {"d0", 0, TRUE}, {"d1", 1, TRUE}, {"d2", 2, TRUE}, {"d3", 3, TRUE},
+ {"d4", 4, TRUE}, {"d5", 5, TRUE}, {"d6", 6, TRUE}, {"d7", 7, TRUE},
+ {"d8", 8, TRUE}, {"d9", 9, TRUE}, {"d10", 10, TRUE}, {"d11", 11, TRUE},
+ {"d12", 12, TRUE}, {"d13", 13, TRUE}, {"d14", 14, TRUE}, {"d15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+/* Maverick DSP coprocessor registers. */
+static const struct reg_entry mav_mvf_table[] =
+{
+ {"mvf0", 0, TRUE}, {"mvf1", 1, TRUE}, {"mvf2", 2, TRUE}, {"mvf3", 3, TRUE},
+ {"mvf4", 4, TRUE}, {"mvf5", 5, TRUE}, {"mvf6", 6, TRUE}, {"mvf7", 7, TRUE},
+ {"mvf8", 8, TRUE}, {"mvf9", 9, TRUE}, {"mvf10", 10, TRUE}, {"mvf11", 11, TRUE},
+ {"mvf12", 12, TRUE}, {"mvf13", 13, TRUE}, {"mvf14", 14, TRUE}, {"mvf15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+static const struct reg_entry mav_mvd_table[] =
+{
+ {"mvd0", 0, TRUE}, {"mvd1", 1, TRUE}, {"mvd2", 2, TRUE}, {"mvd3", 3, TRUE},
+ {"mvd4", 4, TRUE}, {"mvd5", 5, TRUE}, {"mvd6", 6, TRUE}, {"mvd7", 7, TRUE},
+ {"mvd8", 8, TRUE}, {"mvd9", 9, TRUE}, {"mvd10", 10, TRUE}, {"mvd11", 11, TRUE},
+ {"mvd12", 12, TRUE}, {"mvd13", 13, TRUE}, {"mvd14", 14, TRUE}, {"mvd15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+static const struct reg_entry mav_mvfx_table[] =
+{
+ {"mvfx0", 0, TRUE}, {"mvfx1", 1, TRUE}, {"mvfx2", 2, TRUE}, {"mvfx3", 3, TRUE},
+ {"mvfx4", 4, TRUE}, {"mvfx5", 5, TRUE}, {"mvfx6", 6, TRUE}, {"mvfx7", 7, TRUE},
+ {"mvfx8", 8, TRUE}, {"mvfx9", 9, TRUE}, {"mvfx10", 10, TRUE}, {"mvfx11", 11, TRUE},
+ {"mvfx12", 12, TRUE}, {"mvfx13", 13, TRUE}, {"mvfx14", 14, TRUE}, {"mvfx15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+static const struct reg_entry mav_mvdx_table[] =
+{
+ {"mvdx0", 0, TRUE}, {"mvdx1", 1, TRUE}, {"mvdx2", 2, TRUE}, {"mvdx3", 3, TRUE},
+ {"mvdx4", 4, TRUE}, {"mvdx5", 5, TRUE}, {"mvdx6", 6, TRUE}, {"mvdx7", 7, TRUE},
+ {"mvdx8", 8, TRUE}, {"mvdx9", 9, TRUE}, {"mvdx10", 10, TRUE}, {"mvdx11", 11, TRUE},
+ {"mvdx12", 12, TRUE}, {"mvdx13", 13, TRUE}, {"mvdx14", 14, TRUE}, {"mvdx15", 15, TRUE},
+ {NULL, 0, TRUE}
+};
+
+static const struct reg_entry mav_mvax_table[] =
+{
+ {"mvax0", 0, TRUE}, {"mvax1", 1, TRUE}, {"mvax2", 2, TRUE}, {"mvax3", 3, TRUE},
+ {NULL, 0, TRUE}
+};
+
+static const struct reg_entry mav_dspsc_table[] =
+{
+ {"dspsc", 0, TRUE},
+ {NULL, 0, TRUE}
+};
+
+struct reg_map
+{
+ const struct reg_entry *names;
+ int max_regno;
+ struct hash_control *htab;
+ const char *expected;
+};
+
+struct reg_map all_reg_maps[] =
+{
+ {rn_table, 15, NULL, N_("ARM register expected")},
+ {cp_table, 15, NULL, N_("bad or missing co-processor number")},
+ {cn_table, 15, NULL, N_("co-processor register expected")},
+ {fn_table, 7, NULL, N_("FPA register expected")},
+ {sn_table, 31, NULL, N_("VFP single precision register expected")},
+ {dn_table, 15, NULL, N_("VFP double precision register expected")},
+ {mav_mvf_table, 15, NULL, N_("Maverick MVF register expected")},
+ {mav_mvd_table, 15, NULL, N_("Maverick MVD register expected")},
+ {mav_mvfx_table, 15, NULL, N_("Maverick MVFX register expected")},
+ {mav_mvdx_table, 15, NULL, N_("Maverick MVDX register expected")},
+ {mav_mvax_table, 3, NULL, N_("Maverick MVAX register expected")},
+ {mav_dspsc_table, 0, NULL, N_("Maverick DSPSC register expected")},
+ {iwmmxt_table, 23, NULL, N_("Intel Wireless MMX technology register expected")},
+};
+
+/* Enumeration matching entries in table above. */
+enum arm_reg_type
+{
+ REG_TYPE_RN = 0,
+#define REG_TYPE_FIRST REG_TYPE_RN
+ REG_TYPE_CP = 1,
+ REG_TYPE_CN = 2,
+ REG_TYPE_FN = 3,
+ REG_TYPE_SN = 4,
+ REG_TYPE_DN = 5,
+ REG_TYPE_MVF = 6,
+ REG_TYPE_MVD = 7,
+ REG_TYPE_MVFX = 8,
+ REG_TYPE_MVDX = 9,
+ REG_TYPE_MVAX = 10,
+ REG_TYPE_DSPSC = 11,
+ REG_TYPE_IWMMXT = 12,
+
+ REG_TYPE_MAX = 13
+};
+
/* Functions called by parser. */
/* ARM instructions. */
static void do_arit PARAMS ((char *));
/* ARM v4T. */
static void do_bx PARAMS ((char *));
-/* ARM v5. */
+/* ARM v5T. */
static void do_blx PARAMS ((char *));
static void do_bkpt PARAMS ((char *));
static void do_clz PARAMS ((char *));
static void do_cdp2 PARAMS ((char *));
static void do_co_reg2 PARAMS ((char *));
-/* ARM v5ExP. */
+/* ARM v5TExP. */
static void do_smla PARAMS ((char *));
static void do_smlal PARAMS ((char *));
static void do_smul PARAMS ((char *));
static void do_qadd PARAMS ((char *));
-/* ARM v5E. */
+/* ARM v5TE. */
static void do_pld PARAMS ((char *));
static void do_ldrd PARAMS ((char *));
static void do_co_reg2c PARAMS ((char *));
+/* ARM v5TEJ. */
+static void do_bxj PARAMS ((char *));
+
+/* ARM V6. */
+static void do_cps PARAMS ((char *));
+static void do_cpsi PARAMS ((char *));
+static void do_ldrex PARAMS ((char *));
+static void do_pkhbt PARAMS ((char *));
+static void do_pkhtb PARAMS ((char *));
+static void do_qadd16 PARAMS ((char *));
+static void do_rev PARAMS ((char *));
+static void do_rfe PARAMS ((char *));
+static void do_sxtah PARAMS ((char *));
+static void do_sxth PARAMS ((char *));
+static void do_setend PARAMS ((char *));
+static void do_smlad PARAMS ((char *));
+static void do_smlald PARAMS ((char *));
+static void do_smmul PARAMS ((char *));
+static void do_ssat PARAMS ((char *));
+static void do_usat PARAMS ((char *));
+static void do_srs PARAMS ((char *));
+static void do_ssat16 PARAMS ((char *));
+static void do_usat16 PARAMS ((char *));
+static void do_strex PARAMS ((char *));
+static void do_umaal PARAMS ((char *));
+
+static void do_cps_mode PARAMS ((char **));
+static void do_cps_flags PARAMS ((char **, int));
+static int do_endian_specifier PARAMS ((char *));
+static void do_pkh_core PARAMS ((char *, int));
+static void do_sat PARAMS ((char **, int));
+static void do_sat16 PARAMS ((char **, int));
+
/* Coprocessor Instructions. */
static void do_cdp PARAMS ((char *));
static void do_lstc PARAMS ((char *));
static void do_fpa_from_reg PARAMS ((char *));
static void do_fpa_to_reg PARAMS ((char *));
+/* VFP instructions. */
+static void do_vfp_sp_monadic PARAMS ((char *));
+static void do_vfp_dp_monadic PARAMS ((char *));
+static void do_vfp_sp_dyadic PARAMS ((char *));
+static void do_vfp_dp_dyadic PARAMS ((char *));
+static void do_vfp_reg_from_sp PARAMS ((char *));
+static void do_vfp_sp_from_reg PARAMS ((char *));
+static void do_vfp_sp_reg2 PARAMS ((char *));
+static void do_vfp_reg_from_dp PARAMS ((char *));
+static void do_vfp_reg2_from_dp PARAMS ((char *));
+static void do_vfp_dp_from_reg PARAMS ((char *));
+static void do_vfp_dp_from_reg2 PARAMS ((char *));
+static void do_vfp_reg_from_ctrl PARAMS ((char *));
+static void do_vfp_ctrl_from_reg PARAMS ((char *));
+static void do_vfp_sp_ldst PARAMS ((char *));
+static void do_vfp_dp_ldst PARAMS ((char *));
+static void do_vfp_sp_ldstmia PARAMS ((char *));
+static void do_vfp_sp_ldstmdb PARAMS ((char *));
+static void do_vfp_dp_ldstmia PARAMS ((char *));
+static void do_vfp_dp_ldstmdb PARAMS ((char *));
+static void do_vfp_xp_ldstmia PARAMS ((char *));
+static void do_vfp_xp_ldstmdb PARAMS ((char *));
+static void do_vfp_sp_compare_z PARAMS ((char *));
+static void do_vfp_dp_compare_z PARAMS ((char *));
+static void do_vfp_dp_sp_cvt PARAMS ((char *));
+static void do_vfp_sp_dp_cvt PARAMS ((char *));
+
/* XScale. */
-static void do_mia PARAMS ((char *));
-static void do_mar PARAMS ((char *));
-static void do_mra PARAMS ((char *));
+static void do_xsc_mia PARAMS ((char *));
+static void do_xsc_mar PARAMS ((char *));
+static void do_xsc_mra PARAMS ((char *));
/* Maverick. */
-static void do_c_binops PARAMS ((char *, int));
-static void do_c_binops_1 PARAMS ((char *));
-static void do_c_binops_2 PARAMS ((char *));
-static void do_c_binops_3 PARAMS ((char *));
-static void do_c_triple PARAMS ((char *, int));
-static void do_c_triple_4 PARAMS ((char *));
-static void do_c_triple_5 PARAMS ((char *));
-static void do_c_quad PARAMS ((char *, int));
-static void do_c_quad_6 PARAMS ((char *));
-static void do_c_dspsc PARAMS ((char *, int));
-static void do_c_dspsc_1 PARAMS ((char *));
-static void do_c_dspsc_2 PARAMS ((char *));
-static void do_c_shift PARAMS ((char *, int));
-static void do_c_shift_1 PARAMS ((char *));
-static void do_c_shift_2 PARAMS ((char *));
-static void do_c_ldst PARAMS ((char *, int));
-static void do_c_ldst_1 PARAMS ((char *));
-static void do_c_ldst_2 PARAMS ((char *));
-static void do_c_ldst_3 PARAMS ((char *));
-static void do_c_ldst_4 PARAMS ((char *));
-static int cirrus_reg_required_here PARAMS ((char **, int,
- enum cirrus_regtype));
-static int cirrus_valid_reg PARAMS ((int, enum cirrus_regtype));
-static int cirrus_parse_offset PARAMS ((char **, int *));
+static void do_mav_binops PARAMS ((char *, int, enum arm_reg_type,
+ enum arm_reg_type));
+static void do_mav_binops_1a PARAMS ((char *));
+static void do_mav_binops_1b PARAMS ((char *));
+static void do_mav_binops_1c PARAMS ((char *));
+static void do_mav_binops_1d PARAMS ((char *));
+static void do_mav_binops_1e PARAMS ((char *));
+static void do_mav_binops_1f PARAMS ((char *));
+static void do_mav_binops_1g PARAMS ((char *));
+static void do_mav_binops_1h PARAMS ((char *));
+static void do_mav_binops_1i PARAMS ((char *));
+static void do_mav_binops_1j PARAMS ((char *));
+static void do_mav_binops_1k PARAMS ((char *));
+static void do_mav_binops_1l PARAMS ((char *));
+static void do_mav_binops_1m PARAMS ((char *));
+static void do_mav_binops_1n PARAMS ((char *));
+static void do_mav_binops_1o PARAMS ((char *));
+static void do_mav_binops_2a PARAMS ((char *));
+static void do_mav_binops_2b PARAMS ((char *));
+static void do_mav_binops_2c PARAMS ((char *));
+static void do_mav_binops_3a PARAMS ((char *));
+static void do_mav_binops_3b PARAMS ((char *));
+static void do_mav_binops_3c PARAMS ((char *));
+static void do_mav_binops_3d PARAMS ((char *));
+static void do_mav_triple PARAMS ((char *, int, enum arm_reg_type,
+ enum arm_reg_type,
+ enum arm_reg_type));
+static void do_mav_triple_4a PARAMS ((char *));
+static void do_mav_triple_4b PARAMS ((char *));
+static void do_mav_triple_5a PARAMS ((char *));
+static void do_mav_triple_5b PARAMS ((char *));
+static void do_mav_triple_5c PARAMS ((char *));
+static void do_mav_triple_5d PARAMS ((char *));
+static void do_mav_triple_5e PARAMS ((char *));
+static void do_mav_triple_5f PARAMS ((char *));
+static void do_mav_triple_5g PARAMS ((char *));
+static void do_mav_triple_5h PARAMS ((char *));
+static void do_mav_quad PARAMS ((char *, int, enum arm_reg_type,
+ enum arm_reg_type,
+ enum arm_reg_type,
+ enum arm_reg_type));
+static void do_mav_quad_6a PARAMS ((char *));
+static void do_mav_quad_6b PARAMS ((char *));
+static void do_mav_dspsc_1 PARAMS ((char *));
+static void do_mav_dspsc_2 PARAMS ((char *));
+static void do_mav_shift PARAMS ((char *, enum arm_reg_type,
+ enum arm_reg_type));
+static void do_mav_shift_1 PARAMS ((char *));
+static void do_mav_shift_2 PARAMS ((char *));
+static void do_mav_ldst PARAMS ((char *, enum arm_reg_type));
+static void do_mav_ldst_1 PARAMS ((char *));
+static void do_mav_ldst_2 PARAMS ((char *));
+static void do_mav_ldst_3 PARAMS ((char *));
+static void do_mav_ldst_4 PARAMS ((char *));
+
+static int mav_reg_required_here PARAMS ((char **, int,
+ enum arm_reg_type));
+static int mav_parse_offset PARAMS ((char **, int *));
static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *,
int, int));
-static int arm_reg_parse PARAMS ((char **));
+static int arm_reg_parse PARAMS ((char **, struct hash_control *));
+static enum arm_reg_type arm_reg_parse_any PARAMS ((char *));
static const struct asm_psr * arm_psr_parse PARAMS ((char **));
static void symbol_locate PARAMS ((symbolS *, const char *, segT, valueT,
fragS *));
static int cp_opc_expr PARAMS ((char **, int, int));
static int cp_reg_required_here PARAMS ((char **, int));
static int fp_reg_required_here PARAMS ((char **, int));
+static int vfp_sp_reg_required_here PARAMS ((char **, enum vfp_sp_reg_pos));
+static int vfp_dp_reg_required_here PARAMS ((char **, enum vfp_dp_reg_pos));
+static void vfp_sp_ldstm PARAMS ((char *, enum vfp_ldstm_type));
+static void vfp_dp_ldstm PARAMS ((char *, enum vfp_ldstm_type));
+static long vfp_sp_reg_list PARAMS ((char **, enum vfp_sp_reg_pos));
+static long vfp_dp_reg_list PARAMS ((char **));
+static int vfp_psr_required_here PARAMS ((char **str));
+static const struct vfp_reg *vfp_psr_parse PARAMS ((char **str));
static int cp_address_offset PARAMS ((char **));
-static int cp_address_required_here PARAMS ((char **));
+static int cp_address_required_here PARAMS ((char **, int));
static int my_get_float_expression PARAMS ((char **));
static int skip_past_comma PARAMS ((char **));
static int walk_no_bignums PARAMS ((symbolS *));
static int ldst_extend PARAMS ((char **));
static int ldst_extend_v4 PARAMS ((char **));
static void thumb_add_sub PARAMS ((char *, int));
-static void insert_reg PARAMS ((int));
+static void insert_reg PARAMS ((const struct reg_entry *,
+ struct hash_control *));
static void thumb_shift PARAMS ((char *, int));
static void thumb_mov_compare PARAMS ((char *, int));
static void build_arm_ops_hsh PARAMS ((void));
static void set_constant_flonums PARAMS ((void));
static valueT md_chars_to_number PARAMS ((char *, int));
-static void insert_reg_alias PARAMS ((char *, int));
-static void output_inst PARAMS ((void));
+static void build_reg_hsh PARAMS ((struct reg_map *));
+static void insert_reg_alias PARAMS ((char *, int, struct hash_control *));
+static int create_register_alias PARAMS ((char *, char *));
+static void output_inst PARAMS ((const char *));
static int accum0_required_here PARAMS ((char **));
static int ld_mode_required_here PARAMS ((char **));
static void do_branch25 PARAMS ((char *));
static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
#endif
+static int wreg_required_here PARAMS ((char **, int, enum wreg_type));
+static void do_iwmmxt_byte_addr PARAMS ((char *));
+static void do_iwmmxt_tandc PARAMS ((char *));
+static void do_iwmmxt_tbcst PARAMS ((char *));
+static void do_iwmmxt_textrc PARAMS ((char *));
+static void do_iwmmxt_textrm PARAMS ((char *));
+static void do_iwmmxt_tinsr PARAMS ((char *));
+static void do_iwmmxt_tmcr PARAMS ((char *));
+static void do_iwmmxt_tmcrr PARAMS ((char *));
+static void do_iwmmxt_tmia PARAMS ((char *));
+static void do_iwmmxt_tmovmsk PARAMS ((char *));
+static void do_iwmmxt_tmrc PARAMS ((char *));
+static void do_iwmmxt_tmrrc PARAMS ((char *));
+static void do_iwmmxt_torc PARAMS ((char *));
+static void do_iwmmxt_waligni PARAMS ((char *));
+static void do_iwmmxt_wmov PARAMS ((char *));
+static void do_iwmmxt_word_addr PARAMS ((char *));
+static void do_iwmmxt_wrwr PARAMS ((char *));
+static void do_iwmmxt_wrwrwcg PARAMS ((char *));
+static void do_iwmmxt_wrwrwr PARAMS ((char *));
+static void do_iwmmxt_wshufh PARAMS ((char *));
+static void do_iwmmxt_wzero PARAMS ((char *));
+static int cp_byte_address_offset PARAMS ((char **));
+static int cp_byte_address_required_here PARAMS ((char **));
+
/* ARM instructions take 4bytes in the object file, Thumb instructions
take 2: */
#define INSN_SIZE 4
/* "INSN<cond> X,Y" where X:bit12, Y:bit16. */
-#define CIRRUS_MODE1 0x100c
+#define MAV_MODE1 0x100c
/* "INSN<cond> X,Y" where X:bit16, Y:bit12. */
-#define CIRRUS_MODE2 0x0c10
+#define MAV_MODE2 0x0c10
/* "INSN<cond> X,Y" where X:0, Y:bit16. */
-#define CIRRUS_MODE3 0x1000
+#define MAV_MODE3 0x1000
/* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12. */
-#define CIRRUS_MODE4 0x0c0010
+#define MAV_MODE4 0x0c0010
/* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0. */
-#define CIRRUS_MODE5 0x00100c
+#define MAV_MODE5 0x00100c
/* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0. */
-#define CIRRUS_MODE6 0x00100c05
+#define MAV_MODE6 0x00100c05
struct asm_opcode
{
{"mla", 0xe0200090, 3, ARM_EXT_V2, do_mla},
{"mlas", 0xe0300090, 3, ARM_EXT_V2, do_mla},
- /* Generic copressor instructions. */
+ /* Generic coprocessor instructions. */
{"cdp", 0xee000000, 3, ARM_EXT_V2, do_cdp},
{"ldc", 0xec100000, 3, ARM_EXT_V2, do_lstc},
{"ldcl", 0xec500000, 3, ARM_EXT_V2, do_lstc},
{"strh", 0xe00000b0, 3, ARM_EXT_V4, do_ldstv4},
/* ARM Architecture 4T. */
- /* Note: bx (and blx) are required on V5, even if the processor does
+ /* Note: bx (and blx) are required on V5, even if the processor does
not support Thumb. */
{"bx", 0xe12fff10, 2, ARM_EXT_V4T | ARM_EXT_V5, do_bx},
- /* ARM Architecture 5. */
+ /* ARM Architecture 5T. */
/* Note: blx has 2 variants, so the .value is set dynamically.
Only one of the variants has conditional execution. */
{"blx", 0xe0000000, 3, ARM_EXT_V5, do_blx},
{"mcr2", 0xfe000010, 0, ARM_EXT_V5, do_co_reg2},
{"mrc2", 0xfe100010, 0, ARM_EXT_V5, do_co_reg2},
- /* ARM Architecture 5ExP. */
+ /* ARM Architecture 5TExP. */
{"smlabb", 0xe1000080, 6, ARM_EXT_V5ExP, do_smla},
{"smlatb", 0xe10000a0, 6, ARM_EXT_V5ExP, do_smla},
{"smlabt", 0xe10000c0, 6, ARM_EXT_V5ExP, do_smla},
{"qsub", 0xe1200050, 4, ARM_EXT_V5ExP, do_qadd},
{"qdsub", 0xe1600050, 5, ARM_EXT_V5ExP, do_qadd},
- /* ARM Architecture 5E. */
+ /* ARM Architecture 5TE. */
{"pld", 0xf450f000, 0, ARM_EXT_V5E, do_pld},
{"ldrd", 0xe00000d0, 3, ARM_EXT_V5E, do_ldrd},
{"strd", 0xe00000f0, 3, ARM_EXT_V5E, do_ldrd},
{"mcrr", 0xec400000, 4, ARM_EXT_V5E, do_co_reg2c},
{"mrrc", 0xec500000, 4, ARM_EXT_V5E, do_co_reg2c},
+ /* ARM Architecture 5TEJ. */
+ {"bxj", 0xe12fff20, 3, ARM_EXT_V5J, do_bxj},
+
+ /* ARM V6. */
+ { "cps", 0xf1020000, 0, ARM_EXT_V6, do_cps},
+ { "cpsie", 0xf1080000, 0, ARM_EXT_V6, do_cpsi},
+ { "cpsid", 0xf10C0000, 0, ARM_EXT_V6, do_cpsi},
+ { "ldrex", 0xe1900f9f, 5, ARM_EXT_V6, do_ldrex},
+ { "mcrr2", 0xfc400000, 0, ARM_EXT_V6, do_co_reg2c},
+ { "mrrc2", 0xfc500000, 0, ARM_EXT_V6, do_co_reg2c},
+ { "pkhbt", 0xe6800010, 5, ARM_EXT_V6, do_pkhbt},
+ { "pkhtb", 0xe6800050, 5, ARM_EXT_V6, do_pkhtb},
+ { "qadd16", 0xe6200f10, 6, ARM_EXT_V6, do_qadd16},
+ { "qadd8", 0xe6200f90, 5, ARM_EXT_V6, do_qadd16},
+ { "qaddsubx", 0xe6200f30, 8, ARM_EXT_V6, do_qadd16},
+ { "qsub16", 0xe6200f70, 6, ARM_EXT_V6, do_qadd16},
+ { "qsub8", 0xe6200ff0, 5, ARM_EXT_V6, do_qadd16},
+ { "qsubaddx", 0xe6200f50, 8, ARM_EXT_V6, do_qadd16},
+ { "sadd16", 0xe6100f10, 6, ARM_EXT_V6, do_qadd16},
+ { "sadd8", 0xe6100f90, 5, ARM_EXT_V6, do_qadd16},
+ { "saddsubx", 0xe6100f30, 8, ARM_EXT_V6, do_qadd16},
+ { "shadd16", 0xe6300f10, 7, ARM_EXT_V6, do_qadd16},
+ { "shadd8", 0xe6300f90, 6, ARM_EXT_V6, do_qadd16},
+ { "shaddsubx", 0xe6300f30, 9, ARM_EXT_V6, do_qadd16},
+ { "shsub16", 0xe6300f70, 7, ARM_EXT_V6, do_qadd16},
+ { "shsub8", 0xe6300ff0, 6, ARM_EXT_V6, do_qadd16},
+ { "shsubaddx", 0xe6300f50, 9, ARM_EXT_V6, do_qadd16},
+ { "ssub16", 0xe6100f70, 6, ARM_EXT_V6, do_qadd16},
+ { "ssub8", 0xe6100ff0, 5, ARM_EXT_V6, do_qadd16},
+ { "ssubaddx", 0xe6100f50, 8, ARM_EXT_V6, do_qadd16},
+ { "uadd16", 0xe6500f10, 6, ARM_EXT_V6, do_qadd16},
+ { "uadd8", 0xe6500f90, 5, ARM_EXT_V6, do_qadd16},
+ { "uaddsubx", 0xe6500f30, 8, ARM_EXT_V6, do_qadd16},
+ { "uhadd16", 0xe6700f10, 7, ARM_EXT_V6, do_qadd16},
+ { "uhadd8", 0xe6700f90, 6, ARM_EXT_V6, do_qadd16},
+ { "uhaddsubx", 0xe6700f30, 9, ARM_EXT_V6, do_qadd16},
+ { "uhsub16", 0xe6700f70, 7, ARM_EXT_V6, do_qadd16},
+ { "uhsub8", 0xe6700ff0, 6, ARM_EXT_V6, do_qadd16},
+ { "uhsubaddx", 0xe6700f50, 9, ARM_EXT_V6, do_qadd16},
+ { "uqadd16", 0xe6600f10, 7, ARM_EXT_V6, do_qadd16},
+ { "uqadd8", 0xe6600f90, 6, ARM_EXT_V6, do_qadd16},
+ { "uqaddsubx", 0xe6600f30, 9, ARM_EXT_V6, do_qadd16},
+ { "uqsub16", 0xe6600f70, 7, ARM_EXT_V6, do_qadd16},
+ { "uqsub8", 0xe6600ff0, 6, ARM_EXT_V6, do_qadd16},
+ { "uqsubaddx", 0xe6600f50, 9, ARM_EXT_V6, do_qadd16},
+ { "usub16", 0xe6500f70, 6, ARM_EXT_V6, do_qadd16},
+ { "usub8", 0xe6500ff0, 5, ARM_EXT_V6, do_qadd16},
+ { "usubaddx", 0xe6500f50, 8, ARM_EXT_V6, do_qadd16},
+ { "rev", 0xe6bf0f30, 3, ARM_EXT_V6, do_rev},
+ { "rev16", 0xe6bf0fb0, 5, ARM_EXT_V6, do_rev},
+ { "revsh", 0xe6ff0fb0, 5, ARM_EXT_V6, do_rev},
+ { "rfeia", 0xf8900a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfeib", 0xf9900a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfeda", 0xf8100a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfedb", 0xf9100a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfefd", 0xf8900a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfefa", 0xf9900a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfeea", 0xf8100a00, 0, ARM_EXT_V6, do_rfe},
+ { "rfeed", 0xf9100a00, 0, ARM_EXT_V6, do_rfe},
+ { "sxtah", 0xe6b00070, 5, ARM_EXT_V6, do_sxtah},
+ { "sxtab16", 0xe6800070, 7, ARM_EXT_V6, do_sxtah},
+ { "sxtab", 0xe6a00070, 5, ARM_EXT_V6, do_sxtah},
+ { "sxth", 0xe6bf0070, 4, ARM_EXT_V6, do_sxth},
+ { "sxtb16", 0xe68f0070, 6, ARM_EXT_V6, do_sxth},
+ { "sxtb", 0xe6af0070, 4, ARM_EXT_V6, do_sxth},
+ { "uxtah", 0xe6f00070, 5, ARM_EXT_V6, do_sxtah},
+ { "uxtab16", 0xe6c00070, 7, ARM_EXT_V6, do_sxtah},
+ { "uxtab", 0xe6e00070, 5, ARM_EXT_V6, do_sxtah},
+ { "uxth", 0xe6ff0070, 4, ARM_EXT_V6, do_sxth},
+ { "uxtb16", 0xe6cf0070, 6, ARM_EXT_V6, do_sxth},
+ { "uxtb", 0xe6ef0070, 4, ARM_EXT_V6, do_sxth},
+ { "sel", 0xe68000b0, 3, ARM_EXT_V6, do_qadd16},
+ { "setend", 0xf1010000, 0, ARM_EXT_V6, do_setend},
+ { "smlad", 0xe7000010, 5, ARM_EXT_V6, do_smlad},
+ { "smladx", 0xe7000030, 6, ARM_EXT_V6, do_smlad},
+ { "smlald", 0xe7400010, 6, ARM_EXT_V6, do_smlald},
+ { "smlaldx", 0xe7400030, 7, ARM_EXT_V6, do_smlald},
+ { "smlsd", 0xe7000050, 5, ARM_EXT_V6, do_smlad},
+ { "smlsdx", 0xe7000070, 6, ARM_EXT_V6, do_smlad},
+ { "smlsld", 0xe7400050, 6, ARM_EXT_V6, do_smlald},
+ { "smlsldx", 0xe7400070, 7, ARM_EXT_V6, do_smlald},
+ { "smmla", 0xe7500010, 5, ARM_EXT_V6, do_smlad},
+ { "smmlar", 0xe7500030, 6, ARM_EXT_V6, do_smlad},
+ { "smmls", 0xe75000d0, 5, ARM_EXT_V6, do_smlad},
+ { "smmlsr", 0xe75000f0, 6, ARM_EXT_V6, do_smlad},
+ { "smmul", 0xe750f010, 5, ARM_EXT_V6, do_smmul},
+ { "smmulr", 0xe750f030, 6, ARM_EXT_V6, do_smmul},
+ { "smuad", 0xe700f010, 5, ARM_EXT_V6, do_smmul},
+ { "smuadx", 0xe700f030, 6, ARM_EXT_V6, do_smmul},
+ { "smusd", 0xe700f050, 5, ARM_EXT_V6, do_smmul},
+ { "smusdx", 0xe700f070, 6, ARM_EXT_V6, do_smmul},
+ { "srsia", 0xf8cd0500, 0, ARM_EXT_V6, do_srs},
+ { "srsib", 0xf9cd0500, 0, ARM_EXT_V6, do_srs},
+ { "srsda", 0xf84d0500, 0, ARM_EXT_V6, do_srs},
+ { "srsdb", 0xf94d0500, 0, ARM_EXT_V6, do_srs},
+ { "ssat", 0xe6a00010, 4, ARM_EXT_V6, do_ssat},
+ { "ssat16", 0xe6a00f30, 6, ARM_EXT_V6, do_ssat16},
+ { "strex", 0xe1800f90, 5, ARM_EXT_V6, do_strex},
+ { "umaal", 0xe0400090, 5, ARM_EXT_V6, do_umaal},
+ { "usad8", 0xe780f010, 5, ARM_EXT_V6, do_smmul},
+ { "usada8", 0xe7800010, 6, ARM_EXT_V6, do_smlad},
+ { "usat", 0xe6e00010, 4, ARM_EXT_V6, do_usat},
+ { "usat16", 0xe6e00f30, 6, ARM_EXT_V6, do_usat16},
+
/* Core FPA instruction set (V1). */
{"wfs", 0xee200110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
{"rfs", 0xee300110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
{"sfmfd", 0xed000200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
{"sfmea", 0xec800200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
+ /* VFP V1xD (single precision). */
+ /* Moves and type conversions. */
+ {"fcpys", 0xeeb00a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fmrs", 0xee100a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_sp},
+ {"fmsr", 0xee000a10, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_from_reg},
+ {"fmstat", 0xeef1fa10, 6, FPU_VFP_EXT_V1xD, do_empty},
+ {"fsitos", 0xeeb80ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fuitos", 0xeeb80a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"ftosis", 0xeebd0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"ftosizs", 0xeebd0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"ftouis", 0xeebc0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"ftouizs", 0xeebc0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fmrx", 0xeef00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_ctrl},
+ {"fmxr", 0xeee00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_ctrl_from_reg},
+
+ /* Memory operations. */
+ {"flds", 0xed100a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
+ {"fsts", 0xed000a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
+ {"fldmias", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
+ {"fldmfds", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
+ {"fldmdbs", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
+ {"fldmeas", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
+ {"fldmiax", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
+ {"fldmfdx", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
+ {"fldmdbx", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+ {"fldmeax", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+ {"fstmias", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
+ {"fstmeas", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
+ {"fstmdbs", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
+ {"fstmfds", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
+ {"fstmiax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
+ {"fstmeax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
+ {"fstmdbx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+ {"fstmfdx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+
+ /* Monadic operations. */
+ {"fabss", 0xeeb00ac0, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fnegs", 0xeeb10a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fsqrts", 0xeeb10ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+
+ /* Dyadic operations. */
+ {"fadds", 0xee300a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fsubs", 0xee300a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fmuls", 0xee200a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fdivs", 0xee800a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fmacs", 0xee000a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fmscs", 0xee100a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fnmuls", 0xee200a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fnmacs", 0xee000a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ {"fnmscs", 0xee100a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+
+ /* Comparisons. */
+ {"fcmps", 0xeeb40a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fcmpzs", 0xeeb50a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
+ {"fcmpes", 0xeeb40ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ {"fcmpezs", 0xeeb50ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
+
+ /* VFP V1 (Double precision). */
+ /* Moves and type conversions. */
+ {"fcpyd", 0xeeb00b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ {"fcvtds", 0xeeb70ac0, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
+ {"fcvtsd", 0xeeb70bc0, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+ {"fmdhr", 0xee200b10, 5, FPU_VFP_EXT_V1, do_vfp_dp_from_reg},
+ {"fmdlr", 0xee000b10, 5, FPU_VFP_EXT_V1, do_vfp_dp_from_reg},
+ {"fmrdh", 0xee300b10, 5, FPU_VFP_EXT_V1, do_vfp_reg_from_dp},
+ {"fmrdl", 0xee100b10, 5, FPU_VFP_EXT_V1, do_vfp_reg_from_dp},
+ {"fsitod", 0xeeb80bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
+ {"fuitod", 0xeeb80b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
+ {"ftosid", 0xeebd0b40, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+ {"ftosizd", 0xeebd0bc0, 7, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+ {"ftouid", 0xeebc0b40, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+ {"ftouizd", 0xeebc0bc0, 7, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+
+ /* Memory operations. */
+ {"fldd", 0xed100b00, 4, FPU_VFP_EXT_V1, do_vfp_dp_ldst},
+ {"fstd", 0xed000b00, 4, FPU_VFP_EXT_V1, do_vfp_dp_ldst},
+ {"fldmiad", 0xec900b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
+ {"fldmfdd", 0xec900b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
+ {"fldmdbd", 0xed300b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
+ {"fldmead", 0xed300b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
+ {"fstmiad", 0xec800b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
+ {"fstmead", 0xec800b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
+ {"fstmdbd", 0xed200b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
+ {"fstmfdd", 0xed200b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
+
+ /* Monadic operations. */
+ {"fabsd", 0xeeb00bc0, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ {"fnegd", 0xeeb10b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ {"fsqrtd", 0xeeb10bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+
+ /* Dyadic operations. */
+ {"faddd", 0xee300b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fsubd", 0xee300b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fmuld", 0xee200b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fdivd", 0xee800b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fmacd", 0xee000b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fmscd", 0xee100b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fnmuld", 0xee200b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fnmacd", 0xee000b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ {"fnmscd", 0xee100b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+
+ /* Comparisons. */
+ {"fcmpd", 0xeeb40b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ {"fcmpzd", 0xeeb50b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
+ {"fcmped", 0xeeb40bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ {"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
+
+ /* VFP V2. */
+ {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
+ {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
+ {"fmdrr", 0xec400b10, 5, FPU_VFP_EXT_V2, do_vfp_dp_from_reg2},
+ {"fmrrd", 0xec500b10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_dp},
+
/* Intel XScale extensions to ARM V5 ISA. (All use CP0). */
- {"mia", 0xee200010, 3, ARM_EXT_XSCALE, do_mia},
- {"miaph", 0xee280010, 5, ARM_EXT_XSCALE, do_mia},
- {"miabb", 0xee2c0010, 5, ARM_EXT_XSCALE, do_mia},
- {"miabt", 0xee2d0010, 5, ARM_EXT_XSCALE, do_mia},
- {"miatb", 0xee2e0010, 5, ARM_EXT_XSCALE, do_mia},
- {"miatt", 0xee2f0010, 5, ARM_EXT_XSCALE, do_mia},
- {"mar", 0xec400000, 3, ARM_EXT_XSCALE, do_mar},
- {"mra", 0xec500000, 3, ARM_EXT_XSCALE, do_mra},
-
- /* Cirrus DSP instructions. */
- {"cfldrs", 0xec100400, 6, ARM_EXT_MAVERICK, do_c_ldst_1},
- {"cfldrd", 0xec500400, 6, ARM_EXT_MAVERICK, do_c_ldst_2},
- {"cfldr32", 0xec100500, 7, ARM_EXT_MAVERICK, do_c_ldst_3},
- {"cfldr64", 0xec500500, 7, ARM_EXT_MAVERICK, do_c_ldst_4},
- {"cfstrs", 0xec000400, 6, ARM_EXT_MAVERICK, do_c_ldst_1},
- {"cfstrd", 0xec400400, 6, ARM_EXT_MAVERICK, do_c_ldst_2},
- {"cfstr32", 0xec000500, 7, ARM_EXT_MAVERICK, do_c_ldst_3},
- {"cfstr64", 0xec400500, 7, ARM_EXT_MAVERICK, do_c_ldst_4},
- {"cfmvsr", 0xee000450, 6, ARM_EXT_MAVERICK, do_c_binops_2},
- {"cfmvrs", 0xee100450, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfmvdlr", 0xee000410, 7, ARM_EXT_MAVERICK, do_c_binops_2},
- {"cfmvrdl", 0xee100410, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfmvdhr", 0xee000430, 7, ARM_EXT_MAVERICK, do_c_binops_2},
- {"cfmvrdh", 0xee100430, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfmv64lr", 0xee000510, 8, ARM_EXT_MAVERICK, do_c_binops_2},
- {"cfmvr64l", 0xee100510, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfmv64hr", 0xee000530, 8, ARM_EXT_MAVERICK, do_c_binops_2},
- {"cfmvr64h", 0xee100530, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfmval32", 0xee100610, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmv32al", 0xee000610, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmvam32", 0xee100630, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmv32am", 0xee000630, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmvah32", 0xee100650, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmv32ah", 0xee000650, 8, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmv32a", 0xee000670, 7, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmva32", 0xee100670, 7, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmv64a", 0xee000690, 7, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmva64", 0xee100690, 7, ARM_EXT_MAVERICK, do_c_binops_3},
- {"cfmvsc32", 0xee1006b0, 8, ARM_EXT_MAVERICK, do_c_dspsc_1},
- {"cfmv32sc", 0xee0006b0, 8, ARM_EXT_MAVERICK, do_c_dspsc_2},
- {"cfcpys", 0xee000400, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcpyd", 0xee000420, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvtsd", 0xee000460, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvtds", 0xee000440, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvt32s", 0xee000480, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvt32d", 0xee0004a0, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvt64s", 0xee0004c0, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvt64d", 0xee0004e0, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvts32", 0xee100580, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfcvtd32", 0xee1005a0, 8, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cftruncs32", 0xee1005c0, 10, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cftruncd32", 0xee1005e0, 10, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfrshl32", 0xee000550, 8, ARM_EXT_MAVERICK, do_c_triple_4},
- {"cfrshl64", 0xee000570, 8, ARM_EXT_MAVERICK, do_c_triple_4},
- {"cfsh32", 0xee000500, 6, ARM_EXT_MAVERICK, do_c_shift_1},
- {"cfsh64", 0xee200500, 6, ARM_EXT_MAVERICK, do_c_shift_2},
- {"cfcmps", 0xee100490, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfcmpd", 0xee1004b0, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfcmp32", 0xee100590, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfcmp64", 0xee1005b0, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfabss", 0xee300400, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfabsd", 0xee300420, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfnegs", 0xee300440, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfnegd", 0xee300460, 6, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfadds", 0xee300480, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfaddd", 0xee3004a0, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfsubs", 0xee3004c0, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfsubd", 0xee3004e0, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmuls", 0xee100400, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmuld", 0xee100420, 6, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfabs32", 0xee300500, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfabs64", 0xee300520, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfneg32", 0xee300540, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfneg64", 0xee300560, 7, ARM_EXT_MAVERICK, do_c_binops_1},
- {"cfadd32", 0xee300580, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfadd64", 0xee3005a0, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfsub32", 0xee3005c0, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfsub64", 0xee3005e0, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmul32", 0xee100500, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmul64", 0xee100520, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmac32", 0xee100540, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmsc32", 0xee100560, 7, ARM_EXT_MAVERICK, do_c_triple_5},
- {"cfmadd32", 0xee000600, 8, ARM_EXT_MAVERICK, do_c_quad_6},
- {"cfmsub32", 0xee100600, 8, ARM_EXT_MAVERICK, do_c_quad_6},
- {"cfmadda32", 0xee200600, 9, ARM_EXT_MAVERICK, do_c_quad_6},
- {"cfmsuba32", 0xee300600, 9, ARM_EXT_MAVERICK, do_c_quad_6},
+ {"mia", 0xee200010, 3, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"miaph", 0xee280010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"miabb", 0xee2c0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"miabt", 0xee2d0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"miatb", 0xee2e0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"miatt", 0xee2f0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
+ {"mar", 0xec400000, 3, ARM_CEXT_XSCALE, do_xsc_mar},
+ {"mra", 0xec500000, 3, ARM_CEXT_XSCALE, do_xsc_mra},
+
+ /* Intel Wireless MMX technology instructions. */
+ {"tandcb", 0xee130130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+ {"tandch", 0xee530130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+ {"tandcw", 0xee930130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
+ {"tbcstb", 0xee400010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+ {"tbcsth", 0xee400050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+ {"tbcstw", 0xee400090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
+ {"textrcb", 0xee130170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+ {"textrch", 0xee530170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+ {"textrcw", 0xee930170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
+ {"textrmub", 0xee100070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"textrmuh", 0xee500070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"textrmuw", 0xee900070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"textrmsb", 0xee100078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"textrmsh", 0xee500078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"textrmsw", 0xee900078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
+ {"tinsrb", 0xee600010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+ {"tinsrh", 0xee600050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+ {"tinsrw", 0xee600090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
+ {"tmcr", 0xee000110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmcr},
+ {"tmcrr", 0xec400000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmcrr},
+ {"tmia", 0xee200010, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmiaph", 0xee280010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmiabb", 0xee2c0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmiabt", 0xee2d0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmiatb", 0xee2e0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmiatt", 0xee2f0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
+ {"tmovmskb", 0xee100030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+ {"tmovmskh", 0xee500030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+ {"tmovmskw", 0xee900030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
+ {"tmrc", 0xee100110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmrc},
+ {"tmrrc", 0xec500000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmrrc},
+ {"torcb", 0xee130150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+ {"torch", 0xee530150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+ {"torcw", 0xee930150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
+ {"waccb", 0xee0001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wacch", 0xee4001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"waccw", 0xee8001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"waddbss", 0xee300180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddb", 0xee000180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddbus", 0xee100180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddhss", 0xee700180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddh", 0xee400180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddhus", 0xee500180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddwss", 0xeeb00180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddw", 0xee800180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waddwus", 0xee900180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"waligni", 0xee000020, 7, ARM_CEXT_IWMMXT, do_iwmmxt_waligni},
+ {"walignr0", 0xee800020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"walignr1", 0xee900020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"walignr2", 0xeea00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"walignr3", 0xeeb00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wand", 0xee200000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wandn", 0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wavg2b", 0xee800000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wavg2br", 0xee900000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wavg2h", 0xeec00000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wavg2hr", 0xeed00000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpeqb", 0xee000060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpeqh", 0xee400060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpeqw", 0xee800060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtub", 0xee100060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtuh", 0xee500060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtuw", 0xee900060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtsb", 0xee300060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtsh", 0xee700060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wcmpgtsw", 0xeeb00060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wldrb", 0xec100000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+ {"wldrh", 0xec100100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+ {"wldrw", 0xec100200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+ {"wldrd", 0xec100300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+ {"wmacs", 0xee600100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmacsz", 0xee700100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmacu", 0xee400100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmacuz", 0xee500100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmadds", 0xeea00100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaddu", 0xee800100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxsb", 0xee200160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxsh", 0xee600160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxsw", 0xeea00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxub", 0xee000160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxuh", 0xee400160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmaxuw", 0xee800160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminsb", 0xee300160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminsh", 0xee700160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminsw", 0xeeb00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminub", 0xee100160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminuh", 0xee500160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wminuw", 0xee900160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmov", 0xee000000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wmov},
+ {"wmulsm", 0xee300100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmulsl", 0xee200100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmulum", 0xee100100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wmulul", 0xee000100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wor", 0xee000000, 3, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackhss", 0xee700080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackhus", 0xee500080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackwss", 0xeeb00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackwus", 0xee900080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackdss", 0xeef00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wpackdus", 0xeed00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wrorh", 0xee700040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wrorhg", 0xee700148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wrorw", 0xeeb00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wrorwg", 0xeeb00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wrord", 0xeef00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wrordg", 0xeef00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsadb", 0xee000120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsadbz", 0xee100120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsadh", 0xee400120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsadhz", 0xee500120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wshufh", 0xee0001e0, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wshufh},
+ {"wsllh", 0xee500040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsllhg", 0xee500148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsllw", 0xee900040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsllwg", 0xee900148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wslld", 0xeed00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wslldg", 0xeed00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsrah", 0xee400040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsrahg", 0xee400148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsraw", 0xee800040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsrawg", 0xee800148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsrad", 0xeec00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsradg", 0xeec00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsrlh", 0xee600040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsrlhg", 0xee600148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsrlw", 0xeea00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsrlwg", 0xeea00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wsrld", 0xeee00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsrldg", 0xeee00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
+ {"wstrb", 0xec000000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+ {"wstrh", 0xec000100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
+ {"wstrw", 0xec000200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+ {"wstrd", 0xec000300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
+ {"wsubbss", 0xee3001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubb", 0xee0001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubbus", 0xee1001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubhss", 0xee7001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubh", 0xee4001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubhus", 0xee5001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubwss", 0xeeb001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubw", 0xee8001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wsubwus", 0xee9001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckehub", 0xee0000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckehuh", 0xee4000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckehuw", 0xee8000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckehsb", 0xee2000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckehsh", 0xee6000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckehsw", 0xeea000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckihb", 0xee1000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckihh", 0xee5000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckihw", 0xee9000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckelub", 0xee0000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckeluh", 0xee4000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckeluw", 0xee8000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckelsb", 0xee2000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckelsh", 0xee6000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckelsw", 0xeea000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
+ {"wunpckilb", 0xee1000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckilh", 0xee5000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wunpckilw", 0xee9000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wxor", 0xee100000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
+ {"wzero", 0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wzero},
+
+ /* Cirrus Maverick instructions. */
+ {"cfldrs", 0xec100400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_1},
+ {"cfldrd", 0xec500400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_2},
+ {"cfldr32", 0xec100500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_3},
+ {"cfldr64", 0xec500500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_4},
+ {"cfstrs", 0xec000400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_1},
+ {"cfstrd", 0xec400400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_2},
+ {"cfstr32", 0xec000500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_3},
+ {"cfstr64", 0xec400500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_4},
+ {"cfmvsr", 0xee000450, 6, ARM_CEXT_MAVERICK, do_mav_binops_2a},
+ {"cfmvrs", 0xee100450, 6, ARM_CEXT_MAVERICK, do_mav_binops_1a},
+ {"cfmvdlr", 0xee000410, 7, ARM_CEXT_MAVERICK, do_mav_binops_2b},
+ {"cfmvrdl", 0xee100410, 7, ARM_CEXT_MAVERICK, do_mav_binops_1b},
+ {"cfmvdhr", 0xee000430, 7, ARM_CEXT_MAVERICK, do_mav_binops_2b},
+ {"cfmvrdh", 0xee100430, 7, ARM_CEXT_MAVERICK, do_mav_binops_1b},
+ {"cfmv64lr", 0xee000510, 8, ARM_CEXT_MAVERICK, do_mav_binops_2c},
+ {"cfmvr64l", 0xee100510, 8, ARM_CEXT_MAVERICK, do_mav_binops_1c},
+ {"cfmv64hr", 0xee000530, 8, ARM_CEXT_MAVERICK, do_mav_binops_2c},
+ {"cfmvr64h", 0xee100530, 8, ARM_CEXT_MAVERICK, do_mav_binops_1c},
+ {"cfmval32", 0xee100610, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
+ {"cfmv32al", 0xee000610, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
+ {"cfmvam32", 0xee100630, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
+ {"cfmv32am", 0xee000630, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
+ {"cfmvah32", 0xee100650, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
+ {"cfmv32ah", 0xee000650, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
+ {"cfmva32", 0xee100670, 7, ARM_CEXT_MAVERICK, do_mav_binops_3a},
+ {"cfmv32a", 0xee000670, 7, ARM_CEXT_MAVERICK, do_mav_binops_3b},
+ {"cfmva64", 0xee100690, 7, ARM_CEXT_MAVERICK, do_mav_binops_3c},
+ {"cfmv64a", 0xee000690, 7, ARM_CEXT_MAVERICK, do_mav_binops_3d},
+ {"cfmvsc32", 0xee1006b0, 8, ARM_CEXT_MAVERICK, do_mav_dspsc_1},
+ {"cfmv32sc", 0xee0006b0, 8, ARM_CEXT_MAVERICK, do_mav_dspsc_2},
+ {"cfcpys", 0xee000400, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
+ {"cfcpyd", 0xee000420, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
+ {"cfcvtsd", 0xee000460, 7, ARM_CEXT_MAVERICK, do_mav_binops_1f},
+ {"cfcvtds", 0xee000440, 7, ARM_CEXT_MAVERICK, do_mav_binops_1g},
+ {"cfcvt32s", 0xee000480, 8, ARM_CEXT_MAVERICK, do_mav_binops_1h},
+ {"cfcvt32d", 0xee0004a0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1i},
+ {"cfcvt64s", 0xee0004c0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1j},
+ {"cfcvt64d", 0xee0004e0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1k},
+ {"cfcvts32", 0xee100580, 8, ARM_CEXT_MAVERICK, do_mav_binops_1l},
+ {"cfcvtd32", 0xee1005a0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1m},
+ {"cftruncs32", 0xee1005c0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1l},
+ {"cftruncd32", 0xee1005e0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1m},
+ {"cfrshl32", 0xee000550, 8, ARM_CEXT_MAVERICK, do_mav_triple_4a},
+ {"cfrshl64", 0xee000570, 8, ARM_CEXT_MAVERICK, do_mav_triple_4b},
+ {"cfsh32", 0xee000500, 6, ARM_CEXT_MAVERICK, do_mav_shift_1},
+ {"cfsh64", 0xee200500, 6, ARM_CEXT_MAVERICK, do_mav_shift_2},
+ {"cfcmps", 0xee100490, 6, ARM_CEXT_MAVERICK, do_mav_triple_5a},
+ {"cfcmpd", 0xee1004b0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5b},
+ {"cfcmp32", 0xee100590, 7, ARM_CEXT_MAVERICK, do_mav_triple_5c},
+ {"cfcmp64", 0xee1005b0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5d},
+ {"cfabss", 0xee300400, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
+ {"cfabsd", 0xee300420, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
+ {"cfnegs", 0xee300440, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
+ {"cfnegd", 0xee300460, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
+ {"cfadds", 0xee300480, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
+ {"cfaddd", 0xee3004a0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
+ {"cfsubs", 0xee3004c0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
+ {"cfsubd", 0xee3004e0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
+ {"cfmuls", 0xee100400, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
+ {"cfmuld", 0xee100420, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
+ {"cfabs32", 0xee300500, 7, ARM_CEXT_MAVERICK, do_mav_binops_1n},
+ {"cfabs64", 0xee300520, 7, ARM_CEXT_MAVERICK, do_mav_binops_1o},
+ {"cfneg32", 0xee300540, 7, ARM_CEXT_MAVERICK, do_mav_binops_1n},
+ {"cfneg64", 0xee300560, 7, ARM_CEXT_MAVERICK, do_mav_binops_1o},
+ {"cfadd32", 0xee300580, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
+ {"cfadd64", 0xee3005a0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
+ {"cfsub32", 0xee3005c0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
+ {"cfsub64", 0xee3005e0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
+ {"cfmul32", 0xee100500, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
+ {"cfmul64", 0xee100520, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
+ {"cfmac32", 0xee100540, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
+ {"cfmsc32", 0xee100560, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
+ {"cfmadd32", 0xee000600, 8, ARM_CEXT_MAVERICK, do_mav_quad_6a},
+ {"cfmsub32", 0xee100600, 8, ARM_CEXT_MAVERICK, do_mav_quad_6a},
+ {"cfmadda32", 0xee200600, 9, ARM_CEXT_MAVERICK, do_mav_quad_6b},
+ {"cfmsuba32", 0xee300600, 9, ARM_CEXT_MAVERICK, do_mav_quad_6b},
};
/* Defines for various bits that we will want to toggle. */
static void do_t_blx PARAMS ((char *));
static void do_t_bkpt PARAMS ((char *));
+/* ARM V6. */
+static void do_t_cps PARAMS ((char *));
+static void do_t_cpy PARAMS ((char *));
+static void do_t_setend PARAMS ((char *));;
+
#define T_OPCODE_MUL 0x4340
#define T_OPCODE_TST 0x4200
#define T_OPCODE_CMN 0x42c0
#define THUMB_MOVE 0
#define THUMB_COMPARE 1
+#define THUMB_CPY 2
#define THUMB_LOAD 0
#define THUMB_STORE 1
/* Thumb v2 (ARMv5T). */
{"blx", 0, 0, ARM_EXT_V5T, do_t_blx},
{"bkpt", 0xbe00, 2, ARM_EXT_V5T, do_t_bkpt},
-};
-
-struct reg_entry
-{
- const char * name;
- int number;
-};
-
-#define int_register(reg) ((reg) >= 0 && (reg) <= 15)
-#define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
-#define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
-
-#define ARM_EXT_MAVERICKSC_REG 134
-
-#define cirrus_register(reg) ((reg) >= 50 && (reg) <= 134)
-#define cirrus_mvf_register(reg) ((reg) >= 50 && (reg) <= 65)
-#define cirrus_mvd_register(reg) ((reg) >= 70 && (reg) <= 85)
-#define cirrus_mvfx_register(reg) ((reg) >= 90 && (reg) <= 105)
-#define cirrus_mvdx_register(reg) ((reg) >= 110 && (reg) <= 125)
-#define cirrus_mvax_register(reg) ((reg) >= 130 && (reg) <= 133)
-#define ARM_EXT_MAVERICKsc_register(reg) ((reg) == ARM_EXT_MAVERICKSC_REG)
-
-#define REG_SP 13
-#define REG_LR 14
-#define REG_PC 15
-/* These are the standard names. Users can add aliases with .req. */
-static const struct reg_entry reg_table[] =
-{
- /* Processor Register Numbers. */
- {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
- {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
- {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
- {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
- /* APCS conventions. */
- {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
- {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
- {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
- {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
- /* ATPCS additions to APCS conventions. */
- {"wr", 7}, {"v8", 11},
- /* FP Registers. */
- {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
- {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
- {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
- {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
- {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
- {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
- {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
- {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
- {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
- {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
- /* ATPCS additions to float register names. */
- {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
- {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
- {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
- {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
- /* Cirrus DSP coprocessor registers. */
- {"mvf0", 50}, {"mvf1", 51}, {"mvf2", 52}, {"mvf3", 53},
- {"mvf4", 54}, {"mvf5", 55}, {"mvf6", 56}, {"mvf7", 57},
- {"mvf8", 58}, {"mvf9", 59}, {"mvf10", 60}, {"mvf11", 61},
- {"mvf12", 62},{"mvf13", 63}, {"mvf14", 64}, {"mvf15", 65},
- {"mvd0", 70}, {"mvd1", 71}, {"mvd2", 72}, {"mvd3", 73},
- {"mvd4", 74}, {"mvd5", 75}, {"mvd6", 76}, {"mvd7", 77},
- {"mvd8", 78}, {"mvd9", 79}, {"mvd10", 80}, {"mvd11", 81},
- {"mvd12", 82},{"mvd13", 83}, {"mvd14", 84}, {"mvd15", 85},
- {"mvfx0", 90},{"mvfx1", 91}, {"mvfx2", 92}, {"mvfx3", 93},
- {"mvfx4", 94},{"mvfx5", 95}, {"mvfx6", 96}, {"mvfx7", 97},
- {"mvfx8", 98},{"mvfx9", 99}, {"mvfx10", 100},{"mvfx11", 101},
- {"mvfx12", 102},{"mvfx13", 103},{"mvfx14", 104},{"mvfx15", 105},
- {"mvdx0", 110}, {"mvdx1", 111}, {"mvdx2", 112}, {"mvdx3", 113},
- {"mvdx4", 114}, {"mvdx5", 115}, {"mvdx6", 116}, {"mvdx7", 117},
- {"mvdx8", 118}, {"mvdx9", 119}, {"mvdx10", 120},{"mvdx11", 121},
- {"mvdx12", 122},{"mvdx13", 123},{"mvdx14", 124},{"mvdx15", 125},
- {"mvax0", 130}, {"mvax1", 131}, {"mvax2", 132}, {"mvax3", 133},
- {"dspsc", ARM_EXT_MAVERICKSC_REG},
- /* FIXME: At some point we need to add VFP register names. */
- /* Array terminator. */
- {NULL, 0}
+ /* ARM V6. */
+ {"cpsie", 0xb660, 2, ARM_EXT_V6, do_t_cps},
+ {"cpsid", 0xb670, 2, ARM_EXT_V6, do_t_cps},
+ {"cpy", 0x4600, 2, ARM_EXT_V6, do_t_cpy},
+ {"rev", 0xba00, 2, ARM_EXT_V6, do_t_arit},
+ {"rev16", 0xba40, 2, ARM_EXT_V6, do_t_arit},
+ {"revsh", 0xbac0, 2, ARM_EXT_V6, do_t_arit},
+ {"setend", 0xb650, 2, ARM_EXT_V6, do_t_setend},
+ {"sxth", 0xb200, 2, ARM_EXT_V6, do_t_arit},
+ {"sxtb", 0xb240, 2, ARM_EXT_V6, do_t_arit},
+ {"uxth", 0xb280, 2, ARM_EXT_V6, do_t_arit},
+ {"uxtb", 0xb2c0, 2, ARM_EXT_V6, do_t_arit},
};
-#define BAD_ARGS _("Bad arguments to instruction")
+#define BAD_ARGS _("bad arguments to instruction")
#define BAD_PC _("r15 not allowed here")
-#define BAD_COND _("Instruction is not conditional")
+#define BAD_COND _("instruction is not conditional")
#define ERR_NO_ACCUM _("acc0 expected")
static struct hash_control * arm_ops_hsh = NULL;
static struct hash_control * arm_tops_hsh = NULL;
static struct hash_control * arm_cond_hsh = NULL;
static struct hash_control * arm_shift_hsh = NULL;
-static struct hash_control * arm_reg_hsh = NULL;
static struct hash_control * arm_psr_hsh = NULL;
/* This table describes all the machine specific pseudo-ops the assembler
Integer arg to pass to the function. */
static void s_req PARAMS ((int));
+static void s_unreq PARAMS ((int));
static void s_align PARAMS ((int));
static void s_bss PARAMS ((int));
static void s_even PARAMS ((int));
static void s_force_thumb PARAMS ((int));
static void s_thumb_func PARAMS ((int));
static void s_thumb_set PARAMS ((int));
-static void arm_s_text PARAMS ((int));
-static void arm_s_data PARAMS ((int));
#ifdef OBJ_ELF
-static void arm_s_section PARAMS ((int));
static void s_arm_elf_cons PARAMS ((int));
#endif
const pseudo_typeS md_pseudo_table[] =
{
- /* Never called becasue '.req' does not start line. */
+ /* Never called because '.req' does not start a line. */
{ "req", s_req, 0 },
+ { "unreq", s_unreq, 0 },
{ "bss", s_bss, 0 },
{ "align", s_align, 0 },
{ "arm", s_arm, 0 },
{ "even", s_even, 0 },
{ "ltorg", s_ltorg, 0 },
{ "pool", s_ltorg, 0 },
- /* Allow for the effect of section changes. */
- { "text", arm_s_text, 0 },
- { "data", arm_s_data, 0 },
#ifdef OBJ_ELF
- { "section", arm_s_section, 0 },
- { "section.s", arm_s_section, 0 },
- { "sect", arm_s_section, 0 },
- { "sect.s", arm_s_section, 0 },
{ "word", s_arm_elf_cons, 4 },
{ "long", s_arm_elf_cons, 4 },
- { "file", dwarf2_directive_file, 0 },
- { "loc", dwarf2_directive_loc, 0 },
#else
{ "word", cons, 4},
#endif
{ 0, 0, 0 }
};
+/* Other internal functions. */
+static int arm_parse_extension PARAMS ((char *, int *));
+static int arm_parse_cpu PARAMS ((char *));
+static int arm_parse_arch PARAMS ((char *));
+static int arm_parse_fpu PARAMS ((char *));
+#if 0 /* Suppressed - for now. */
+#if defined OBJ_COFF || defined OBJ_ELF
+static void arm_add_note PARAMS ((const char *, const char *, unsigned int));
+#endif
+#endif
+
/* Stuff needed to resolve the label ambiguity
As:
...
*/
symbolS * last_label_seen;
-static int label_is_thumb_function_name = false;
+static int label_is_thumb_function_name = FALSE;
-/* Literal stuff. */
+/* Literal Pool stuff. */
#define MAX_LITERAL_POOL_SIZE 1024
-typedef struct literalS
+/* Literal pool structure. Held on a per-section
+ and per-sub-section basis. */
+typedef struct literal_pool
+{
+ expressionS literals [MAX_LITERAL_POOL_SIZE];
+ unsigned int next_free_entry;
+ unsigned int id;
+ symbolS * symbol;
+ segT section;
+ subsegT sub_section;
+ struct literal_pool * next;
+} literal_pool;
+
+/* Pointer to a linked list of literal pools. */
+literal_pool * list_of_pools = NULL;
+
+static literal_pool * find_literal_pool PARAMS ((void));
+static literal_pool * find_or_make_literal_pool PARAMS ((void));
+
+static literal_pool *
+find_literal_pool ()
+{
+ literal_pool * pool;
+
+ for (pool = list_of_pools; pool != NULL; pool = pool->next)
+ {
+ if (pool->section == now_seg
+ && pool->sub_section == now_subseg)
+ break;
+ }
+
+ return pool;
+}
+
+static literal_pool *
+find_or_make_literal_pool ()
{
- struct expressionS exp;
- struct arm_it * inst;
-} literalT;
+ /* Next literal pool ID number. */
+ static unsigned int latest_pool_num = 1;
+ literal_pool * pool;
+
+ pool = find_literal_pool ();
+
+ if (pool == NULL)
+ {
+ /* Create a new pool. */
+ pool = (literal_pool *) xmalloc (sizeof (* pool));
+ if (! pool)
+ return NULL;
-literalT literals[MAX_LITERAL_POOL_SIZE];
+ pool->next_free_entry = 0;
+ pool->section = now_seg;
+ pool->sub_section = now_subseg;
+ pool->next = list_of_pools;
+ pool->symbol = NULL;
-/* Next free entry in the pool. */
-int next_literal_pool_place = 0;
+ /* Add it to the list. */
+ list_of_pools = pool;
+ }
-/* Next literal pool number. */
-int lit_pool_num = 1;
+ /* New pools, and emptied pools, will have a NULL symbol. */
+ if (pool->symbol == NULL)
+ {
+ pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
+ (valueT) 0, &zero_address_frag);
+ pool->id = latest_pool_num ++;
+ }
-symbolS * current_poolP = NULL;
+ /* Done. */
+ return pool;
+}
+/* Add the literal in the global 'inst'
+ structure to the relevent literal pool. */
static int
add_to_lit_pool ()
{
- int lit_count = 0;
+ literal_pool * pool;
+ unsigned int entry;
- if (current_poolP == NULL)
- current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
- (valueT) 0, &zero_address_frag);
+ pool = find_or_make_literal_pool ();
- /* Check if this literal value is already in the pool: */
- while (lit_count < next_literal_pool_place)
+ /* Check if this literal value is already in the pool. */
+ for (entry = 0; entry < pool->next_free_entry; entry ++)
{
- if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
- && inst.reloc.exp.X_op == O_constant
- && (literals[lit_count].exp.X_add_number
+ if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+ && (inst.reloc.exp.X_op == O_constant)
+ && (pool->literals[entry].X_add_number
== inst.reloc.exp.X_add_number)
- && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
+ && (pool->literals[entry].X_unsigned
+ == inst.reloc.exp.X_unsigned))
break;
- if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
- && inst.reloc.exp.X_op == O_symbol
- && (literals[lit_count].exp.X_add_number
+ if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+ && (inst.reloc.exp.X_op == O_symbol)
+ && (pool->literals[entry].X_add_number
== inst.reloc.exp.X_add_number)
- && (literals[lit_count].exp.X_add_symbol
+ && (pool->literals[entry].X_add_symbol
== inst.reloc.exp.X_add_symbol)
- && (literals[lit_count].exp.X_op_symbol
+ && (pool->literals[entry].X_op_symbol
== inst.reloc.exp.X_op_symbol))
break;
-
- lit_count++;
}
- if (lit_count == next_literal_pool_place) /* New entry. */
+ /* Do we need to create a new entry? */
+ if (entry == pool->next_free_entry)
{
- if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
+ if (entry >= MAX_LITERAL_POOL_SIZE)
{
- inst.error = _("Literal Pool Overflow");
+ inst.error = _("literal pool overflow");
return FAIL;
}
- literals[next_literal_pool_place].exp = inst.reloc.exp;
- lit_count = next_literal_pool_place++;
+ pool->literals[entry] = inst.reloc.exp;
+ pool->next_free_entry += 1;
}
- inst.reloc.exp.X_op = O_symbol;
- inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
- inst.reloc.exp.X_add_symbol = current_poolP;
+ inst.reloc.exp.X_op = O_symbol;
+ inst.reloc.exp.X_add_number = ((int) entry) * 4 - 8;
+ inst.reloc.exp.X_add_symbol = pool->symbol;
return SUCCESS;
}
S_SET_SEGMENT (symbolP, segment);
S_SET_VALUE (symbolP, valu);
- symbol_clear_list_pointers(symbolP);
+ symbol_clear_list_pointers (symbolP);
symbol_set_frag (symbolP, frag);
return FAIL;
}
-/* Check to see if an immediate can be computed as two seperate immediate
+/* Check to see if an immediate can be computed as two separate immediate
values, added together. We already know that this value cannot be
computed by just one ARM instruction. */
return val;
}
+\f
+#ifdef OBJ_ELF
+enum mstate
+{
+ MAP_DATA,
+ MAP_ARM,
+ MAP_THUMB
+};
+
+/* This code is to handle mapping symbols as defined in the ARM ELF spec.
+ (This text is taken from version B-02 of the spec):
+
+ 4.4.7 Mapping and tagging symbols
+
+ A section of an ARM ELF file can contain a mixture of ARM code,
+ Thumb code, and data. There are inline transitions between code
+ and data at literal pool boundaries. There can also be inline
+ transitions between ARM code and Thumb code, for example in
+ ARM-Thumb inter-working veneers. Linkers, machine-level
+ debuggers, profiling tools, and disassembly tools need to map
+ images accurately. For example, setting an ARM breakpoint on a
+ Thumb location, or in a literal pool, can crash the program
+ being debugged, ruining the debugging session.
+
+ ARM ELF entities are mapped (see section 4.4.7.1 below) and
+ tagged (see section 4.4.7.2 below) using local symbols (with
+ binding STB_LOCAL). To assist consumers, mapping and tagging
+ symbols should be collated first in the symbol table, before
+ other symbols with binding STB_LOCAL.
+
+ To allow properly collated mapping and tagging symbols to be
+ skipped by consumers that have no interest in them, the first
+ such symbol should have the name $m and its st_value field equal
+ to the total number of mapping and tagging symbols (including
+ the $m) in the symbol table.
+
+ 4.4.7.1 Mapping symbols
+
+ $a Labels the first byte of a sequence of ARM instructions.
+ Its type is STT_FUNC.
+
+ $d Labels the first byte of a sequence of data items.
+ Its type is STT_OBJECT.
+
+ $t Labels the first byte of a sequence of Thumb instructions.
+ Its type is STT_FUNC.
+
+ This list of mapping symbols may be extended in the future.
+
+ Section-relative mapping symbols
+
+ Mapping symbols defined in a section define a sequence of
+ half-open address intervals that cover the address range of the
+ section. Each interval starts at the address defined by a
+ mapping symbol, and continues up to, but not including, the
+ address defined by the next (in address order) mapping symbol or
+ the end of the section. A corollary is that there must be a
+ mapping symbol defined at the beginning of each section.
+ Consumers can ignore the size of a section-relative mapping
+ symbol. Producers can set it to 0.
+
+ Absolute mapping symbols
+
+ Because of the need to crystallize a Thumb address with the
+ Thumb-bit set, absolute symbol of type STT_FUNC (symbols of type
+ STT_FUNC defined in section SHN_ABS) need to be mapped with $a
+ or $t.
+
+ The extent of a mapping symbol defined in SHN_ABS is [st_value,
+ st_value + st_size), or [st_value, st_value + 1) if st_size = 0,
+ where [x, y) denotes the half-open address range from x,
+ inclusive, to y, exclusive.
+
+ In the absence of a mapping symbol, a consumer can interpret a
+ function symbol with an odd value as the Thumb code address
+ obtained by clearing the least significant bit of the
+ value. This interpretation is deprecated, and it may not work in
+ the future.
+
+ Note - the Tagging symbols ($b, $f, $p $m) have been dropped from
+ the EABI (which is still under development), so they are not
+ implemented here. */
+
+static void
+mapping_state (enum mstate state)
+{
+ static enum mstate mapstate = MAP_DATA;
+ symbolS * symbolP;
+ const char * symname;
+ int type;
+
+ if (mapstate == state)
+ /* The mapping symbol has already been emitted.
+ There is nothing else to do. */
+ return;
+
+ mapstate = state;
+
+ switch (state)
+ {
+ case MAP_DATA:
+ symname = "$d";
+ type = BSF_OBJECT;
+ break;
+ case MAP_ARM:
+ symname = "$a";
+ type = BSF_FUNCTION;
+ break;
+ case MAP_THUMB:
+ symname = "$t";
+ type = BSF_FUNCTION;
+ break;
+ default:
+ abort ();
+ }
+
+ symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
+ symbol_table_insert (symbolP);
+ symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
+
+ switch (state)
+ {
+ case MAP_ARM:
+ THUMB_SET_FUNC (symbolP, 0);
+ ARM_SET_THUMB (symbolP, 0);
+ ARM_SET_INTERWORK (symbolP, support_interwork);
+ break;
+
+ case MAP_THUMB:
+ THUMB_SET_FUNC (symbolP, 1);
+ ARM_SET_THUMB (symbolP, 1);
+ ARM_SET_INTERWORK (symbolP, support_interwork);
+ break;
+
+ case MAP_DATA:
+ default:
+ return;
+ }
+}
+
+/* When we change sections we need to issue a new mapping symbol. */
+
+void
+arm_elf_change_section (void)
+{
+ flagword flags;
+
+ if (!SEG_NORMAL (now_seg))
+ return;
+
+ flags = bfd_get_section_flags (stdoutput, now_seg);
+
+ /* We can ignore sections that only contain debug info. */
+ if ((flags & SEC_ALLOC) == 0)
+ return;
+
+ if (flags & SEC_CODE)
+ {
+ if (thumb_mode)
+ mapping_state (MAP_THUMB);
+ else
+ mapping_state (MAP_ARM);
+ }
+ else
+ /* This section does not contain code. Therefore it must contain data. */
+ mapping_state (MAP_DATA);
+}
+#else
+#define mapping_state(a)
+#endif /* OBJ_ELF */
+\f
+
static void
s_req (a)
int a ATTRIBUTE_UNUSED;
{
- as_bad (_("Invalid syntax for .req directive."));
+ as_bad (_("invalid syntax for .req directive"));
+}
+
+/* The .unreq directive deletes an alias which was previously defined
+ by .req. For example:
+
+ my_alias .req r11
+ .unreq my_alias */
+
+static void
+s_unreq (int a ATTRIBUTE_UNUSED)
+{
+ char *name;
+ char saved_char;
+
+ skip_whitespace (input_line_pointer);
+ name = input_line_pointer;
+
+ while (*input_line_pointer != 0
+ && *input_line_pointer != ' '
+ && *input_line_pointer != '\n')
+ ++input_line_pointer;
+
+ saved_char = *input_line_pointer;
+ *input_line_pointer = 0;
+
+ if (*name)
+ {
+ enum arm_reg_type req_type = arm_reg_parse_any (name);
+
+ if (req_type != REG_TYPE_MAX)
+ {
+ char *temp_name = name;
+ int req_no = arm_reg_parse (&temp_name, all_reg_maps[req_type].htab);
+
+ if (req_no != FAIL)
+ {
+ struct reg_entry *req_entry;
+
+ /* Check to see if this alias is a builtin one. */
+ req_entry = hash_delete (all_reg_maps[req_type].htab, name);
+
+ if (!req_entry)
+ as_bad (_("unreq: missing hash entry for \"%s\""), name);
+ else if (req_entry->builtin)
+ /* FIXME: We are deleting a built in register alias which
+ points to a const data structure, so we only need to
+ free up the memory used by the key in the hash table.
+ Unfortunately we have not recorded this value, so this
+ is a memory leak. */
+ /* FIXME: Should we issue a warning message ? */
+ ;
+ else
+ {
+ /* Deleting a user defined alias. We need to free the
+ key and the value, but fortunately the key is the same
+ as the value->name field. */
+ free ((char *) req_entry->name);
+ free (req_entry);
+ }
+ }
+ else
+ as_bad (_(".unreq: unrecognized symbol \"%s\""), name);
+ }
+ else
+ as_bad (_(".unreq: unrecognized symbol \"%s\""), name);
+ }
+ else
+ as_bad (_("invalid syntax for .unreq directive"));
+
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
}
static void
marking in_bss, then looking at s_skip for clues. */
subseg_set (bss_section, 0);
demand_empty_rest_of_line ();
+ mapping_state (MAP_DATA);
}
static void
s_ltorg (ignored)
int ignored ATTRIBUTE_UNUSED;
{
- int lit_count = 0;
+ unsigned int entry;
+ literal_pool * pool;
char sym_name[20];
- if (current_poolP == NULL)
+ pool = find_literal_pool ();
+ if (pool == NULL
+ || pool->symbol == NULL
+ || pool->next_free_entry == 0)
return;
/* Align pool as you have word accesses.
record_alignment (now_seg, 2);
- sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
+ sprintf (sym_name, "$$lit_\002%x", pool->id);
- symbol_locate (current_poolP, sym_name, now_seg,
+ symbol_locate (pool->symbol, sym_name, now_seg,
(valueT) frag_now_fix (), frag_now);
- symbol_table_insert (current_poolP);
+ symbol_table_insert (pool->symbol);
- ARM_SET_THUMB (current_poolP, thumb_mode);
+ ARM_SET_THUMB (pool->symbol, thumb_mode);
#if defined OBJ_COFF || defined OBJ_ELF
- ARM_SET_INTERWORK (current_poolP, support_interwork);
+ ARM_SET_INTERWORK (pool->symbol, support_interwork);
#endif
- while (lit_count < next_literal_pool_place)
+ for (entry = 0; entry < pool->next_free_entry; entry ++)
/* First output the expression in the instruction to the pool. */
- emit_expr (&(literals[lit_count++].exp), 4); /* .word */
+ emit_expr (&(pool->literals[entry]), 4); /* .word */
- next_literal_pool_place = 0;
- current_poolP = NULL;
+ /* Mark the pool as empty. */
+ pool->next_free_entry = 0;
+ pool->symbol = NULL;
}
/* Same as s_align_ptwo but align 0 => align 2. */
temp = get_absolute_expression ();
if (temp > max_alignment)
- as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
+ as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
else if (temp < 0)
{
- as_bad (_("Alignment negative. 0 assumed."));
+ as_bad (_("alignment negative. 0 assumed."));
temp = 0;
}
/* The following label is the name/address of the start of a Thumb function.
We need to know this for the interworking support. */
- label_is_thumb_function_name = true;
+ label_is_thumb_function_name = TRUE;
demand_empty_rest_of_line ();
}
if (*input_line_pointer != ',')
{
*end_name = 0;
- as_bad (_("Expected comma after name \"%s\""), name);
+ as_bad (_("expected comma after name \"%s\""), name);
*end_name = delim;
ignore_rest_of_line ();
return;
#endif
}
-/* If we change section we must dump the literal pool first. */
-
-static void
-arm_s_text (ignore)
- int ignore;
-{
- if (now_seg != text_section)
- s_ltorg (0);
-
-#ifdef OBJ_ELF
- obj_elf_text (ignore);
-#else
- s_text (ignore);
-#endif
-}
-
-static void
-arm_s_data (ignore)
- int ignore;
-{
- if (flag_readonly_data_in_text)
- {
- if (now_seg != text_section)
- s_ltorg (0);
- }
- else if (now_seg != data_section)
- s_ltorg (0);
-
-#ifdef OBJ_ELF
- obj_elf_data (ignore);
-#else
- s_data (ignore);
-#endif
-}
-
-#ifdef OBJ_ELF
-static void
-arm_s_section (ignore)
- int ignore;
-{
- s_ltorg (0);
-
- obj_elf_section (ignore);
-}
-#endif
-
static void
opcode_select (width)
int width;
coming from ARM mode, which is word-aligned. */
record_alignment (now_seg, 1);
}
+ mapping_state (MAP_THUMB);
break;
case 32:
if (thumb_mode)
{
- if ((cpu_variant & ARM_ANY) == ARM_EXT_V4T)
+ if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
as_bad (_("selected processor does not support ARM opcodes"));
thumb_mode = 0;
if (!need_pass_2)
- frag_align (2, 0, 0);
+ frag_align (2, 0, 0);
- record_alignment (now_seg, 1);
+ record_alignment (now_seg, 1);
}
+ mapping_state (MAP_ARM);
break;
default:
static void
end_of_line (str)
- char * str;
+ char *str;
{
skip_whitespace (str);
- if (* str != '\0')
- inst.error = _("Garbage following instruction");
+ if (*str != '\0' && !inst.error)
+ inst.error = _("garbage following instruction");
}
static int
int reg;
char * start = * str;
- if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_RN].htab)) != FAIL)
{
if (shift >= 0)
inst.instruction |= reg << shift;
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- sprintf (buff, _("Register expected, not '%.100s'"), start);
+ sprintf (buff, _("register expected, not '%.100s'"), start);
inst.error = buff;
return FAIL;
}
-static const struct asm_psr *
-arm_psr_parse (ccp)
- register char ** ccp;
-{
- char * start = * ccp;
- char c;
- char * p;
- const struct asm_psr * psr;
+/* A Intel Wireless MMX technology register
+ must be given at this point.
+ Shift is the place to put it in inst.instruction.
+ Restores input start point on err.
+ Returns the reg#, or FAIL. */
+
+static int
+wreg_required_here (str, shift, reg_type)
+ char ** str;
+ int shift;
+ enum wreg_type reg_type;
+{
+ static char buff [128];
+ int reg;
+ char * start = *str;
+
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_IWMMXT].htab)) != FAIL)
+ {
+ if (wr_register (reg)
+ && (reg_type == IWMMXT_REG_WR || reg_type == IWMMXT_REG_WR_OR_WC))
+ {
+ if (shift >= 0)
+ inst.instruction |= (reg ^ WR_PREFIX) << shift;
+ return reg;
+ }
+ else if (wc_register (reg)
+ && (reg_type == IWMMXT_REG_WC || reg_type == IWMMXT_REG_WR_OR_WC))
+ {
+ if (shift >= 0)
+ inst.instruction |= (reg ^ WC_PREFIX) << shift;
+ return reg;
+ }
+ else if ((wcg_register (reg) && reg_type == IWMMXT_REG_WCG))
+ {
+ if (shift >= 0)
+ inst.instruction |= ((reg ^ WC_PREFIX) - 8) << shift;
+ return reg;
+ }
+ }
+
+ /* Restore the start point, we may have got a reg of the wrong class. */
+ *str = start;
+
+ /* In the few cases where we might be able to accept
+ something else this error can be overridden. */
+ sprintf (buff, _("Intel Wireless MMX technology register expected, not '%.100s'"), start);
+ inst.error = buff;
+
+ return FAIL;
+}
+
+static const struct asm_psr *
+arm_psr_parse (ccp)
+ register char ** ccp;
+{
+ char * start = * ccp;
+ char c;
+ char * p;
+ const struct asm_psr * psr;
p = start;
static int
co_proc_number (str)
- char ** str;
+ char **str;
{
int processor, pchar;
+ char *start;
- skip_whitespace (* str);
+ skip_whitespace (*str);
+ start = *str;
/* The data sheet seems to imply that just a number on its own is valid
here, but the RISC iX assembler seems to accept a prefix 'p'. We will
accept either. */
- if (**str == 'p' || **str == 'P')
- (*str)++;
-
- pchar = *(*str)++;
- if (pchar >= '0' && pchar <= '9')
+ if ((processor = arm_reg_parse (str, all_reg_maps[REG_TYPE_CP].htab))
+ == FAIL)
{
- processor = pchar - '0';
- if (**str >= '0' && **str <= '9')
+ *str = start;
+
+ pchar = *(*str)++;
+ if (pchar >= '0' && pchar <= '9')
{
- processor = processor * 10 + *(*str)++ - '0';
- if (processor > 15)
+ processor = pchar - '0';
+ if (**str >= '0' && **str <= '9')
{
- inst.error = _("Illegal co-processor number");
- return FAIL;
+ processor = processor * 10 + *(*str)++ - '0';
+ if (processor > 15)
+ {
+ inst.error = _("illegal co-processor number");
+ return FAIL;
+ }
}
}
- }
- else
- {
- inst.error = _("Bad or missing co-processor number");
- return FAIL;
+ else
+ {
+ inst.error = _("bad or missing co-processor number");
+ return FAIL;
+ }
}
inst.instruction |= processor << 8;
int reg;
char * start = *str;
- if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_CN].htab)) != FAIL)
{
- reg &= 15;
inst.instruction |= reg << where;
return reg;
}
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- inst.error = _("Co-processor register expected");
+ inst.error = _("co-processor register expected");
/* Restore the start point. */
*str = start;
int reg;
char * start = * str;
- if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_FN].htab)) != FAIL)
{
- reg &= 7;
inst.instruction |= reg << where;
return reg;
}
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- inst.error = _("Floating point register expected");
+ inst.error = _("floating point register expected");
/* Restore the start point. */
*str = start;
}
static int
-cp_address_required_here (str)
+cp_address_required_here (str, wb_ok)
char ** str;
+ int wb_ok;
{
char * p = * str;
int pre_inc = 0;
{
p++;
- if (skip_past_comma (& p) == SUCCESS)
+ skip_whitespace (p);
+
+ if (*p == '\0')
{
- /* [Rn], #expr */
- write_back = WRITE_BACK;
+ /* As an extension to the official ARM syntax we allow:
+
+ [Rn]
+
+ as a short hand for:
+
+ [Rn,#0] */
+ inst.instruction |= PRE_INDEX | INDEX_UP;
+ *str = p;
+ return SUCCESS;
+ }
+
+ if (skip_past_comma (& p) == FAIL)
+ {
+ inst.error = _("comma expected after closing square bracket");
+ return FAIL;
+ }
- if (reg == REG_PC)
+ skip_whitespace (p);
+
+ if (*p == '#')
+ {
+ if (wb_ok)
{
- inst.error = _("pc may not be used in post-increment");
- return FAIL;
+ /* [Rn], #expr */
+ write_back = WRITE_BACK;
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("pc may not be used in post-increment");
+ return FAIL;
+ }
+
+ if (cp_address_offset (& p) == FAIL)
+ return FAIL;
}
+ else
+ pre_inc = PRE_INDEX | INDEX_UP;
+ }
+ else if (*p == '{')
+ {
+ int option;
- if (cp_address_offset (& p) == FAIL)
+ /* [Rn], {<expr>} */
+ p++;
+
+ skip_whitespace (p);
+
+ if (my_get_expression (& inst.reloc.exp, & p))
return FAIL;
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ option = inst.reloc.exp.X_add_number;
+
+ if (option > 255 || option < 0)
+ {
+ inst.error = _("'option' field too large");
+ return FAIL;
+ }
+
+ skip_whitespace (p);
+
+ if (*p != '}')
+ {
+ inst.error = _("'}' expected at end of 'option' field");
+ return FAIL;
+ }
+ else
+ {
+ p++;
+ inst.instruction |= option;
+ inst.instruction |= INDEX_UP;
+ }
+ }
+ else
+ {
+ inst.error = _("non-constant expressions for 'option' field not supported");
+ return FAIL;
+ }
}
else
- pre_inc = PRE_INDEX | INDEX_UP;
+ {
+ inst.error = _("# or { expected after comma");
+ return FAIL;
+ }
}
else
{
skip_whitespace (p);
- if (*p == '!')
+ if (wb_ok && *p == '!')
{
if (reg == REG_PC)
{
return SUCCESS;
}
+static int
+cp_byte_address_offset (str)
+ char ** str;
+{
+ int offset;
+
+ skip_whitespace (* str);
+
+ if (! is_immediate_prefix (**str))
+ {
+ inst.error = _("immediate expression expected");
+ return FAIL;
+ }
+
+ (*str)++;
+
+ if (my_get_expression (& inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ offset = inst.reloc.exp.X_add_number;
+
+ if (offset > 255 || offset < -255)
+ {
+ inst.error = _("offset too large");
+ return FAIL;
+ }
+
+ if (offset >= 0)
+ inst.instruction |= INDEX_UP;
+ else
+ offset = -offset;
+
+ inst.instruction |= offset;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+
+ return SUCCESS;
+}
+
+static int
+cp_byte_address_required_here (str)
+ char ** str;
+{
+ char * p = * str;
+ int pre_inc = 0;
+ int write_back = 0;
+
+ if (*p == '[')
+ {
+ int reg;
+
+ p++;
+ skip_whitespace (p);
+
+ if ((reg = reg_required_here (& p, 16)) == FAIL)
+ return FAIL;
+
+ skip_whitespace (p);
+
+ if (*p == ']')
+ {
+ p++;
+
+ if (skip_past_comma (& p) == SUCCESS)
+ {
+ /* [Rn], #expr */
+ write_back = WRITE_BACK;
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("pc may not be used in post-increment");
+ return FAIL;
+ }
+
+ if (cp_byte_address_offset (& p) == FAIL)
+ return FAIL;
+ }
+ else
+ pre_inc = PRE_INDEX | INDEX_UP;
+ }
+ else
+ {
+ /* '['Rn, #expr']'[!] */
+
+ if (skip_past_comma (& p) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return FAIL;
+ }
+
+ pre_inc = PRE_INDEX;
+
+ if (cp_byte_address_offset (& p) == FAIL)
+ return FAIL;
+
+ skip_whitespace (p);
+
+ if (*p++ != ']')
+ {
+ inst.error = _("missing ]");
+ return FAIL;
+ }
+
+ skip_whitespace (p);
+
+ if (*p == '!')
+ {
+ if (reg == REG_PC)
+ {
+ inst.error = _("pc may not be used with write-back");
+ return FAIL;
+ }
+
+ p++;
+ write_back = WRITE_BACK;
+ }
+ }
+ }
+ else
+ {
+ if (my_get_expression (&inst.reloc.exp, &p))
+ return FAIL;
+
+ inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+ inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = PRE_INDEX;
+ }
+
+ inst.instruction |= write_back | pre_inc;
+ *str = p;
+ return SUCCESS;
+}
+
static void
do_empty (str)
char * str;
if ( strcmp (str, "CPSR") == 0
|| strcmp (str, "SPSR") == 0
- /* Lower case versions for backwards compatability. */
+ /* Lower case versions for backwards compatibility. */
|| strcmp (str, "cpsr") == 0
|| strcmp (str, "spsr") == 0)
skip = 4;
- /* This is for backwards compatability with older toolchains. */
+ /* This is for backwards compatibility with older toolchains. */
else if ( strcmp (str, "cpsr_all") == 0
|| strcmp (str, "spsr_all") == 0)
skip = 8;
else
{
- inst.error = _("{C|S}PSR expected");
+ inst.error = _("CPSR or SPSR expected");
return;
}
if (value == (unsigned) FAIL)
{
- inst.error = _("Invalid constant");
+ inst.error = _("invalid constant");
return;
}
}
else /* [Rn] */
{
- skip_whitespace (str);
+ skip_whitespace (str);
- if (* str == '!')
- {
- str ++;
- inst.instruction |= WRITE_BACK;
- }
+ if (* str == '!')
+ {
+ str ++;
+ inst.instruction |= WRITE_BACK;
+ }
inst.instruction |= INDEX_UP | HWOFFSET_IMM;
pre_inc = 1;
/* Unpredictable result if rd or rn is R15. */
if (rd == REG_PC || rn == REG_PC)
as_tsktsk
- (_("Warning: Instruction unpredictable when using r15"));
+ (_("Warning: instruction unpredictable when using r15"));
if (skip_past_comma (& str) == FAIL
|| cp_reg_required_here (& str, 0) == FAIL)
/* ARM V5 (argument parse)
LDC2{L} <coproc>, <CRd>, <addressing mode>
STC2{L} <coproc>, <CRd>, <addressing mode>
- Instruction is not conditional, and has 0xf in the codition field.
+ Instruction is not conditional, and has 0xf in the condition field.
Otherwise, it's the same as LDC/STC. */
static void
inst.error = BAD_ARGS;
}
else if (skip_past_comma (& str) == FAIL
- || cp_address_required_here (& str) == FAIL)
+ || cp_address_required_here (&str, CP_WB_OK) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
end_of_line (str);
}
-/* THUMB V5 breakpoint instruction (argument parse)
- BKPT <immed_8>. */
-
+/* ARM v5TEJ. Jump to Jazelle code. */
static void
-do_t_bkpt (str)
+do_bxj (str)
char * str;
{
- expressionS expr;
- unsigned long number;
+ int reg;
skip_whitespace (str);
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (*str))
- str ++;
-
- memset (& expr, '\0', sizeof (expr));
- if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
- {
- inst.error = _("bad or missing expression");
- return;
- }
-
- number = expr.X_add_number;
-
- /* Check it fits an 8 bit unsigned. */
- if (number != (number & 0xff))
+ if ((reg = reg_required_here (&str, 0)) == FAIL)
{
- inst.error = _("immediate value out of range");
+ inst.error = BAD_ARGS;
return;
}
- inst.instruction |= number;
+ /* Note - it is not illegal to do a "bxj pc". Useless, but not illegal. */
+ if (reg == REG_PC)
+ as_tsktsk (_("use of r15 in bxj is not really useful"));
end_of_line (str);
}
-/* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
- Expects inst.instruction is set for BLX(1).
- Note: this is cloned from do_branch, and the reloc changed to be a
- new one that can cope with setting one extra bit (the H bit). */
+/* ARM V6 umaal (argument parse). */
static void
-do_branch25 (str)
- char * str;
+do_umaal (str)
+ char *str;
{
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
-
-#ifdef OBJ_ELF
- {
- char * save_in;
-
- /* ScottB: February 5, 1998 */
- /* Check to see of PLT32 reloc required for the instruction. */
- /* arm_parse_reloc() works on input_line_pointer.
- We actually want to parse the operands to the branch instruction
- passed in 'str'. Save the input pointer and restore it later. */
- save_in = input_line_pointer;
- input_line_pointer = str;
+ int rdlo, rdhi, rm, rs;
- if (inst.reloc.exp.X_op == O_symbol
- && *str == '('
- && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
- {
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
- inst.reloc.pc_rel = 0;
- /* Modify str to point to after parsed operands, otherwise
- end_of_line() will complain about the (PLT) left in str. */
- str = input_line_pointer;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
- inst.reloc.pc_rel = 1;
- }
+ skip_whitespace (str);
+ if ((rdlo = reg_required_here (& str, 12)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 8)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- input_line_pointer = save_in;
- }
-#else
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
- inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF */
+ if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
end_of_line (str);
}
-/* ARM V5 branch-link-exchange instruction (argument parse)
- BLX <target_addr> ie BLX(1)
- BLX{<condition>} <Rm> ie BLX(2)
- Unfortunately, there are two different opcodes for this mnemonic.
- So, the insns[].value is not used, and the code here zaps values
- into inst.instruction.
- Also, the <target_addr> can be 25 bits, hence has its own reloc. */
+/* ARM V6 strex (argument parse). */
-static void
-do_blx (str)
- char * str;
+static void
+do_strex (str)
+ char *str;
{
- char * mystr = str;
- int rm;
-
- skip_whitespace (mystr);
- rm = reg_required_here (& mystr, 0);
-
- /* The above may set inst.error. Ignore his opinion. */
- inst.error = 0;
+ int rd, rm, rn;
- if (rm != FAIL)
+ /* Parse Rd, Rm,. */
+ skip_whitespace (str);
+ if ((rd = reg_required_here (& str, 12)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL)
{
- /* Arg is a register.
- Use the condition code our caller put in inst.instruction.
- Pass ourselves off as a BX with a funny opcode. */
- inst.instruction |= 0x012fff30;
- do_bx (str);
+ inst.error = BAD_ARGS;
+ return;
}
- else
+ if (rd == REG_PC || rm == REG_PC)
{
- /* This must be is BLX <target address>, no condition allowed. */
- if (inst.instruction != COND_ALWAYS)
- {
- inst.error = BAD_COND;
- return;
- }
+ inst.error = BAD_PC;
+ return;
+ }
+ if (rd == rm)
+ {
+ inst.error = _("Rd equal to Rm or Rn yields unpredictable results");
+ return;
+ }
- inst.instruction = 0xfafffffe;
+ /* Skip past '['. */
+ if ((strlen (str) >= 1)
+ && strncmp (str, "[", 1) == 0)
+ str+=1;
+ skip_whitespace (str);
- /* Process like a B/BL, but with a different reloc.
- Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
- do_branch25 (str);
+ /* Parse Rn. */
+ if ((rn = reg_required_here (& str, 16)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+ else if (rn == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
+ if (rd == rn)
+ {
+ inst.error = _("Rd equal to Rm or Rn yields unpredictable results");
+ return;
}
+ skip_whitespace (str);
+
+ /* Skip past ']'. */
+ if ((strlen (str) >= 1)
+ && strncmp (str, "]", 1) == 0)
+ str+=1;
+
+ end_of_line (str);
}
-/* ARM V5 Thumb BLX (argument parse)
- BLX <target_addr> which is BLX(1)
- BLX <Rm> which is BLX(2)
- Unfortunately, there are two different opcodes for this mnemonic.
- So, the tinsns[].value is not used, and the code here zaps values
- into inst.instruction. */
+/* ARM V6 ssat (argument parse). */
static void
-do_t_blx (str)
- char * str;
+do_ssat (str)
+ char* str;
{
- char * mystr = str;
- int rm;
+ do_sat (&str, /*bias=*/-1);
+ end_of_line (str);
+}
- skip_whitespace (mystr);
- inst.instruction = 0x4780;
+/* ARM V6 usat (argument parse). */
- /* Note that this call is to the ARM register recognizer. BLX(2)
- uses the ARM register space, not the Thumb one, so a call to
- thumb_reg() would be wrong. */
- rm = reg_required_here (& mystr, 3);
- inst.error = 0;
+static void
+do_usat (str)
+ char* str;
+{
+ do_sat (&str, /*bias=*/0);
+ end_of_line (str);
+}
- if (rm != FAIL)
+static void
+do_sat (str, bias)
+ char **str;
+ int bias;
+{
+ int rd, rm;
+ expressionS expr;
+
+ skip_whitespace (*str);
+
+ /* Parse <Rd>, field. */
+ if ((rd = reg_required_here (str, 12)) == FAIL
+ || skip_past_comma (str) == FAIL)
{
- /* It's BLX(2). The .instruction was zapped with rm & is final. */
- inst.size = 2;
+ inst.error = BAD_ARGS;
+ return;
}
- else
+ if (rd == REG_PC)
{
- /* No ARM register. This must be BLX(1). Change the .instruction. */
- inst.instruction = 0xf7ffeffe;
- inst.size = 4;
+ inst.error = BAD_PC;
+ return;
+ }
- if (my_get_expression (& inst.reloc.exp, & mystr))
- return;
+ /* Parse #<immed>, field. */
+ if (is_immediate_prefix (**str))
+ (*str)++;
+ else
+ {
+ inst.error = _("immediate expression expected");
+ return;
+ }
+ if (my_get_expression (&expr, str))
+ {
+ inst.error = _("bad expression");
+ return;
+ }
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+ if (expr.X_add_number + bias < 0
+ || expr.X_add_number + bias > 31)
+ {
+ inst.error = _("immediate value out of range");
+ return;
+ }
+ inst.instruction |= (expr.X_add_number + bias) << 16;
+ if (skip_past_comma (str) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
- inst.reloc.pc_rel = 1;
+ /* Parse <Rm> field. */
+ if ((rm = reg_required_here (str, 0)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+ if (rm == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
}
- end_of_line (mystr);
+ if (skip_past_comma (str) == SUCCESS)
+ decode_shift (str, SHIFT_LSL_OR_ASR_IMMEDIATE);
}
-/* ARM V5 breakpoint instruction (argument parse)
- BKPT <16 bit unsigned immediate>
- Instruction is not conditional.
- The bit pattern given in insns[] has the COND_ALWAYS condition,
- and it is an error if the caller tried to override that. */
+/* ARM V6 ssat16 (argument parse). */
static void
-do_bkpt (str)
- char * str;
+do_ssat16 (str)
+ char *str;
{
- expressionS expr;
- unsigned long number;
+ do_sat16 (&str, /*bias=*/-1);
+ end_of_line (str);
+}
- skip_whitespace (str);
+static void
+do_usat16 (str)
+ char *str;
+{
+ do_sat16 (&str, /*bias=*/0);
+ end_of_line (str);
+}
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (* str))
- str++;
+static void
+do_sat16 (str, bias)
+ char **str;
+ int bias;
+{
+ int rd, rm;
+ expressionS expr;
- memset (& expr, '\0', sizeof (expr));
+ skip_whitespace (*str);
- if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
+ /* Parse the <Rd> field. */
+ if ((rd = reg_required_here (str, 12)) == FAIL
+ || skip_past_comma (str) == FAIL)
{
- inst.error = _("bad or missing expression");
+ inst.error = BAD_ARGS;
+ return;
+ }
+ if (rd == REG_PC)
+ {
+ inst.error = BAD_PC;
return;
}
- number = expr.X_add_number;
-
- /* Check it fits a 16 bit unsigned. */
- if (number != (number & 0xffff))
+ /* Parse #<immed>, field. */
+ if (is_immediate_prefix (**str))
+ (*str)++;
+ else
+ {
+ inst.error = _("immediate expression expected");
+ return;
+ }
+ if (my_get_expression (&expr, str))
+ {
+ inst.error = _("bad expression");
+ return;
+ }
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+ if (expr.X_add_number + bias < 0
+ || expr.X_add_number + bias > 15)
{
inst.error = _("immediate value out of range");
return;
}
+ inst.instruction |= (expr.X_add_number + bias) << 16;
+ if (skip_past_comma (str) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- /* Top 12 of 16 bits to bits 19:8. */
- inst.instruction |= (number & 0xfff0) << 4;
+ /* Parse <Rm> field. */
+ if ((rm = reg_required_here (str, 0)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+ if (rm == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
+}
- /* Bottom 4 of 16 bits to bits 3:0. */
- inst.instruction |= number & 0xf;
+/* ARM V6 srs (argument parse). */
+static void
+do_srs (str)
+ char* str;
+{
+ char *exclam;
+ skip_whitespace (str);
+ exclam = strchr (str, '!');
+ if (exclam)
+ *exclam = '\0';
+ do_cps_mode (&str);
+ if (exclam)
+ *exclam = '!';
+ if (*str == '!')
+ {
+ inst.instruction |= WRITE_BACK;
+ str++;
+ }
end_of_line (str);
}
-/* Xscale multiply-accumulate (argument parse)
- MIAcc acc0,Rm,Rs
- MIAPHcc acc0,Rm,Rs
- MIAxycc acc0,Rm,Rs. */
+/* ARM V6 SMMUL (argument parse). */
static void
-do_mia (str)
- char * str;
+do_smmul (str)
+ char* str;
{
- int rs;
- int rm;
-
- if (accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
-
- else if (skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || (rs = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
+ int rd, rm, rs;
+
+ skip_whitespace (str);
+ if ((rd = reg_required_here (&str, 16)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rs = reg_required_here (&str, 8)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- /* inst.instruction has now been zapped with both rm and rs. */
- else if (rm == REG_PC || rs == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
+ if (rd == REG_PC
+ || rm == REG_PC
+ || rs == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
- else
- end_of_line (str);
+ end_of_line (str);
+
}
-/* Xscale move-accumulator-register (argument parse)
-
- MARcc acc0,RdLo,RdHi. */
+/* ARM V6 SMLALD (argument parse). */
static void
-do_mar (str)
- char * str;
+do_smlald (str)
+ char* str;
{
- int rdlo, rdhi;
-
- if (accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
-
- else if (skip_past_comma (& str) == FAIL
- || (rdlo = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || (rdhi = reg_required_here (& str, 16)) == FAIL)
- inst.error = BAD_ARGS;
+ int rdlo, rdhi, rm, rs;
+ skip_whitespace (str);
+ if ((rdlo = reg_required_here (&str, 12)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rdhi = reg_required_here (&str, 16)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rs = reg_required_here (&str, 8)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- /* inst.instruction has now been zapped with both rdlo and rdhi. */
- else if (rdlo == REG_PC || rdhi == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
+ if (rdlo == REG_PC
+ || rdhi == REG_PC
+ || rm == REG_PC
+ || rs == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
- else
- end_of_line (str);
+ end_of_line (str);
}
-/* Xscale move-register-accumulator (argument parse)
-
- MRAcc RdLo,RdHi,acc0. */
+/* ARM V6 SMLAD (argument parse). Signed multiply accumulate dual.
+ smlad{x}{<cond>} Rd, Rm, Rs, Rn */
-static void
-do_mra (str)
- char * str;
+static void
+do_smlad (str)
+ char *str;
{
- int rdlo;
- int rdhi;
-
+ int rd, rm, rs, rn;
+
skip_whitespace (str);
+ if ((rd = reg_required_here (&str, 16)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rs = reg_required_here (&str, 8)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rn = reg_required_here (&str, 12)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (rd == REG_PC
+ || rn == REG_PC
+ || rs == REG_PC
+ || rm == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
- if ((rdlo = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
+ end_of_line (str);
+}
- else if (skip_past_comma (& str) == FAIL
- || (rdhi = reg_required_here (& str, 16)) == FAIL)
- inst.error = BAD_ARGS;
+/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
+ preserving the other bits.
- else if (skip_past_comma (& str) == FAIL
- || accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
+ setend <endian_specifier>, where <endian_specifier> is either
+ BE or LE. */
- /* inst.instruction has now been zapped with both rdlo and rdhi. */
- else if (rdlo == rdhi)
- inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
+static void
+do_setend (str)
+ char *str;
+{
+ if (do_endian_specifier (str))
+ inst.instruction |= 0x200;
+}
- else if (rdlo == REG_PC || rdhi == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
+/* Returns true if the endian-specifier indicates big-endianness. */
+
+static int
+do_endian_specifier (str)
+ char *str;
+{
+ int big_endian = 0;
+
+ skip_whitespace (str);
+ if (strlen (str) < 2)
+ inst.error = _("missing endian specifier");
+ else if (strncasecmp (str, "BE", 2) == 0)
+ {
+ str += 2;
+ big_endian = 1;
+ }
+ else if (strncasecmp (str, "LE", 2) == 0)
+ str += 2;
else
- end_of_line (str);
-}
+ inst.error = _("valid endian specifiers are be or le");
-/* ARMv5TE: Preload-Cache
+ end_of_line (str);
- PLD <addr_mode>
+ return big_endian;
+}
- Syntactically, like LDR with B=1, W=0, L=1. */
+/* ARM V6 SXTH.
-static void
-do_pld (str)
- char * str;
-{
- int rd;
+ SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
+ Condition defaults to COND_ALWAYS.
+ Error if any register uses R15. */
+static void
+do_sxth (str)
+ char *str;
+{
+ int rd, rm;
+ expressionS expr;
+ int rotation_clear_mask = 0xfffff3ff;
+ int rotation_eight_mask = 0x00000400;
+ int rotation_sixteen_mask = 0x00000800;
+ int rotation_twenty_four_mask = 0x00000c00;
+
skip_whitespace (str);
-
- if (* str != '[')
+ if ((rd = reg_required_here (&str, 12)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL)
{
- inst.error = _("'[' expected after PLD mnemonic");
+ inst.error = BAD_ARGS;
return;
}
- ++str;
+ else if (rd == REG_PC || rm == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
+
+ /* Zero out the rotation field. */
+ inst.instruction &= rotation_clear_mask;
+
+ /* Check for lack of optional rotation field. */
+ if (skip_past_comma (&str) == FAIL)
+ {
+ end_of_line (str);
+ return;
+ }
+
+ /* Move past 'ROR'. */
skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 16)) == FAIL)
- return;
-
+ if (strncasecmp (str, "ROR", 3) == 0)
+ str+=3;
+ else
+ {
+ inst.error = _("missing rotation field after comma");
+ return;
+ }
+
+ /* Get the immediate constant. */
skip_whitespace (str);
-
- if (*str == ']')
+ if (is_immediate_prefix (* str))
+ str++;
+ else
{
- /* [Rn], ... ? */
- ++str;
- skip_whitespace (str);
-
- /* Post-indexed addressing is not allowed with PLD. */
- if (skip_past_comma (&str) == SUCCESS)
- {
- inst.error
- = _("post-indexed expression used in preload instruction");
- return;
- }
- else if (*str == '!') /* [Rn]! */
- {
- inst.error = _("writeback used in preload instruction");
- ++str;
- }
- else /* [Rn] */
- inst.instruction |= INDEX_UP | PRE_INDEX;
+ inst.error = _("immediate expression expected");
+ return;
}
- else /* [Rn, ...] */
+
+ if (my_get_expression (&expr, &str))
{
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
-
- if (ldst_extend (&str) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (* str != ']')
- {
- inst.error = _("missing ]");
- return;
- }
+ inst.error = _("bad expression");
+ return;
+ }
- ++ str;
- skip_whitespace (str);
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ switch (expr.X_add_number)
+ {
+ case 0:
+ /* Rotation field has already been zeroed. */
+ break;
+ case 8:
+ inst.instruction |= rotation_eight_mask;
+ break;
- if (* str == '!') /* [Rn]! */
- {
- inst.error = _("writeback used in preload instruction");
- ++ str;
- }
+ case 16:
+ inst.instruction |= rotation_sixteen_mask;
+ break;
+
+ case 24:
+ inst.instruction |= rotation_twenty_four_mask;
+ break;
- inst.instruction |= PRE_INDEX;
+ default:
+ inst.error = _("rotation can be 8, 16, 24 or 0 when field is ommited");
+ break;
}
end_of_line (str);
+
}
-/* ARMv5TE load-consecutive (argument parse)
- Mode is like LDRH.
-
- LDRccD R, mode
- STRccD R, mode. */
+/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
+ extends it to 32-bits, and adds the result to a value in another
+ register. You can specify a rotation by 0, 8, 16, or 24 bits
+ before extracting the 16-bit value.
+ SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
+ Condition defaults to COND_ALWAYS.
+ Error if any register uses R15. */
-static void
-do_ldrd (str)
- char * str;
+static void
+do_sxtah (str)
+ char *str;
{
- int rd;
- int rn;
-
+ int rd, rn, rm;
+ expressionS expr;
+ int rotation_clear_mask = 0xfffff3ff;
+ int rotation_eight_mask = 0x00000400;
+ int rotation_sixteen_mask = 0x00000800;
+ int rotation_twenty_four_mask = 0x00000c00;
+
skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 12)) == FAIL)
+ if ((rd = reg_required_here (&str, 12)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rn = reg_required_here (&str, 16)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL)
{
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (& str) == FAIL
- || (rn = ld_mode_required_here (& str)) == FAIL)
+ else if (rd == REG_PC || rn == REG_PC || rm == REG_PC)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = BAD_PC;
return;
}
-
- /* inst.instruction has now been zapped with Rd and the addressing mode. */
- if (rd & 1) /* Unpredictable result if Rd is odd. */
+
+ /* Zero out the rotation field. */
+ inst.instruction &= rotation_clear_mask;
+
+ /* Check for lack of optional rotation field. */
+ if (skip_past_comma (&str) == FAIL)
{
- inst.error = _("Destination register must be even");
+ end_of_line (str);
return;
}
-
- if (rd == REG_LR)
+
+ /* Move past 'ROR'. */
+ skip_whitespace (str);
+ if (strncasecmp (str, "ROR", 3) == 0)
+ str+=3;
+ else
{
- inst.error = _("r14 not allowed here");
+ inst.error = _("missing rotation field after comma");
return;
}
-
- if (((rd == rn) || (rd + 1 == rn))
- && ((inst.instruction & WRITE_BACK)
- || (!(inst.instruction & PRE_INDEX))))
- as_warn (_("pre/post-indexing used when modified address register is destination"));
-
- /* For an index-register load, the index register must not overlap the
- destination (even if not write-back). */
- if ((inst.instruction & V4_STR_BIT) == 0
- && (inst.instruction & HWOFFSET_IMM) == 0)
+
+ /* Get the immediate constant. */
+ skip_whitespace (str);
+ if (is_immediate_prefix (* str))
+ str++;
+ else
{
- int rm = inst.instruction & 0x0000000f;
+ inst.error = _("immediate expression expected");
+ return;
+ }
+
+ if (my_get_expression (&expr, &str))
+ {
+ inst.error = _("bad expression");
+ return;
+ }
- if (rm == rd || (rm == rd + 1))
- as_warn (_("ldrd destination registers must not overlap index register"));
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ switch (expr.X_add_number)
+ {
+ case 0:
+ /* Rotation field has already been zeroed. */
+ break;
+
+ case 8:
+ inst.instruction |= rotation_eight_mask;
+ break;
+
+ case 16:
+ inst.instruction |= rotation_sixteen_mask;
+ break;
+
+ case 24:
+ inst.instruction |= rotation_twenty_four_mask;
+ break;
+
+ default:
+ inst.error = _("rotation can be 8, 16, 24 or 0 when field is ommited");
+ break;
}
end_of_line (str);
+
}
+
-/* Returns the index into fp_values of a floating point number,
- or -1 if not in the table. */
+/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
+ word at the specified address and the following word
+ respectively.
+ Unconditionally executed.
+ Error if Rn is R15.
+*/
-static int
-my_get_float_expression (str)
- char ** str;
+static void
+do_rfe (str)
+ char *str;
{
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- char * save_in;
- expressionS exp;
- int i;
- int j;
+ int rn;
- memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
+ skip_whitespace (str);
+
+ if ((rn = reg_required_here (&str, 16)) == FAIL)
+ return;
- /* Look for a raw floating point number. */
- if ((save_in = atof_ieee (*str, 'x', words)) != NULL
- && is_end_of_line[(unsigned char) *save_in])
+ if (rn == REG_PC)
{
- for (i = 0; i < NUM_FLOAT_VALS; i++)
- {
- for (j = 0; j < MAX_LITTLENUMS; j++)
- {
- if (words[j] != fp_values[i][j])
- break;
- }
-
- if (j == MAX_LITTLENUMS)
- {
- *str = save_in;
- return i;
- }
- }
+ inst.error = BAD_PC;
+ return;
}
- /* Try and parse a more complex expression, this will probably fail
- unless the code uses a floating point prefix (eg "0f"). */
- save_in = input_line_pointer;
- input_line_pointer = *str;
- if (expression (&exp) == absolute_section
- && exp.X_op == O_big
- && exp.X_add_number < 0)
+ skip_whitespace (str);
+
+ if (*str == '!')
{
- /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
- Ditto for 15. */
- if (gen_to_words (words, 5, (long) 15) == 0)
- {
- for (i = 0; i < NUM_FLOAT_VALS; i++)
- {
- for (j = 0; j < MAX_LITTLENUMS; j++)
- {
- if (words[j] != fp_values[i][j])
- break;
- }
-
- if (j == MAX_LITTLENUMS)
- {
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return i;
- }
- }
- }
+ inst.instruction |= WRITE_BACK;
+ str++;
}
-
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return -1;
+ end_of_line (str);
}
-/* Return true if anything in the expression is a bignum. */
+/* ARM V6 REV (Byte Reverse Word) reverses the byte order in a 32-bit
+ register (argument parse).
+ REV{<cond>} Rd, Rm.
+ Condition defaults to COND_ALWAYS.
+ Error if Rd or Rm are R15. */
-static int
-walk_no_bignums (sp)
- symbolS * sp;
+static void
+do_rev (str)
+ char* str;
{
- if (symbol_get_value_expression (sp)->X_op == O_big)
- return 1;
+ int rd, rm;
- if (symbol_get_value_expression (sp)->X_add_symbol)
- {
- return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
- || (symbol_get_value_expression (sp)->X_op_symbol
- && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
- }
+ skip_whitespace (str);
- return 0;
+ if ((rd = reg_required_here (&str, 12)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL)
+ inst.error = BAD_ARGS;
+
+ else if (rd == REG_PC || rm == REG_PC)
+ inst.error = BAD_PC;
+
+ else
+ end_of_line (str);
}
-static int
-my_get_expression (ep, str)
- expressionS * ep;
- char ** str;
+/* ARM V6 Perform Two Sixteen Bit Integer Additions. (argument parse).
+ QADD16{<cond>} <Rd>, <Rn>, <Rm>
+ Condition defaults to COND_ALWAYS.
+ Error if Rd, Rn or Rm are R15. */
+
+static void
+do_qadd16 (str)
+ char* str;
{
- char * save_in;
- segT seg;
+ int rd, rm, rn;
- save_in = input_line_pointer;
- input_line_pointer = *str;
- seg = expression (ep);
+ skip_whitespace (str);
-#ifdef OBJ_AOUT
- if (seg != absolute_section
- && seg != text_section
- && seg != data_section
- && seg != bss_section
- && seg != undefined_section)
- {
- inst.error = _("bad_segment");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
- }
-#endif
+ if ((rd = reg_required_here (&str, 12)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rn = reg_required_here (&str, 16)) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || (rm = reg_required_here (&str, 0)) == FAIL)
+ inst.error = BAD_ARGS;
- /* Get rid of any bignums now, so that we don't generate an error for which
- we can't establish a line number later on. Big numbers are never valid
- in instructions, which is where this routine is always called. */
- if (ep->X_op == O_big
- || (ep->X_add_symbol
- && (walk_no_bignums (ep->X_add_symbol)
- || (ep->X_op_symbol
- && walk_no_bignums (ep->X_op_symbol)))))
- {
- inst.error = _("Invalid constant");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
- }
+ else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
+ inst.error = BAD_PC;
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 0;
+ else
+ end_of_line (str);
}
-/* UNRESTRICT should be one if <shift> <register> is permitted for this
- instruction. */
+/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
+ PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
+ Condition defaults to COND_ALWAYS.
+ Error if Rd, Rn or Rm are R15. */
-static int
-decode_shift (str, unrestrict)
- char ** str;
- int unrestrict;
+static void
+do_pkhbt (str)
+ char* str;
{
- const struct asm_shift_name * shift;
- char * p;
- char c;
+ do_pkh_core (str, SHIFT_LSL_IMMEDIATE);
+}
- skip_whitespace (* str);
+/* ARM V6 PKHTB (Argument Parse). */
- for (p = * str; ISALPHA (* p); p ++)
- ;
+static void
+do_pkhtb (str)
+ char* str;
+{
+ do_pkh_core (str, SHIFT_ASR_IMMEDIATE);
+}
- if (p == * str)
+static void
+do_pkh_core (str, shift)
+ char* str;
+ int shift;
+{
+ int rd, rn, rm;
+
+ skip_whitespace (str);
+ if (((rd = reg_required_here (&str, 12)) == FAIL)
+ || (skip_past_comma (&str) == FAIL)
+ || ((rn = reg_required_here (&str, 16)) == FAIL)
+ || (skip_past_comma (&str) == FAIL)
+ || ((rm = reg_required_here (&str, 0)) == FAIL))
{
- inst.error = _("Shift expression expected");
- return FAIL;
+ inst.error = BAD_ARGS;
+ return;
}
- c = * p;
- * p = '\0';
- shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
- * p = c;
+ else if (rd == REG_PC || rn == REG_PC || rm == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
- if (shift == NULL)
+ /* Check for optional shift immediate constant. */
+ if (skip_past_comma (&str) == FAIL)
{
- inst.error = _("Shift expression expected");
- return FAIL;
+ if (shift == SHIFT_ASR_IMMEDIATE)
+ {
+ /* If the shift specifier is ommited, turn the instruction
+ into pkhbt rd, rm, rn. First, switch the instruction
+ code, and clear the rn and rm fields. */
+ inst.instruction &= 0xfff0f010;
+ /* Now, re-encode the registers. */
+ inst.instruction |= (rm << 16) | rn;
+ }
+ return;
}
- assert (shift->properties->index == shift_properties[shift->properties->index].index);
+ decode_shift (&str, shift);
+}
- if (shift->properties->index == SHIFT_RRX)
+/* ARM V6 Load Register Exclusive instruction (argument parse).
+ LDREX{<cond>} <Rd, [<Rn>]
+ Condition defaults to COND_ALWAYS.
+ Error if Rd or Rn are R15.
+ See ARMARMv6 A4.1.27: LDREX. */
+
+
+static void
+do_ldrex (str)
+ char * str;
+{
+ int rd, rn;
+
+ skip_whitespace (str);
+
+ /* Parse Rd. */
+ if (((rd = reg_required_here (&str, 12)) == FAIL)
+ || (skip_past_comma (&str) == FAIL))
{
- * str = p;
- inst.instruction |= shift->properties->bit_field;
- return SUCCESS;
+ inst.error = BAD_ARGS;
+ return;
+ }
+ else if (rd == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
}
+ skip_whitespace (str);
- skip_whitespace (p);
+ /* Skip past '['. */
+ if ((strlen (str) >= 1)
+ &&strncmp (str, "[", 1) == 0)
+ str+=1;
+ skip_whitespace (str);
- if (unrestrict && reg_required_here (& p, 8) != FAIL)
+ /* Parse Rn. */
+ if ((rn = reg_required_here (&str, 16)) == FAIL)
{
- inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
- * str = p;
- return SUCCESS;
+ inst.error = BAD_ARGS;
+ return;
}
- else if (! is_immediate_prefix (* p))
+ else if (rn == REG_PC)
{
- inst.error = (unrestrict
- ? _("shift requires register or #expression")
- : _("shift requires #expression"));
- * str = p;
- return FAIL;
+ inst.error = BAD_PC;
+ return;
}
+ skip_whitespace (str);
- inst.error = NULL;
- p ++;
+ /* Skip past ']'. */
+ if ((strlen (str) >= 1)
+ && strncmp (str, "]", 1) == 0)
+ str+=1;
+
+ end_of_line (str);
+}
- if (my_get_expression (& inst.reloc.exp, & p))
- return FAIL;
+/* ARM V6 change processor state instruction (argument parse)
+ CPS, CPSIE, CSPID . */
- /* Validate some simple #expressions. */
- if (inst.reloc.exp.X_op == O_constant)
+static void
+do_cps (str)
+ char * str;
+{
+ do_cps_mode (&str);
+ end_of_line (str);
+}
+
+static void
+do_cpsi (str)
+ char * str;
+{
+ do_cps_flags (&str, /*thumb_p=*/0);
+
+ if (skip_past_comma (&str) == SUCCESS)
{
- unsigned num = inst.reloc.exp.X_add_number;
+ skip_whitespace (str);
+ do_cps_mode (&str);
+ }
+ end_of_line (str);
+}
- /* Reject operations greater than 32. */
- if (num > 32
- /* Reject a shift of 0 unless the mode allows it. */
- || (num == 0 && shift->properties->allows_0 == 0)
- /* Reject a shift of 32 unless the mode allows it. */
- || (num == 32 && shift->properties->allows_32 == 0)
- )
- {
- /* As a special case we allow a shift of zero for
- modes that do not support it to be recoded as an
- logical shift left of zero (ie nothing). We warn
- about this though. */
- if (num == 0)
- {
- as_warn (_("Shift of 0 ignored."));
- shift = & shift_names[0];
- assert (shift->properties->index == SHIFT_LSL);
- }
- else
- {
- inst.error = _("Invalid immediate shift");
- return FAIL;
- }
- }
+static void
+do_cps_mode (str)
+ char **str;
+{
+ expressionS expr;
- /* Shifts of 32 are encoded as 0, for those shifts that
- support it. */
- if (num == 32)
- num = 0;
+ skip_whitespace (*str);
- inst.instruction |= (num << 7) | shift->properties->bit_field;
+ if (! is_immediate_prefix (**str))
+ {
+ inst.error = _("immediate expression expected");
+ return;
}
- else
+
+ (*str)++; /* Strip off the immediate signifier. */
+ if (my_get_expression (&expr, str))
{
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
- inst.reloc.pc_rel = 0;
- inst.instruction |= shift->properties->bit_field;
+ inst.error = _("bad expression");
+ return;
}
- * str = p;
- return SUCCESS;
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ /* The mode is a 5 bit field. Valid values are 0-31. */
+ if (((unsigned) expr.X_add_number) > 31
+ || (inst.reloc.exp.X_add_number) < 0)
+ {
+ inst.error = _("invalid constant");
+ return;
+ }
+
+ inst.instruction |= expr.X_add_number;
+ return;
}
-/* Do those data_ops which can take a negative immediate constant
- by altering the instuction. A bit of a hack really.
- MOV <-> MVN
- AND <-> BIC
- ADC <-> SBC
- by inverting the second operand, and
- ADD <-> SUB
- CMP <-> CMN
- by negating the second operand. */
+static void
+do_cps_flags (str, thumb_p)
+ char **str;
+ int thumb_p;
+{
+ struct cps_flag {
+ char character;
+ unsigned long arm_value;
+ unsigned long thumb_value;
+ };
+ static struct cps_flag flag_table[] = {
+ {'a', 0x100, 0x4 },
+ {'i', 0x080, 0x2 },
+ {'f', 0x040, 0x1 }
+ };
-static int
-negate_data_op (instruction, value)
- unsigned long * instruction;
- unsigned long value;
+ int saw_a_flag = 0;
+
+ skip_whitespace (*str);
+
+ /* Get the a, f and i flags. */
+ while (**str && **str != ',')
+ {
+ struct cps_flag *p;
+ struct cps_flag *q = flag_table + sizeof (flag_table)/sizeof (*p);
+ for (p = flag_table; p < q; ++p)
+ if (strncasecmp (*str, &p->character, 1) == 0)
+ {
+ inst.instruction |= (thumb_p ? p->thumb_value : p->arm_value);
+ saw_a_flag = 1;
+ break;
+ }
+ if (p == q)
+ {
+ inst.error = _("unrecognized flag");
+ return;
+ }
+ (*str)++;
+ }
+ if (!saw_a_flag)
+ inst.error = _("no 'a', 'i', or 'f' flags for 'cps'");
+}
+
+/* THUMB V5 breakpoint instruction (argument parse)
+ BKPT <immed_8>. */
+
+static void
+do_t_bkpt (str)
+ char * str;
{
- int op, new_inst;
- unsigned long negated, inverted;
+ expressionS expr;
+ unsigned long number;
- negated = validate_immediate (-value);
- inverted = validate_immediate (~value);
+ skip_whitespace (str);
- op = (*instruction >> DATA_OP_SHIFT) & 0xf;
- switch (op)
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (*str))
+ str ++;
+
+ memset (& expr, '\0', sizeof (expr));
+ if (my_get_expression (& expr, & str)
+ || (expr.X_op != O_constant
+ /* As a convenience we allow 'bkpt' without an operand. */
+ && expr.X_op != O_absent))
{
- /* First negates. */
- case OPCODE_SUB: /* ADD <-> SUB */
- new_inst = OPCODE_ADD;
- value = negated;
- break;
+ inst.error = _("bad expression");
+ return;
+ }
- case OPCODE_ADD:
- new_inst = OPCODE_SUB;
- value = negated;
- break;
+ number = expr.X_add_number;
- case OPCODE_CMP: /* CMP <-> CMN */
- new_inst = OPCODE_CMN;
- value = negated;
- break;
+ /* Check it fits an 8 bit unsigned. */
+ if (number != (number & 0xff))
+ {
+ inst.error = _("immediate value out of range");
+ return;
+ }
- case OPCODE_CMN:
- new_inst = OPCODE_CMP;
- value = negated;
- break;
+ inst.instruction |= number;
- /* Now Inverted ops. */
- case OPCODE_MOV: /* MOV <-> MVN */
- new_inst = OPCODE_MVN;
- value = inverted;
- break;
+ end_of_line (str);
+}
- case OPCODE_MVN:
- new_inst = OPCODE_MOV;
- value = inverted;
- break;
+/* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
+ Expects inst.instruction is set for BLX(1).
+ Note: this is cloned from do_branch, and the reloc changed to be a
+ new one that can cope with setting one extra bit (the H bit). */
- case OPCODE_AND: /* AND <-> BIC */
- new_inst = OPCODE_BIC;
- value = inverted;
- break;
+static void
+do_branch25 (str)
+ char * str;
+{
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return;
- case OPCODE_BIC:
- new_inst = OPCODE_AND;
- value = inverted;
- break;
+#ifdef OBJ_ELF
+ {
+ char * save_in;
- case OPCODE_ADC: /* ADC <-> SBC */
- new_inst = OPCODE_SBC;
- value = inverted;
- break;
+ /* ScottB: February 5, 1998 */
+ /* Check to see of PLT32 reloc required for the instruction. */
- case OPCODE_SBC:
- new_inst = OPCODE_ADC;
- value = inverted;
- break;
+ /* arm_parse_reloc() works on input_line_pointer.
+ We actually want to parse the operands to the branch instruction
+ passed in 'str'. Save the input pointer and restore it later. */
+ save_in = input_line_pointer;
+ input_line_pointer = str;
- /* We cannot do anything. */
- default:
- return FAIL;
- }
+ if (inst.reloc.exp.X_op == O_symbol
+ && *str == '('
+ && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ inst.reloc.pc_rel = 0;
+ /* Modify str to point to after parsed operands, otherwise
+ end_of_line() will complain about the (PLT) left in str. */
+ str = input_line_pointer;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
+ }
- if (value == (unsigned) FAIL)
- return FAIL;
+ input_line_pointer = save_in;
+ }
+#else
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
+#endif /* OBJ_ELF */
- *instruction &= OPCODE_MASK;
- *instruction |= new_inst << DATA_OP_SHIFT;
- return value;
+ end_of_line (str);
}
-static int
-data_op2 (str)
- char ** str;
+/* ARM V5 branch-link-exchange instruction (argument parse)
+ BLX <target_addr> ie BLX(1)
+ BLX{<condition>} <Rm> ie BLX(2)
+ Unfortunately, there are two different opcodes for this mnemonic.
+ So, the insns[].value is not used, and the code here zaps values
+ into inst.instruction.
+ Also, the <target_addr> can be 25 bits, hence has its own reloc. */
+
+static void
+do_blx (str)
+ char * str;
{
- int value;
- expressionS expr;
+ char * mystr = str;
+ int rm;
- skip_whitespace (* str);
+ skip_whitespace (mystr);
+ rm = reg_required_here (& mystr, 0);
- if (reg_required_here (str, 0) != FAIL)
- {
- if (skip_past_comma (str) == SUCCESS)
- /* Shift operation on register. */
- return decode_shift (str, NO_SHIFT_RESTRICT);
+ /* The above may set inst.error. Ignore his opinion. */
+ inst.error = 0;
- return SUCCESS;
+ if (rm != FAIL)
+ {
+ /* Arg is a register.
+ Use the condition code our caller put in inst.instruction.
+ Pass ourselves off as a BX with a funny opcode. */
+ inst.instruction |= 0x012fff30;
+ do_bx (str);
}
else
{
- /* Immediate expression. */
- if (is_immediate_prefix (**str))
+ /* This must be is BLX <target address>, no condition allowed. */
+ if (inst.instruction != COND_ALWAYS)
{
- (*str)++;
- inst.error = NULL;
+ inst.error = BAD_COND;
+ return;
+ }
- if (my_get_expression (&inst.reloc.exp, str))
- return FAIL;
+ inst.instruction = 0xfafffffe;
- if (inst.reloc.exp.X_add_symbol)
- {
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
- }
- else
- {
- if (skip_past_comma (str) == SUCCESS)
- {
- /* #x, y -- ie explicit rotation by Y. */
- if (my_get_expression (&expr, str))
- return FAIL;
-
- if (expr.X_op != O_constant)
- {
- inst.error = _("Constant expression expected");
- return FAIL;
- }
-
- /* Rotate must be a multiple of 2. */
- if (((unsigned) expr.X_add_number) > 30
- || (expr.X_add_number & 1) != 0
- || ((unsigned) inst.reloc.exp.X_add_number) > 255)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- inst.instruction |= INST_IMMEDIATE;
- inst.instruction |= inst.reloc.exp.X_add_number;
- inst.instruction |= expr.X_add_number << 7;
- return SUCCESS;
- }
+ /* Process like a B/BL, but with a different reloc.
+ Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
+ do_branch25 (str);
+ }
+}
- /* Implicit rotation, select a suitable one. */
- value = validate_immediate (inst.reloc.exp.X_add_number);
+/* ARM V5 Thumb BLX (argument parse)
+ BLX <target_addr> which is BLX(1)
+ BLX <Rm> which is BLX(2)
+ Unfortunately, there are two different opcodes for this mnemonic.
+ So, the tinsns[].value is not used, and the code here zaps values
+ into inst.instruction. */
- if (value == FAIL)
- {
- /* Can't be done. Perhaps the code reads something like
- "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
- if ((value = negate_data_op (&inst.instruction,
- inst.reloc.exp.X_add_number))
- == FAIL)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- }
+static void
+do_t_blx (str)
+ char * str;
+{
+ char * mystr = str;
+ int rm;
- inst.instruction |= value;
- }
+ skip_whitespace (mystr);
+ inst.instruction = 0x4780;
- inst.instruction |= INST_IMMEDIATE;
- return SUCCESS;
- }
+ /* Note that this call is to the ARM register recognizer. BLX(2)
+ uses the ARM register space, not the Thumb one, so a call to
+ thumb_reg() would be wrong. */
+ rm = reg_required_here (& mystr, 3);
+ inst.error = 0;
- (*str)++;
- inst.error = _("Register or shift expression expected");
- return FAIL;
+ if (rm != FAIL)
+ {
+ /* It's BLX(2). The .instruction was zapped with rm & is final. */
+ inst.size = 2;
}
-}
-
-static int
-fp_op2 (str)
- char ** str;
-{
- skip_whitespace (* str);
-
- if (fp_reg_required_here (str, 0) != FAIL)
- return SUCCESS;
else
{
- /* Immediate expression. */
- if (*((*str)++) == '#')
- {
- int i;
-
- inst.error = NULL;
-
- skip_whitespace (* str);
-
- /* First try and match exact strings, this is to guarantee
- that some formats will work even for cross assembly. */
-
- for (i = 0; fp_const[i]; i++)
- {
- if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
- {
- char *start = *str;
-
- *str += strlen (fp_const[i]);
- if (is_end_of_line[(unsigned char) **str])
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
- *str = start;
- }
- }
+ /* No ARM register. This must be BLX(1). Change the .instruction. */
+ inst.instruction = 0xf7ffeffe;
+ inst.size = 4;
- /* Just because we didn't get a match doesn't mean that the
- constant isn't valid, just that it is in a format that we
- don't automatically recognize. Try parsing it with
- the standard expression routines. */
- if ((i = my_get_float_expression (str)) >= 0)
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
+ if (my_get_expression (& inst.reloc.exp, & mystr))
+ return;
- inst.error = _("Invalid floating point immediate expression");
- return FAIL;
- }
- inst.error =
- _("Floating point register or immediate expression expected");
- return FAIL;
+ inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
}
+
+ end_of_line (mystr);
}
+/* ARM V5 breakpoint instruction (argument parse)
+ BKPT <16 bit unsigned immediate>
+ Instruction is not conditional.
+ The bit pattern given in insns[] has the COND_ALWAYS condition,
+ and it is an error if the caller tried to override that. */
+
static void
-do_arit (str)
- char * str;
+do_bkpt (str)
+ char * str;
{
+ expressionS expr;
+ unsigned long number;
+
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 16) == FAIL
- || skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (* str))
+ str++;
+
+ memset (& expr, '\0', sizeof (expr));
+
+ if (my_get_expression (& expr, & str)
+ || (expr.X_op != O_constant
+ /* As a convenience we allow 'bkpt' without an operand. */
+ && expr.X_op != O_absent))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("bad expression");
return;
}
- end_of_line (str);
- return;
-}
-
-static void
-do_adr (str)
- char * str;
-{
- /* This is a pseudo-op of the form "adr rd, label" to be converted
- into a relative address of the form "add rd, pc, #label-.-8". */
- skip_whitespace (str);
+ number = expr.X_add_number;
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
+ /* Check it fits a 16 bit unsigned. */
+ if (number != (number & 0xffff))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("immediate value out of range");
return;
}
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
- inst.reloc.pc_rel = 1;
+ /* Top 12 of 16 bits to bits 19:8. */
+ inst.instruction |= (number & 0xfff0) << 4;
+
+ /* Bottom 4 of 16 bits to bits 3:0. */
+ inst.instruction |= number & 0xf;
end_of_line (str);
}
+/* THUMB CPS instruction (argument parse). */
+
static void
-do_adrl (str)
- char * str;
+do_t_cps (str)
+ char *str;
{
- /* This is a pseudo-op of the form "adrl rd, label" to be converted
- into a relative address of the form:
- add rd, pc, #low(label-.-8)"
- add rd, rd, #high(label-.-8)" */
-
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
-
- return;
- }
-
+ do_cps_flags (&str, /*thumb_p=*/1);
end_of_line (str);
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
- inst.reloc.pc_rel = 1;
- inst.size = INSN_SIZE * 2;
-
- return;
}
+/* THUMB CPY instruction (argument parse). */
+
static void
-do_cmp (str)
- char * str;
+do_t_cpy (str)
+ char *str;
{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ thumb_mov_compare (str, THUMB_CPY);
+}
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+/* THUMB SETEND instruction (argument parse). */
- end_of_line (str);
- return;
+static void
+do_t_setend (str)
+ char *str;
+{
+ if (do_endian_specifier (str))
+ inst.instruction |= 0x8;
}
-static void
-do_mov (str)
+static unsigned long check_iwmmxt_insn PARAMS ((char *, enum iwmmxt_insn_type, int));
+
+/* Parse INSN_TYPE insn STR having a possible IMMEDIATE_SIZE immediate. */
+
+static unsigned long
+check_iwmmxt_insn (str, insn_type, immediate_size)
char * str;
+ enum iwmmxt_insn_type insn_type;
+ int immediate_size;
{
- skip_whitespace (str);
+ int reg = 0;
+ const char * inst_error;
+ expressionS expr;
+ unsigned long number;
- if (reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ inst_error = inst.error;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ skip_whitespace (str);
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
+ switch (insn_type)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
+ case check_rd:
+ if ((reg = reg_required_here (&str, 12)) == FAIL)
+ return FAIL;
+ break;
+
+ case check_wr:
+ if ((wreg_required_here (&str, 0, IWMMXT_REG_WR)) == FAIL)
+ return FAIL;
+ break;
+
+ case check_wrwr:
+ if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
+ return FAIL;
+ break;
+
+ case check_wrwrwr:
+ if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
+ return FAIL;
+ break;
+
+ case check_wrwrwcg:
+ if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 0, IWMMXT_REG_WCG) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tbcst:
+ if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmovmsk:
+ if ((reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmia:
+ if ((wreg_required_here (&str, 5, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 0) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmcrr:
+ if ((wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmrrc:
+ if ((reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmcr:
+ if ((wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tmrc:
+ if ((reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL))
+ return FAIL;
+ break;
+
+ case check_tinsr:
+ if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL))
+ return FAIL;
+ break;
+
+ case check_textrc:
+ if ((reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL))
+ return FAIL;
+ break;
+
+ case check_waligni:
+ if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL))
+ return FAIL;
+ break;
+
+ case check_textrm:
+ if ((reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL))
+ return FAIL;
+ break;
+
+ case check_wshufh:
+ if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
+ || skip_past_comma (&str) == FAIL))
+ return FAIL;
+ break;
+ }
+
+ if (immediate_size == 0)
+ {
+ end_of_line (str);
+ inst.error = inst_error;
+ return reg;
}
+ else
+ {
+ skip_whitespace (str);
+
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (* str))
+ str++;
- end_of_line (str);
- return;
+ memset (& expr, '\0', sizeof (expr));
+
+ if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
+ {
+ inst.error = _("bad or missing expression");
+ return FAIL;
+ }
+
+ number = expr.X_add_number;
+
+ if (number != (number & immediate_size))
+ {
+ inst.error = _("immediate value out of range");
+ return FAIL;
+ }
+ end_of_line (str);
+ inst.error = inst_error;
+ return number;
+ }
}
-static int
-ldst_extend (str)
- char ** str;
+static void
+do_iwmmxt_byte_addr (str)
+ char * str;
{
- int add = INDEX_UP;
-
- switch (**str)
- {
- case '#':
- case '$':
- (*str)++;
- if (my_get_expression (& inst.reloc.exp, str))
- return FAIL;
+ int op = (inst.instruction & 0x300) >> 8;
+ int reg;
- if (inst.reloc.exp.X_op == O_constant)
- {
- int value = inst.reloc.exp.X_add_number;
+ inst.instruction &= ~0x300;
+ inst.instruction |= (op & 1) << 22 | (op & 2) << 7;
- if (value < -4095 || value > 4095)
- {
- inst.error = _("address offset too large");
- return FAIL;
- }
+ skip_whitespace (str);
- if (value < 0)
- {
- value = -value;
- add = 0;
- }
+ if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || cp_byte_address_required_here (&str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ end_of_line (str);
- inst.instruction |= add | value;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
- inst.reloc.pc_rel = 0;
- }
- return SUCCESS;
+ if (wc_register (reg))
+ {
+ as_bad (_("non-word size not supported with control register"));
+ inst.instruction |= 0xf0000100;
+ inst.instruction &= ~0x00400000;
+ }
+}
- case '-':
- add = 0;
- /* Fall through. */
+static void
+do_iwmmxt_tandc (str)
+ char * str;
+{
+ int reg;
- case '+':
- (*str)++;
- /* Fall through. */
+ reg = check_iwmmxt_insn (str, check_rd, 0);
- default:
- if (reg_required_here (str, 0) == FAIL)
- return FAIL;
+ if (reg != REG_PC && !inst.error)
+ inst.error = _("only r15 allowed here");
+ return;
+}
- inst.instruction |= add | OFFSET_REG;
- if (skip_past_comma (str) == SUCCESS)
- return decode_shift (str, SHIFT_RESTRICT);
+static void
+do_iwmmxt_tbcst (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tbcst, 0);
- return SUCCESS;
- }
+ return;
}
static void
-do_ldst (str)
- char * str;
+do_iwmmxt_textrc (str)
+ char * str;
{
- int pre_inc = 0;
- int conflict_reg;
- int value;
+ unsigned long number;
- skip_whitespace (str);
+ if ((number = check_iwmmxt_insn (str, check_textrc, 7)) == (unsigned long) FAIL)
+ return;
- if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ inst.instruction |= number & 0x7;
+ return;
+}
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("Address expected");
- return;
- }
+static void
+do_iwmmxt_textrm (str)
+ char * str;
+{
+ unsigned long number;
- if (*str == '[')
- {
- int reg;
+ if ((number = check_iwmmxt_insn (str, check_textrm, 7)) == (unsigned long) FAIL)
+ return;
- str++;
+ inst.instruction |= number & 0x7;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_tinsr (str)
+ char * str;
+{
+ unsigned long number;
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
+ if ((number = check_iwmmxt_insn (str, check_tinsr, 7)) == (unsigned long) FAIL)
+ return;
- /* Conflicts can occur on stores as well as loads. */
- conflict_reg = (conflict_reg == reg);
+ inst.instruction |= number & 0x7;
+ return;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_tmcr (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmcr, 0);
- if (*str == ']')
- {
- str ++;
+ return;
+}
- if (skip_past_comma (&str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend (&str) == FAIL)
- return;
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- }
- else
- {
- /* [Rn] */
- skip_whitespace (str);
+static void
+do_iwmmxt_tmcrr (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmcrr, 0);
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
+ return;
+}
- inst.instruction |= INDEX_UP;
- pre_inc = 1;
- }
- }
- else
- {
- /* [Rn,...] */
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
+static void
+do_iwmmxt_tmia (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmia, 0);
- pre_inc = 1;
- if (ldst_extend (&str) == FAIL)
- return;
+ return;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_tmovmsk (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmovmsk, 0);
- if (*str++ != ']')
- {
- inst.error = _("missing ]");
- return;
- }
+ return;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_tmrc (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmrc, 0);
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
- }
- }
- else if (*str == '=')
- {
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
+ return;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_tmrrc (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_tmrrc, 0);
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ return;
+}
- if (inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
- {
- inst.error = _("Constant expression expected");
- return;
- }
+static void
+do_iwmmxt_torc (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_rd, 0);
+ return;
+}
- if (inst.reloc.exp.X_op == O_constant
- && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
- {
- /* This can be done with a mov instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
- inst.instruction |= (value & 0xfff);
- end_of_line (str);
- return;
- }
- else
- {
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
- {
- if (!inst.error)
- inst.error = _("literal pool insertion failed");
- return;
- }
+static void
+do_iwmmxt_waligni (str)
+ char * str;
+{
+ unsigned long number;
- /* Change the instruction exp to point to the pool. */
- inst.reloc.type = BFD_RELOC_ARM_LITERAL;
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
- }
- else
- {
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ if ((number = check_iwmmxt_insn (str, check_waligni, 7)) == (unsigned long) FAIL)
+ return;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
-#ifndef TE_WINCE
- /* PC rel adjust. */
- inst.reloc.exp.X_add_number -= 8;
-#endif
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
+ inst.instruction |= ((number & 0x7) << 20);
+ return;
+}
- inst.instruction |= (pre_inc ? PRE_INDEX : 0);
- end_of_line (str);
+static void
+do_iwmmxt_wmov (str)
+ char * str;
+{
+ if (check_iwmmxt_insn (str, check_wrwr, 0) == (unsigned long) FAIL)
+ return;
+
+ inst.instruction |= ((inst.instruction >> 16) & 0xf);
return;
}
static void
-do_ldstt (str)
- char * str;
+do_iwmmxt_word_addr (str)
+ char * str;
{
- int conflict_reg;
+ int op = (inst.instruction & 0x300) >> 8;
+ int reg;
+
+ inst.instruction &= ~0x300;
+ inst.instruction |= (op & 1) << 22 | (op & 2) << 7;
skip_whitespace (str);
- if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || cp_address_required_here (& str, CP_WB_OK) == FAIL)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
+ if (! inst.error)
+ inst.error = BAD_ARGS;
}
+ else
+ end_of_line (str);
- if (skip_past_comma (& str) == FAIL)
+ if (wc_register (reg))
{
- inst.error = _("Address expected");
- return;
+ if ((inst.instruction & COND_MASK) != COND_ALWAYS)
+ as_bad (_("conditional execution not supported with control register"));
+ if (op != 2)
+ as_bad (_("non-word size not supported with control register"));
+ inst.instruction |= 0xf0000100;
+ inst.instruction &= ~0x00400000;
}
+}
- if (*str == '[')
- {
- int reg;
-
- str++;
+static void
+do_iwmmxt_wrwr (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_wrwr, 0);
+
+ return;
+}
- skip_whitespace (str);
+static void
+do_iwmmxt_wrwrwcg (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_wrwrwcg, 0);
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
+ return;
+}
- /* ldrt/strt always use post-indexed addressing, so if the base is
- the same as Rd, we warn. */
- if (conflict_reg == reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
+static void
+do_iwmmxt_wrwrwr (str)
+ char * str;
+{
+ check_iwmmxt_insn (str, check_wrwrwr, 0);
- skip_whitespace (str);
+ return;
+}
- if (*str == ']')
- {
- str ++;
+static void
+do_iwmmxt_wshufh (str)
+ char * str;
+{
+ unsigned long number;
- if (skip_past_comma (&str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend (&str) == FAIL)
- return;
- }
- else
- {
- /* [Rn] */
- skip_whitespace (str);
+ if ((number = check_iwmmxt_insn (str, check_wshufh, 0xff)) == (unsigned long) FAIL)
+ return;
- /* Skip a write-back '!'. */
- if (*str == '!')
- str++;
+ inst.instruction |= ((number & 0xf0) << 16) | (number & 0xf);
+ return;
+}
- inst.instruction |= INDEX_UP;
- }
- }
- else
- {
- inst.error = _("post-indexed expression expected");
- return;
- }
- }
- else
- {
- inst.error = _("post-indexed expression expected");
- return;
- }
+static void
+do_iwmmxt_wzero (str)
+ char * str;
+{
+ if (check_iwmmxt_insn (str, check_wr, 0) == (unsigned long) FAIL)
+ return;
- end_of_line (str);
+ inst.instruction |= ((inst.instruction & 0xf) << 12) | ((inst.instruction & 0xf) << 16);
return;
}
-static int
-ldst_extend_v4 (str)
- char ** str;
+/* Xscale multiply-accumulate (argument parse)
+ MIAcc acc0,Rm,Rs
+ MIAPHcc acc0,Rm,Rs
+ MIAxycc acc0,Rm,Rs. */
+
+static void
+do_xsc_mia (str)
+ char * str;
{
- int add = INDEX_UP;
+ int rs;
+ int rm;
- switch (**str)
- {
- case '#':
- case '$':
- (*str)++;
- if (my_get_expression (& inst.reloc.exp, str))
- return FAIL;
+ if (accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
- if (inst.reloc.exp.X_op == O_constant)
- {
- int value = inst.reloc.exp.X_add_number;
+ else if (skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL)
+ inst.error = BAD_ARGS;
- if (value < -255 || value > 255)
- {
- inst.error = _("address offset too large");
- return FAIL;
- }
+ else if (skip_past_comma (& str) == FAIL
+ || (rs = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
- if (value < 0)
- {
- value = -value;
- add = 0;
- }
+ /* inst.instruction has now been zapped with both rm and rs. */
+ else if (rm == REG_PC || rs == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
- /* Halfword and signextension instructions have the
- immediate value split across bits 11..8 and bits 3..0. */
- inst.instruction |= (add | HWOFFSET_IMM
- | ((value >> 4) << 8) | (value & 0xF));
- }
- else
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- inst.reloc.pc_rel = 0;
- }
- return SUCCESS;
+ else
+ end_of_line (str);
+}
- case '-':
- add = 0;
- /* Fall through. */
+/* Xscale move-accumulator-register (argument parse)
- case '+':
- (*str)++;
- /* Fall through. */
+ MARcc acc0,RdLo,RdHi. */
- default:
- if (reg_required_here (str, 0) == FAIL)
- return FAIL;
+static void
+do_xsc_mar (str)
+ char * str;
+{
+ int rdlo, rdhi;
- inst.instruction |= add;
- return SUCCESS;
- }
+ if (accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
+
+ else if (skip_past_comma (& str) == FAIL
+ || (rdlo = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
+
+ else if (skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL)
+ inst.error = BAD_ARGS;
+
+ /* inst.instruction has now been zapped with both rdlo and rdhi. */
+ else if (rdlo == REG_PC || rdhi == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
+
+ else
+ end_of_line (str);
}
-/* Halfword and signed-byte load/store operations. */
+/* Xscale move-register-accumulator (argument parse)
+
+ MRAcc RdLo,RdHi,acc0. */
+
static void
-do_ldstv4 (str)
- char * str;
+do_xsc_mra (str)
+ char * str;
{
- int pre_inc = 0;
- int conflict_reg;
- int value;
+ int rdlo;
+ int rdhi;
skip_whitespace (str);
- if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("Address expected");
- return;
- }
-
- if (*str == '[')
- {
- int reg;
-
- str++;
+ if ((rdlo = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
- skip_whitespace (str);
+ else if (skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL)
+ inst.error = BAD_ARGS;
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
+ else if (skip_past_comma (& str) == FAIL
+ || accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
- /* Conflicts can occur on stores as well as loads. */
- conflict_reg = (conflict_reg == reg);
+ /* inst.instruction has now been zapped with both rdlo and rdhi. */
+ else if (rdlo == rdhi)
+ inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
- skip_whitespace (str);
+ else if (rdlo == REG_PC || rdhi == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
+ else
+ end_of_line (str);
+}
- if (*str == ']')
- {
- str ++;
+/* ARMv5TE: Preload-Cache
- if (skip_past_comma (&str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend_v4 (&str) == FAIL)
- return;
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- }
- else
- {
- /* [Rn] */
- inst.instruction |= HWOFFSET_IMM;
+ PLD <addr_mode>
- skip_whitespace (str);
+ Syntactically, like LDR with B=1, W=0, L=1. */
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
+static void
+do_pld (str)
+ char * str;
+{
+ int rd;
- inst.instruction |= INDEX_UP;
- pre_inc = 1;
- }
- }
- else
- {
- /* [Rn,...] */
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
+ skip_whitespace (str);
- pre_inc = 1;
- if (ldst_extend_v4 (&str) == FAIL)
- return;
+ if (* str != '[')
+ {
+ inst.error = _("'[' expected after PLD mnemonic");
+ return;
+ }
- skip_whitespace (str);
+ ++str;
+ skip_whitespace (str);
- if (*str++ != ']')
- {
- inst.error = _("missing ]");
- return;
- }
+ if ((rd = reg_required_here (& str, 16)) == FAIL)
+ return;
- skip_whitespace (str);
+ skip_whitespace (str);
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
- }
- }
- else if (*str == '=')
+ if (*str == ']')
{
- /* XXX Does this work correctly for half-word/byte ops? */
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
-
+ /* [Rn], ... ? */
+ ++str;
skip_whitespace (str);
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
- if (inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
+ /* Post-indexed addressing is not allowed with PLD. */
+ if (skip_past_comma (&str) == SUCCESS)
{
- inst.error = _("Constant expression expected");
+ inst.error
+ = _("post-indexed expression used in preload instruction");
return;
}
-
- if (inst.reloc.exp.X_op == O_constant)
+ else if (*str == '!') /* [Rn]! */
{
- value = validate_immediate (inst.reloc.exp.X_add_number);
+ inst.error = _("writeback used in preload instruction");
+ ++str;
+ }
+ else /* [Rn] */
+ inst.instruction |= INDEX_UP | PRE_INDEX;
+ }
+ else /* [Rn, ...] */
+ {
+ if (skip_past_comma (& str) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return;
+ }
- if (value != FAIL)
- {
- /* This can be done with a mov instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
- inst.instruction |= value & 0xfff;
- end_of_line (str);
- return;
- }
-
- value = validate_immediate (~ inst.reloc.exp.X_add_number);
+ if (ldst_extend (&str) == FAIL)
+ return;
- if (value != FAIL)
- {
- /* This can be done with a mvn instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
- inst.instruction |= value & 0xfff;
- end_of_line (str);
- return;
- }
- }
+ skip_whitespace (str);
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
+ if (* str != ']')
{
- if (!inst.error)
- inst.error = _("literal pool insertion failed");
+ inst.error = _("missing ]");
return;
}
- /* Change the instruction exp to point to the pool. */
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
- else
- {
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ ++ str;
+ skip_whitespace (str);
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
-#ifndef TE_WINCE
- /* PC rel adjust. */
- inst.reloc.exp.X_add_number -= 8;
-#endif
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
+ if (* str == '!') /* [Rn]! */
+ {
+ inst.error = _("writeback used in preload instruction");
+ ++ str;
+ }
+
+ inst.instruction |= PRE_INDEX;
}
- inst.instruction |= (pre_inc ? PRE_INDEX : 0);
end_of_line (str);
- return;
}
-static long
-reg_list (strp)
- char ** strp;
-{
- char * str = * strp;
- long range = 0;
- int another_range;
+/* ARMv5TE load-consecutive (argument parse)
+ Mode is like LDRH.
- /* We come back here if we get ranges concatenated by '+' or '|'. */
- do
- {
- another_range = 0;
+ LDRccD R, mode
+ STRccD R, mode. */
- if (*str == '{')
- {
- int in_range = 0;
- int cur_reg = -1;
+static void
+do_ldrd (str)
+ char * str;
+{
+ int rd;
+ int rn;
- str++;
- do
- {
- int reg;
+ skip_whitespace (str);
- skip_whitespace (str);
+ if ((rd = reg_required_here (& str, 12)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
- if ((reg = reg_required_here (& str, -1)) == FAIL)
- return FAIL;
+ if (skip_past_comma (& str) == FAIL
+ || (rn = ld_mode_required_here (& str)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- if (in_range)
- {
- int i;
+ /* inst.instruction has now been zapped with Rd and the addressing mode. */
+ if (rd & 1) /* Unpredictable result if Rd is odd. */
+ {
+ inst.error = _("destination register must be even");
+ return;
+ }
- if (reg <= cur_reg)
- {
- inst.error = _("Bad range in register list");
- return FAIL;
- }
+ if (rd == REG_LR)
+ {
+ inst.error = _("r14 not allowed here");
+ return;
+ }
- for (i = cur_reg + 1; i < reg; i++)
- {
- if (range & (1 << i))
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- i);
- else
- range |= 1 << i;
- }
- in_range = 0;
- }
+ if (((rd == rn) || (rd + 1 == rn))
+ && ((inst.instruction & WRITE_BACK)
+ || (!(inst.instruction & PRE_INDEX))))
+ as_warn (_("pre/post-indexing used when modified address register is destination"));
- if (range & (1 << reg))
- as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
- reg);
- else if (reg <= cur_reg)
- as_tsktsk (_("Warning: Register range not in ascending order"));
+ /* For an index-register load, the index register must not overlap the
+ destination (even if not write-back). */
+ if ((inst.instruction & V4_STR_BIT) == 0
+ && (inst.instruction & HWOFFSET_IMM) == 0)
+ {
+ int rm = inst.instruction & 0x0000000f;
- range |= 1 << reg;
- cur_reg = reg;
+ if (rm == rd || (rm == rd + 1))
+ as_warn (_("ldrd destination registers must not overlap index register"));
+ }
+
+ end_of_line (str);
+}
+
+/* Returns the index into fp_values of a floating point number,
+ or -1 if not in the table. */
+
+static int
+my_get_float_expression (str)
+ char ** str;
+{
+ LITTLENUM_TYPE words[MAX_LITTLENUMS];
+ char * save_in;
+ expressionS exp;
+ int i;
+ int j;
+
+ memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
+
+ /* Look for a raw floating point number. */
+ if ((save_in = atof_ieee (*str, 'x', words)) != NULL
+ && is_end_of_line[(unsigned char) *save_in])
+ {
+ for (i = 0; i < NUM_FLOAT_VALS; i++)
+ {
+ for (j = 0; j < MAX_LITTLENUMS; j++)
+ {
+ if (words[j] != fp_values[i][j])
+ break;
}
- while (skip_past_comma (&str) != FAIL
- || (in_range = 1, *str++ == '-'));
- str--;
- skip_whitespace (str);
- if (*str++ != '}')
+ if (j == MAX_LITTLENUMS)
{
- inst.error = _("Missing `}'");
- return FAIL;
+ *str = save_in;
+ return i;
+ }
+ }
+ }
+
+ /* Try and parse a more complex expression, this will probably fail
+ unless the code uses a floating point prefix (eg "0f"). */
+ save_in = input_line_pointer;
+ input_line_pointer = *str;
+ if (expression (&exp) == absolute_section
+ && exp.X_op == O_big
+ && exp.X_add_number < 0)
+ {
+ /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
+ Ditto for 15. */
+ if (gen_to_words (words, 5, (long) 15) == 0)
+ {
+ for (i = 0; i < NUM_FLOAT_VALS; i++)
+ {
+ for (j = 0; j < MAX_LITTLENUMS; j++)
+ {
+ if (words[j] != fp_values[i][j])
+ break;
+ }
+
+ if (j == MAX_LITTLENUMS)
+ {
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return i;
+ }
}
}
+ }
+
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return -1;
+}
+
+/* Return TRUE if anything in the expression is a bignum. */
+
+static int
+walk_no_bignums (sp)
+ symbolS * sp;
+{
+ if (symbol_get_value_expression (sp)->X_op == O_big)
+ return 1;
+
+ if (symbol_get_value_expression (sp)->X_add_symbol)
+ {
+ return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+ || (symbol_get_value_expression (sp)->X_op_symbol
+ && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
+ }
+
+ return 0;
+}
+
+static int in_my_get_expression = 0;
+
+static int
+my_get_expression (ep, str)
+ expressionS * ep;
+ char ** str;
+{
+ char * save_in;
+ segT seg;
+
+ save_in = input_line_pointer;
+ input_line_pointer = *str;
+ in_my_get_expression = 1;
+ seg = expression (ep);
+ in_my_get_expression = 0;
+
+ if (ep->X_op == O_illegal)
+ {
+ /* We found a bad expression in md_operand(). */
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
+
+#ifdef OBJ_AOUT
+ if (seg != absolute_section
+ && seg != text_section
+ && seg != data_section
+ && seg != bss_section
+ && seg != undefined_section)
+ {
+ inst.error = _("bad_segment");
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
+#endif
+
+ /* Get rid of any bignums now, so that we don't generate an error for which
+ we can't establish a line number later on. Big numbers are never valid
+ in instructions, which is where this routine is always called. */
+ if (ep->X_op == O_big
+ || (ep->X_add_symbol
+ && (walk_no_bignums (ep->X_add_symbol)
+ || (ep->X_op_symbol
+ && walk_no_bignums (ep->X_op_symbol)))))
+ {
+ inst.error = _("invalid constant");
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
+
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 0;
+}
+
+/* We handle all bad expressions here, so that we can report the faulty
+ instruction in the error message. */
+void
+md_operand (expr)
+ expressionS *expr;
+{
+ if (in_my_get_expression)
+ {
+ expr->X_op = O_illegal;
+ if (inst.error == NULL)
+ inst.error = _("bad expression");
+ }
+}
+
+/* KIND indicates what kind of shifts are accepted. */
+
+static int
+decode_shift (str, kind)
+ char ** str;
+ int kind;
+{
+ const struct asm_shift_name * shift;
+ char * p;
+ char c;
+
+ skip_whitespace (* str);
+
+ for (p = * str; ISALPHA (* p); p ++)
+ ;
+
+ if (p == * str)
+ {
+ inst.error = _("shift expression expected");
+ return FAIL;
+ }
+
+ c = * p;
+ * p = '\0';
+ shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
+ * p = c;
+
+ if (shift == NULL)
+ {
+ inst.error = _("shift expression expected");
+ return FAIL;
+ }
+
+ assert (shift->properties->index == shift_properties[shift->properties->index].index);
+
+ if (kind == SHIFT_LSL_OR_ASR_IMMEDIATE
+ && shift->properties->index != SHIFT_LSL
+ && shift->properties->index != SHIFT_ASR)
+ {
+ inst.error = _("'LSL' or 'ASR' required");
+ return FAIL;
+ }
+ else if (kind == SHIFT_LSL_IMMEDIATE
+ && shift->properties->index != SHIFT_LSL)
+ {
+ inst.error = _("'LSL' required");
+ return FAIL;
+ }
+ else if (kind == SHIFT_ASR_IMMEDIATE
+ && shift->properties->index != SHIFT_ASR)
+ {
+ inst.error = _("'ASR' required");
+ return FAIL;
+ }
+
+ if (shift->properties->index == SHIFT_RRX)
+ {
+ * str = p;
+ inst.instruction |= shift->properties->bit_field;
+ return SUCCESS;
+ }
+
+ skip_whitespace (p);
+
+ if (kind == NO_SHIFT_RESTRICT && reg_required_here (& p, 8) != FAIL)
+ {
+ inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
+ * str = p;
+ return SUCCESS;
+ }
+ else if (! is_immediate_prefix (* p))
+ {
+ inst.error = (NO_SHIFT_RESTRICT
+ ? _("shift requires register or #expression")
+ : _("shift requires #expression"));
+ * str = p;
+ return FAIL;
+ }
+
+ inst.error = NULL;
+ p ++;
+
+ if (my_get_expression (& inst.reloc.exp, & p))
+ return FAIL;
+
+ /* Validate some simple #expressions. */
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ unsigned num = inst.reloc.exp.X_add_number;
+
+ /* Reject operations greater than 32. */
+ if (num > 32
+ /* Reject a shift of 0 unless the mode allows it. */
+ || (num == 0 && shift->properties->allows_0 == 0)
+ /* Reject a shift of 32 unless the mode allows it. */
+ || (num == 32 && shift->properties->allows_32 == 0)
+ )
+ {
+ /* As a special case we allow a shift of zero for
+ modes that do not support it to be recoded as an
+ logical shift left of zero (ie nothing). We warn
+ about this though. */
+ if (num == 0)
+ {
+ as_warn (_("shift of 0 ignored."));
+ shift = & shift_names[0];
+ assert (shift->properties->index == SHIFT_LSL);
+ }
+ else
+ {
+ inst.error = _("invalid immediate shift");
+ return FAIL;
+ }
+ }
+
+ /* Shifts of 32 are encoded as 0, for those shifts that
+ support it. */
+ if (num == 32)
+ num = 0;
+
+ inst.instruction |= (num << 7) | shift->properties->bit_field;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+ inst.reloc.pc_rel = 0;
+ inst.instruction |= shift->properties->bit_field;
+ }
+
+ * str = p;
+ return SUCCESS;
+}
+
+/* Do those data_ops which can take a negative immediate constant
+ by altering the instruction. A bit of a hack really.
+ MOV <-> MVN
+ AND <-> BIC
+ ADC <-> SBC
+ by inverting the second operand, and
+ ADD <-> SUB
+ CMP <-> CMN
+ by negating the second operand. */
+
+static int
+negate_data_op (instruction, value)
+ unsigned long * instruction;
+ unsigned long value;
+{
+ int op, new_inst;
+ unsigned long negated, inverted;
+
+ negated = validate_immediate (-value);
+ inverted = validate_immediate (~value);
+
+ op = (*instruction >> DATA_OP_SHIFT) & 0xf;
+ switch (op)
+ {
+ /* First negates. */
+ case OPCODE_SUB: /* ADD <-> SUB */
+ new_inst = OPCODE_ADD;
+ value = negated;
+ break;
+
+ case OPCODE_ADD:
+ new_inst = OPCODE_SUB;
+ value = negated;
+ break;
+
+ case OPCODE_CMP: /* CMP <-> CMN */
+ new_inst = OPCODE_CMN;
+ value = negated;
+ break;
+
+ case OPCODE_CMN:
+ new_inst = OPCODE_CMP;
+ value = negated;
+ break;
+
+ /* Now Inverted ops. */
+ case OPCODE_MOV: /* MOV <-> MVN */
+ new_inst = OPCODE_MVN;
+ value = inverted;
+ break;
+
+ case OPCODE_MVN:
+ new_inst = OPCODE_MOV;
+ value = inverted;
+ break;
+
+ case OPCODE_AND: /* AND <-> BIC */
+ new_inst = OPCODE_BIC;
+ value = inverted;
+ break;
+
+ case OPCODE_BIC:
+ new_inst = OPCODE_AND;
+ value = inverted;
+ break;
+
+ case OPCODE_ADC: /* ADC <-> SBC */
+ new_inst = OPCODE_SBC;
+ value = inverted;
+ break;
+
+ case OPCODE_SBC:
+ new_inst = OPCODE_ADC;
+ value = inverted;
+ break;
+
+ /* We cannot do anything. */
+ default:
+ return FAIL;
+ }
+
+ if (value == (unsigned) FAIL)
+ return FAIL;
+
+ *instruction &= OPCODE_MASK;
+ *instruction |= new_inst << DATA_OP_SHIFT;
+ return value;
+}
+
+static int
+data_op2 (str)
+ char ** str;
+{
+ int value;
+ expressionS expr;
+
+ skip_whitespace (* str);
+
+ if (reg_required_here (str, 0) != FAIL)
+ {
+ if (skip_past_comma (str) == SUCCESS)
+ /* Shift operation on register. */
+ return decode_shift (str, NO_SHIFT_RESTRICT);
+
+ return SUCCESS;
+ }
+ else
+ {
+ /* Immediate expression. */
+ if (is_immediate_prefix (**str))
+ {
+ (*str)++;
+ inst.error = NULL;
+
+ if (my_get_expression (&inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_add_symbol)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.reloc.pc_rel = 0;
+ }
+ else
+ {
+ if (skip_past_comma (str) == SUCCESS)
+ {
+ /* #x, y -- ie explicit rotation by Y. */
+ if (my_get_expression (&expr, str))
+ return FAIL;
+
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("constant expression expected");
+ return FAIL;
+ }
+
+ /* Rotate must be a multiple of 2. */
+ if (((unsigned) expr.X_add_number) > 30
+ || (expr.X_add_number & 1) != 0
+ || ((unsigned) inst.reloc.exp.X_add_number) > 255)
+ {
+ inst.error = _("invalid constant");
+ return FAIL;
+ }
+ inst.instruction |= INST_IMMEDIATE;
+ inst.instruction |= inst.reloc.exp.X_add_number;
+ inst.instruction |= expr.X_add_number << 7;
+ return SUCCESS;
+ }
+
+ /* Implicit rotation, select a suitable one. */
+ value = validate_immediate (inst.reloc.exp.X_add_number);
+
+ if (value == FAIL)
+ {
+ /* Can't be done. Perhaps the code reads something like
+ "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
+ if ((value = negate_data_op (&inst.instruction,
+ inst.reloc.exp.X_add_number))
+ == FAIL)
+ {
+ inst.error = _("invalid constant");
+ return FAIL;
+ }
+ }
+
+ inst.instruction |= value;
+ }
+
+ inst.instruction |= INST_IMMEDIATE;
+ return SUCCESS;
+ }
+
+ (*str)++;
+ inst.error = _("register or shift expression expected");
+ return FAIL;
+ }
+}
+
+static int
+fp_op2 (str)
+ char ** str;
+{
+ skip_whitespace (* str);
+
+ if (fp_reg_required_here (str, 0) != FAIL)
+ return SUCCESS;
+ else
+ {
+ /* Immediate expression. */
+ if (*((*str)++) == '#')
+ {
+ int i;
+
+ inst.error = NULL;
+
+ skip_whitespace (* str);
+
+ /* First try and match exact strings, this is to guarantee
+ that some formats will work even for cross assembly. */
+
+ for (i = 0; fp_const[i]; i++)
+ {
+ if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
+ {
+ char *start = *str;
+
+ *str += strlen (fp_const[i]);
+ if (is_end_of_line[(unsigned char) **str])
+ {
+ inst.instruction |= i + 8;
+ return SUCCESS;
+ }
+ *str = start;
+ }
+ }
+
+ /* Just because we didn't get a match doesn't mean that the
+ constant isn't valid, just that it is in a format that we
+ don't automatically recognize. Try parsing it with
+ the standard expression routines. */
+ if ((i = my_get_float_expression (str)) >= 0)
+ {
+ inst.instruction |= i + 8;
+ return SUCCESS;
+ }
+
+ inst.error = _("invalid floating point immediate expression");
+ return FAIL;
+ }
+ inst.error =
+ _("floating point register or immediate expression expected");
+ return FAIL;
+ }
+}
+
+static void
+do_arit (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_adr (str)
+ char * str;
+{
+ /* This is a pseudo-op of the form "adr rd, label" to be converted
+ into a relative address of the form "add rd, pc, #label-.-8". */
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || my_get_expression (&inst.reloc.exp, &str))
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ /* Frag hacking will turn this into a sub instruction if the offset turns
+ out to be negative. */
+ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
+ inst.reloc.pc_rel = 1;
+
+ end_of_line (str);
+}
+
+static void
+do_adrl (str)
+ char * str;
+{
+ /* This is a pseudo-op of the form "adrl rd, label" to be converted
+ into a relative address of the form:
+ add rd, pc, #low(label-.-8)"
+ add rd, rd, #high(label-.-8)" */
+
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || my_get_expression (&inst.reloc.exp, &str))
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+
+ return;
+ }
+
+ end_of_line (str);
+ /* Frag hacking will turn this into a sub instruction if the offset turns
+ out to be negative. */
+ inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+ inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
+ inst.reloc.pc_rel = 1;
+ inst.size = INSN_SIZE * 2;
+
+ return;
+}
+
+static void
+do_cmp (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_mov (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static int
+ldst_extend (str)
+ char ** str;
+{
+ int add = INDEX_UP;
+
+ switch (**str)
+ {
+ case '#':
+ case '$':
+ (*str)++;
+ if (my_get_expression (& inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ int value = inst.reloc.exp.X_add_number;
+
+ if (value < -4095 || value > 4095)
+ {
+ inst.error = _("address offset too large");
+ return FAIL;
+ }
+
+ if (value < 0)
+ {
+ value = -value;
+ add = 0;
+ }
+
+ inst.instruction |= add | value;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+ inst.reloc.pc_rel = 0;
+ }
+ return SUCCESS;
+
+ case '-':
+ add = 0;
+ /* Fall through. */
+
+ case '+':
+ (*str)++;
+ /* Fall through. */
+
+ default:
+ if (reg_required_here (str, 0) == FAIL)
+ return FAIL;
+
+ inst.instruction |= add | OFFSET_REG;
+ if (skip_past_comma (str) == SUCCESS)
+ return decode_shift (str, SHIFT_IMMEDIATE);
+
+ return SUCCESS;
+ }
+}
+
+static void
+do_ldst (str)
+ char * str;
+{
+ int pre_inc = 0;
+ int conflict_reg;
+ int value;
+
+ skip_whitespace (str);
+
+ if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL)
+ {
+ inst.error = _("address expected");
+ return;
+ }
+
+ if (*str == '[')
+ {
+ int reg;
+
+ str++;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ /* Conflicts can occur on stores as well as loads. */
+ conflict_reg = (conflict_reg == reg);
+
+ skip_whitespace (str);
+
+ if (*str == ']')
+ {
+ str ++;
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ /* [Rn],... (post inc) */
+ if (ldst_extend (&str) == FAIL)
+ return;
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ }
+ else
+ {
+ /* [Rn] */
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+
+ inst.instruction |= INDEX_UP;
+ pre_inc = 1;
+ }
+ }
+ else
+ {
+ /* [Rn,...] */
+ if (skip_past_comma (&str) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return;
+ }
+
+ pre_inc = 1;
+ if (ldst_extend (&str) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+ }
+ }
+ else if (*str == '=')
+ {
+ if ((inst.instruction & LOAD_BIT) == 0)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
+ /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
+ str++;
+
+ skip_whitespace (str);
+
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ if (inst.reloc.exp.X_op != O_constant
+ && inst.reloc.exp.X_op != O_symbol)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ value = validate_immediate (inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mov instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= (INST_IMMEDIATE
+ | (OPCODE_MOV << DATA_OP_SHIFT));
+ inst.instruction |= value & 0xfff;
+ end_of_line (str);
+ return;
+ }
+
+ value = validate_immediate (~inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mvn instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= (INST_IMMEDIATE
+ | (OPCODE_MVN << DATA_OP_SHIFT));
+ inst.instruction |= value & 0xfff;
+ end_of_line (str);
+ return;
+ }
+ }
+
+ /* Insert into literal pool. */
+ if (add_to_lit_pool () == FAIL)
+ {
+ if (!inst.error)
+ inst.error = _("literal pool insertion failed");
+ return;
+ }
+
+ /* Change the instruction exp to point to the pool. */
+ inst.reloc.type = BFD_RELOC_ARM_LITERAL;
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+ else
+ {
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+#ifndef TE_WINCE
+ /* PC rel adjust. */
+ inst.reloc.exp.X_add_number -= 8;
+#endif
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+
+ inst.instruction |= (pre_inc ? PRE_INDEX : 0);
+ end_of_line (str);
+ return;
+}
+
+static void
+do_ldstt (str)
+ char * str;
+{
+ int conflict_reg;
+
+ skip_whitespace (str);
+
+ if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (& str) == FAIL)
+ {
+ inst.error = _("address expected");
+ return;
+ }
+
+ if (*str == '[')
+ {
+ int reg;
+
+ str++;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ /* ldrt/strt always use post-indexed addressing, so if the base is
+ the same as Rd, we warn. */
+ if (conflict_reg == reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+
+ skip_whitespace (str);
+
+ if (*str == ']')
+ {
+ str ++;
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ /* [Rn],... (post inc) */
+ if (ldst_extend (&str) == FAIL)
+ return;
+ }
+ else
+ {
+ /* [Rn] */
+ skip_whitespace (str);
+
+ /* Skip a write-back '!'. */
+ if (*str == '!')
+ str++;
+
+ inst.instruction |= INDEX_UP;
+ }
+ }
+ else
+ {
+ inst.error = _("post-indexed expression expected");
+ return;
+ }
+ }
+ else
+ {
+ inst.error = _("post-indexed expression expected");
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static int
+ldst_extend_v4 (str)
+ char ** str;
+{
+ int add = INDEX_UP;
+
+ switch (**str)
+ {
+ case '#':
+ case '$':
+ (*str)++;
+ if (my_get_expression (& inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ int value = inst.reloc.exp.X_add_number;
+
+ if (value < -255 || value > 255)
+ {
+ inst.error = _("address offset too large");
+ return FAIL;
+ }
+
+ if (value < 0)
+ {
+ value = -value;
+ add = 0;
+ }
+
+ /* Halfword and signextension instructions have the
+ immediate value split across bits 11..8 and bits 3..0. */
+ inst.instruction |= (add | HWOFFSET_IMM
+ | ((value >> 4) << 8) | (value & 0xF));
+ }
+ else
+ {
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+ inst.reloc.pc_rel = 0;
+ }
+ return SUCCESS;
+
+ case '-':
+ add = 0;
+ /* Fall through. */
+
+ case '+':
+ (*str)++;
+ /* Fall through. */
+
+ default:
+ if (reg_required_here (str, 0) == FAIL)
+ return FAIL;
+
+ inst.instruction |= add;
+ return SUCCESS;
+ }
+}
+
+/* Halfword and signed-byte load/store operations. */
+static void
+do_ldstv4 (str)
+ char * str;
+{
+ int pre_inc = 0;
+ int conflict_reg;
+ int value;
+
+ skip_whitespace (str);
+
+ if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (& str) == FAIL)
+ {
+ inst.error = _("address expected");
+ return;
+ }
+
+ if (*str == '[')
+ {
+ int reg;
+
+ str++;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ /* Conflicts can occur on stores as well as loads. */
+ conflict_reg = (conflict_reg == reg);
+
+ skip_whitespace (str);
+
+ if (*str == ']')
+ {
+ str ++;
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ /* [Rn],... (post inc) */
+ if (ldst_extend_v4 (&str) == FAIL)
+ return;
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ }
+ else
+ {
+ /* [Rn] */
+ inst.instruction |= HWOFFSET_IMM;
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+
+ inst.instruction |= INDEX_UP;
+ pre_inc = 1;
+ }
+ }
+ else
+ {
+ /* [Rn,...] */
+ if (skip_past_comma (&str) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return;
+ }
+
+ pre_inc = 1;
+ if (ldst_extend_v4 (&str) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+ }
+ }
+ else if (*str == '=')
+ {
+ if ((inst.instruction & LOAD_BIT) == 0)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
+ /* XXX Does this work correctly for half-word/byte ops? */
+ /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
+ str++;
+
+ skip_whitespace (str);
+
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ if (inst.reloc.exp.X_op != O_constant
+ && inst.reloc.exp.X_op != O_symbol)
+ {
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ value = validate_immediate (inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mov instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
+ inst.instruction |= value & 0xfff;
+ end_of_line (str);
+ return;
+ }
+
+ value = validate_immediate (~ inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mvn instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
+ inst.instruction |= value & 0xfff;
+ end_of_line (str);
+ return;
+ }
+ }
+
+ /* Insert into literal pool. */
+ if (add_to_lit_pool () == FAIL)
+ {
+ if (!inst.error)
+ inst.error = _("literal pool insertion failed");
+ return;
+ }
+
+ /* Change the instruction exp to point to the pool. */
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+ else
+ {
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+#ifndef TE_WINCE
+ /* PC rel adjust. */
+ inst.reloc.exp.X_add_number -= 8;
+#endif
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+
+ inst.instruction |= (pre_inc ? PRE_INDEX : 0);
+ end_of_line (str);
+ return;
+}
+
+static long
+reg_list (strp)
+ char ** strp;
+{
+ char * str = * strp;
+ long range = 0;
+ int another_range;
+
+ /* We come back here if we get ranges concatenated by '+' or '|'. */
+ do
+ {
+ another_range = 0;
+
+ if (*str == '{')
+ {
+ int in_range = 0;
+ int cur_reg = -1;
+
+ str++;
+ do
+ {
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (& str, -1)) == FAIL)
+ return FAIL;
+
+ if (in_range)
+ {
+ int i;
+
+ if (reg <= cur_reg)
+ {
+ inst.error = _("bad range in register list");
+ return FAIL;
+ }
+
+ for (i = cur_reg + 1; i < reg; i++)
+ {
+ if (range & (1 << i))
+ as_tsktsk
+ (_("Warning: duplicated register (r%d) in register list"),
+ i);
+ else
+ range |= 1 << i;
+ }
+ in_range = 0;
+ }
+
+ if (range & (1 << reg))
+ as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
+ reg);
+ else if (reg <= cur_reg)
+ as_tsktsk (_("Warning: register range not in ascending order"));
+
+ range |= 1 << reg;
+ cur_reg = reg;
+ }
+ while (skip_past_comma (&str) != FAIL
+ || (in_range = 1, *str++ == '-'));
+ str--;
+ skip_whitespace (str);
+
+ if (*str++ != '}')
+ {
+ inst.error = _("missing `}'");
+ return FAIL;
+ }
+ }
+ else
+ {
+ expressionS expr;
+
+ if (my_get_expression (&expr, &str))
+ return FAIL;
+
+ if (expr.X_op == O_constant)
+ {
+ if (expr.X_add_number
+ != (expr.X_add_number & 0x0000ffff))
+ {
+ inst.error = _("invalid register mask");
+ return FAIL;
+ }
+
+ if ((range & expr.X_add_number) != 0)
+ {
+ int regno = range & expr.X_add_number;
+
+ regno &= -regno;
+ regno = (1 << regno) - 1;
+ as_tsktsk
+ (_("Warning: duplicated register (r%d) in register list"),
+ regno);
+ }
+
+ range |= expr.X_add_number;
+ }
+ else
+ {
+ if (inst.reloc.type != 0)
+ {
+ inst.error = _("expression too complex");
+ return FAIL;
+ }
+
+ memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
+ inst.reloc.type = BFD_RELOC_ARM_MULTI;
+ inst.reloc.pc_rel = 0;
+ }
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '|' || *str == '+')
+ {
+ str++;
+ another_range = 1;
+ }
+ }
+ while (another_range);
+
+ *strp = str;
+ return range;
+}
+
+static void
+do_ldmstm (str)
+ char * str;
+{
+ int base_reg;
+ long range;
+
+ skip_whitespace (str);
+
+ if ((base_reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ if (base_reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed as base register");
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ inst.instruction |= WRITE_BACK;
+ str++;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || (range = reg_list (&str)) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (*str == '^')
+ {
+ str++;
+ inst.instruction |= LDM_TYPE_2_OR_3;
+ }
+
+ if (inst.instruction & WRITE_BACK)
+ {
+ /* Check for unpredictable uses of writeback. */
+ if (inst.instruction & LOAD_BIT)
+ {
+ /* Not allowed in LDM type 2. */
+ if ((inst.instruction & LDM_TYPE_2_OR_3)
+ && ((range & (1 << REG_PC)) == 0))
+ as_warn (_("writeback of base register is UNPREDICTABLE"));
+ /* Only allowed if base reg not in list for other types. */
+ else if (range & (1 << base_reg))
+ as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
+ }
+ else /* STM. */
+ {
+ /* Not allowed for type 2. */
+ if (inst.instruction & LDM_TYPE_2_OR_3)
+ as_warn (_("writeback of base register is UNPREDICTABLE"));
+ /* Only allowed if base reg not in list, or first in list. */
+ else if ((range & (1 << base_reg))
+ && (range & ((1 << base_reg) - 1)))
+ as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
+ }
+ }
+
+ inst.instruction |= range;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_swi (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (*str))
+ str++;
+
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return;
+
+ inst.reloc.type = BFD_RELOC_ARM_SWI;
+ inst.reloc.pc_rel = 0;
+ end_of_line (str);
+
+ return;
+}
+
+static void
+do_swap (str)
+ char * str;
+{
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 12)) == FAIL)
+ return;
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed in swap");
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || (reg = reg_required_here (&str, 0)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed in swap");
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || *str++ != '[')
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ if (reg == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_branch (str)
+ char * str;
+{
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+#ifdef OBJ_ELF
+ {
+ char * save_in;
+
+ /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
+ required for the instruction. */
+
+ /* arm_parse_reloc () works on input_line_pointer.
+ We actually want to parse the operands to the branch instruction
+ passed in 'str'. Save the input pointer and restore it later. */
+ save_in = input_line_pointer;
+ input_line_pointer = str;
+ if (inst.reloc.exp.X_op == O_symbol
+ && *str == '('
+ && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ inst.reloc.pc_rel = 0;
+ /* Modify str to point to after parsed operands, otherwise
+ end_of_line() will complain about the (PLT) left in str. */
+ str = input_line_pointer;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
+ inst.reloc.pc_rel = 1;
+ }
+ input_line_pointer = save_in;
+ }
+#else
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
+ inst.reloc.pc_rel = 1;
+#endif /* OBJ_ELF */
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_bx (str)
+ char * str;
+{
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 0)) == FAIL)
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
+ if (reg == REG_PC)
+ as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
+
+ end_of_line (str);
+}
+
+static void
+do_cdp (str)
+ char * str;
+{
+ /* Co-processor data operation.
+ Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_opc_expr (&str, 20,4) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 0) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ if (cp_opc_expr (&str, 5, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_lstc (str)
+ char * str;
+{
+ /* Co-processor register load/store.
+ Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
+
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_address_required_here (&str, CP_WB_OK) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_co_reg (str)
+ char * str;
+{
+ /* Co-processor register transfer.
+ Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
+
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_opc_expr (&str, 21, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 0) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ if (cp_opc_expr (&str, 5, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fpa_ctrl (str)
+ char * str;
+{
+ /* FP control registers.
+ Format: <WFS|RFS|WFC|RFC>{cond} Rn */
+
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fpa_ldst (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_address_required_here (&str, CP_WB_OK) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+}
+
+static void
+do_fpa_ldmstm (str)
+ char * str;
+{
+ int num_regs;
+
+ skip_whitespace (str);
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ /* Get Number of registers to transfer. */
+ if (skip_past_comma (&str) == FAIL
+ || my_get_expression (&inst.reloc.exp, &str))
+ {
+ if (! inst.error)
+ inst.error = _("constant expression expected");
+ return;
+ }
+
+ if (inst.reloc.exp.X_op != O_constant)
+ {
+ inst.error = _("constant value required for number of registers");
+ return;
+ }
+
+ num_regs = inst.reloc.exp.X_add_number;
+
+ if (num_regs < 1 || num_regs > 4)
+ {
+ inst.error = _("number of registers must be in the range [1:4]");
+ return;
+ }
+
+ switch (num_regs)
+ {
+ case 1:
+ inst.instruction |= CP_T_X;
+ break;
+ case 2:
+ inst.instruction |= CP_T_Y;
+ break;
+ case 3:
+ inst.instruction |= CP_T_Y | CP_T_X;
+ break;
+ case 4:
+ break;
+ default:
+ abort ();
+ }
+
+ if (inst.instruction & (CP_T_Pre | CP_T_UD)) /* ea/fd format. */
+ {
+ int reg;
+ int write_back;
+ int offset;
+
+ /* The instruction specified "ea" or "fd", so we can only accept
+ [Rn]{!}. The instruction does not really support stacking or
+ unstacking, so we have to emulate these by setting appropriate
+ bits and offsets. */
+ if (skip_past_comma (&str) == FAIL
+ || *str != '[')
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ str++;
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str != ']')
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ str++;
+ if (*str == '!')
+ {
+ write_back = 1;
+ str++;
+ if (reg == REG_PC)
+ {
+ inst.error =
+ _("r15 not allowed as base register with write-back");
+ return;
+ }
+ }
+ else
+ write_back = 0;
+
+ if (inst.instruction & CP_T_Pre)
+ {
+ /* Pre-decrement. */
+ offset = 3 * num_regs;
+ if (write_back)
+ inst.instruction |= CP_T_WB;
+ }
else
{
- expressionS expr;
-
- if (my_get_expression (&expr, &str))
- return FAIL;
-
- if (expr.X_op == O_constant)
+ /* Post-increment. */
+ if (write_back)
{
- if (expr.X_add_number
- != (expr.X_add_number & 0x0000ffff))
- {
- inst.error = _("invalid register mask");
- return FAIL;
- }
-
- if ((range & expr.X_add_number) != 0)
- {
- int regno = range & expr.X_add_number;
-
- regno &= -regno;
- regno = (1 << regno) - 1;
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- regno);
- }
-
- range |= expr.X_add_number;
+ inst.instruction |= CP_T_WB;
+ offset = 3 * num_regs;
}
else
{
- if (inst.reloc.type != 0)
- {
- inst.error = _("expression too complex");
- return FAIL;
- }
-
- memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
- inst.reloc.type = BFD_RELOC_ARM_MULTI;
- inst.reloc.pc_rel = 0;
+ /* No write-back, so convert this into a standard pre-increment
+ instruction -- aesthetically more pleasing. */
+ inst.instruction |= CP_T_Pre | CP_T_UD;
+ offset = 0;
}
}
- skip_whitespace (str);
-
- if (*str == '|' || *str == '+')
- {
- str++;
- another_range = 1;
- }
+ inst.instruction |= offset;
+ }
+ else if (skip_past_comma (&str) == FAIL
+ || cp_address_required_here (&str, CP_WB_OK) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
- while (another_range);
- *strp = str;
- return range;
+ end_of_line (str);
}
static void
-do_ldmstm (str)
+do_fpa_dyadic (str)
char * str;
{
- int base_reg;
- long range;
-
skip_whitespace (str);
- if ((base_reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- if (base_reg == REG_PC)
+ if (fp_reg_required_here (&str, 12) == FAIL)
{
- inst.error = _("r15 not allowed as base register");
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
- skip_whitespace (str);
-
- if (*str == '!')
- {
- inst.instruction |= WRITE_BACK;
- str++;
- }
-
if (skip_past_comma (&str) == FAIL
- || (range = reg_list (&str)) == FAIL)
+ || fp_reg_required_here (&str, 16) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (*str == '^')
+ if (skip_past_comma (&str) == FAIL
+ || fp_op2 (&str) == FAIL)
{
- str++;
- inst.instruction |= LDM_TYPE_2_OR_3;
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
- inst.instruction |= range;
end_of_line (str);
return;
}
static void
-do_swi (str)
+do_fpa_monadic (str)
char * str;
{
skip_whitespace (str);
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (*str))
- str++;
+ if (fp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
+ if (skip_past_comma (&str) == FAIL
+ || fp_op2 (&str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- inst.reloc.type = BFD_RELOC_ARM_SWI;
- inst.reloc.pc_rel = 0;
end_of_line (str);
-
return;
}
static void
-do_swap (str)
+do_fpa_cmp (str)
char * str;
{
- int reg;
-
skip_whitespace (str);
- if ((reg = reg_required_here (&str, 12)) == FAIL)
- return;
-
- if (reg == REG_PC)
+ if (fp_reg_required_here (&str, 16) == FAIL)
{
- inst.error = _("r15 not allowed in swap");
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || (reg = reg_required_here (&str, 0)) == FAIL)
+ || fp_op2 (&str) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (reg == REG_PC)
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fpa_from_reg (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ if (fp_reg_required_here (&str, 16) == FAIL)
{
- inst.error = _("r15 not allowed in swap");
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || *str++ != '[')
+ || reg_required_here (&str, 12) == FAIL)
{
- inst.error = BAD_ARGS;
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fpa_to_reg (str)
+ char * str;
+{
skip_whitespace (str);
- if ((reg = reg_required_here (&str, 16)) == FAIL)
+ if (reg_required_here (&str, 12) == FAIL)
return;
- if (reg == REG_PC)
+ if (skip_past_comma (&str) == FAIL
+ || fp_reg_required_here (&str, 0) == FAIL)
{
- inst.error = BAD_PC;
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
- skip_whitespace (str);
+ end_of_line (str);
+ return;
+}
- if (*str++ != ']')
+static int
+vfp_sp_reg_required_here (str, pos)
+ char **str;
+ enum vfp_sp_reg_pos pos;
+{
+ int reg;
+ char *start = *str;
+
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_SN].htab)) != FAIL)
{
- inst.error = _("missing ]");
- return;
+ switch (pos)
+ {
+ case VFP_REG_Sd:
+ inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
+ break;
+
+ case VFP_REG_Sn:
+ inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
+ break;
+
+ case VFP_REG_Sm:
+ inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
+ break;
+
+ default:
+ abort ();
+ }
+ return reg;
}
- end_of_line (str);
- return;
+ /* In the few cases where we might be able to accept something else
+ this error can be overridden. */
+ inst.error = _(all_reg_maps[REG_TYPE_SN].expected);
+
+ /* Restore the start point. */
+ *str = start;
+ return FAIL;
}
-static void
-do_branch (str)
- char * str;
+static int
+vfp_dp_reg_required_here (str, pos)
+ char **str;
+ enum vfp_dp_reg_pos pos;
{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ int reg;
+ char *start = *str;
-#ifdef OBJ_ELF
- {
- char * save_in;
+ if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_DN].htab)) != FAIL)
+ {
+ switch (pos)
+ {
+ case VFP_REG_Dd:
+ inst.instruction |= reg << 12;
+ break;
- /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
- required for the instruction. */
+ case VFP_REG_Dn:
+ inst.instruction |= reg << 16;
+ break;
- /* arm_parse_reloc () works on input_line_pointer.
- We actually want to parse the operands to the branch instruction
- passed in 'str'. Save the input pointer and restore it later. */
- save_in = input_line_pointer;
- input_line_pointer = str;
- if (inst.reloc.exp.X_op == O_symbol
- && *str == '('
- && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
- {
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
- inst.reloc.pc_rel = 0;
- /* Modify str to point to after parsed operands, otherwise
- end_of_line() will complain about the (PLT) left in str. */
- str = input_line_pointer;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
- inst.reloc.pc_rel = 1;
- }
- input_line_pointer = save_in;
- }
-#else
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
- inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF */
+ case VFP_REG_Dm:
+ inst.instruction |= reg << 0;
+ break;
+
+ default:
+ abort ();
+ }
+ return reg;
+ }
+
+ /* In the few cases where we might be able to accept something else
+ this error can be overridden. */
+ inst.error = _(all_reg_maps[REG_TYPE_DN].expected);
- end_of_line (str);
- return;
+ /* Restore the start point. */
+ *str = start;
+ return FAIL;
}
static void
-do_bx (str)
- char * str;
+do_vfp_sp_monadic (str)
+ char *str;
{
- int reg;
-
skip_whitespace (str);
- if ((reg = reg_required_here (&str, 0)) == FAIL)
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL
+ || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
{
- inst.error = BAD_ARGS;
+ if (! inst.error)
+ inst.error = BAD_ARGS;
return;
}
- /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
- if (reg == REG_PC)
- as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
-
end_of_line (str);
+ return;
}
static void
-do_cdp (str)
- char * str;
+do_vfp_dp_monadic (str)
+ char *str;
{
- /* Co-processor data operation.
- Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_sp_dyadic (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 20,4) == FAIL)
+ || vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_dp_dyadic (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_reg_from_sp (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
+ || vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_sp_reg2 (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
+ || reg_required_here (&str, 16) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == SUCCESS)
+ /* We require exactly two consecutive SP registers. */
+ if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
{
- if (cp_opc_expr (&str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ if (! inst.error)
+ inst.error = _("only two consecutive VFP SP registers allowed here");
}
end_of_line (str);
}
static void
-do_lstc (str)
- char * str;
+do_vfp_sp_from_reg (str)
+ char *str;
{
- /* Co-processor register load/store.
- Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
-
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL)
+ return;
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
+ || reg_required_here (&str, 12) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_reg_from_dp (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
}
static void
-do_co_reg (str)
- char * str;
+do_vfp_reg2_from_dp (str)
+ char *str;
{
- /* Co-processor register transfer.
- Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
-
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ if (reg_required_here (&str, 12) == FAIL)
+ return;
if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 21, 3) == FAIL)
+ || reg_required_here (&str, 16) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_dp_from_reg (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
|| reg_required_here (&str, 12) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ end_of_line (str);
+ return;
+}
+
+static void
+do_vfp_dp_from_reg2 (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
+ return;
+
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
+ || reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16))
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
+ end_of_line (str);
+ return;
+}
+
+static const struct vfp_reg *
+vfp_psr_parse (str)
+ char **str;
+{
+ char *start = *str;
+ char c;
+ char *p;
+ const struct vfp_reg *vreg;
+
+ p = start;
+
+ /* Find the end of the current token. */
+ do
{
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
+ c = *p++;
}
+ while (ISALPHA (c));
- if (skip_past_comma (&str) == SUCCESS)
+ /* Mark it. */
+ *--p = 0;
+
+ for (vreg = vfp_regs + 0;
+ vreg < vfp_regs + sizeof (vfp_regs) / sizeof (struct vfp_reg);
+ vreg++)
{
- if (cp_opc_expr (&str, 5, 3) == FAIL)
+ if (strcmp (start, vreg->name) == 0)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
+ *p = c;
+ *str = p;
+ return vreg;
}
}
+ *p = c;
+ return NULL;
+}
+
+static int
+vfp_psr_required_here (str)
+ char **str;
+{
+ char *start = *str;
+ const struct vfp_reg *vreg;
+
+ vreg = vfp_psr_parse (str);
+
+ if (vreg)
+ {
+ inst.instruction |= vreg->regno;
+ return SUCCESS;
+ }
+
+ inst.error = _("VFP system register expected");
+
+ *str = start;
+ return FAIL;
+}
+
+static void
+do_vfp_reg_from_ctrl (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL
+ || vfp_psr_required_here (&str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
end_of_line (str);
return;
}
static void
-do_fpa_ctrl (str)
- char * str;
+do_vfp_ctrl_from_reg (str)
+ char *str;
{
- /* FP control registers.
- Format: <WFS|RFS|WFC|RFC>{cond} Rn */
-
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL)
+ if (vfp_psr_required_here (&str) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
}
static void
-do_fpa_ldst (str)
- char * str;
+do_vfp_sp_ldst (str)
+ char *str;
{
skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
}
if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
+ || cp_address_required_here (&str, CP_NO_WB) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
}
end_of_line (str);
+ return;
}
static void
-do_fpa_ldmstm (str)
- char * str;
+do_vfp_dp_ldst (str)
+ char *str;
{
- int num_regs;
-
skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- /* Get Number of registers to transfer. */
if (skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
+ || cp_address_required_here (&str, CP_NO_WB) == FAIL)
{
- if (! inst.error)
- inst.error = _("constant expression expected");
+ if (!inst.error)
+ inst.error = BAD_ARGS;
return;
}
- if (inst.reloc.exp.X_op != O_constant)
- {
- inst.error = _("Constant value required for number of registers");
- return;
- }
+ end_of_line (str);
+ return;
+}
- num_regs = inst.reloc.exp.X_add_number;
+/* Parse and encode a VFP SP register list, storing the initial
+ register in position POS and returning the range as the result. If
+ the string is invalid return FAIL (an invalid range). */
+static long
+vfp_sp_reg_list (str, pos)
+ char **str;
+ enum vfp_sp_reg_pos pos;
+{
+ long range = 0;
+ int base_reg = 0;
+ int new_base;
+ long base_bits = 0;
+ int count = 0;
+ long tempinst;
+ unsigned long mask = 0;
+ int warned = 0;
+
+ if (**str != '{')
+ return FAIL;
- if (num_regs < 1 || num_regs > 4)
+ (*str)++;
+ skip_whitespace (*str);
+
+ tempinst = inst.instruction;
+
+ do
{
- inst.error = _("number of registers must be in the range [1:4]");
- return;
+ inst.instruction = 0;
+
+ if ((new_base = vfp_sp_reg_required_here (str, pos)) == FAIL)
+ return FAIL;
+
+ if (count == 0 || base_reg > new_base)
+ {
+ base_reg = new_base;
+ base_bits = inst.instruction;
+ }
+
+ if (mask & (1 << new_base))
+ {
+ inst.error = _("invalid register list");
+ return FAIL;
+ }
+
+ if ((mask >> new_base) != 0 && ! warned)
+ {
+ as_tsktsk (_("register list not in ascending order"));
+ warned = 1;
+ }
+
+ mask |= 1 << new_base;
+ count++;
+
+ skip_whitespace (*str);
+
+ if (**str == '-') /* We have the start of a range expression */
+ {
+ int high_range;
+
+ (*str)++;
+
+ if ((high_range
+ = arm_reg_parse (str, all_reg_maps[REG_TYPE_SN].htab))
+ == FAIL)
+ {
+ inst.error = _(all_reg_maps[REG_TYPE_SN].expected);
+ return FAIL;
+ }
+
+ if (high_range <= new_base)
+ {
+ inst.error = _("register range not in ascending order");
+ return FAIL;
+ }
+
+ for (new_base++; new_base <= high_range; new_base++)
+ {
+ if (mask & (1 << new_base))
+ {
+ inst.error = _("invalid register list");
+ return FAIL;
+ }
+
+ mask |= 1 << new_base;
+ count++;
+ }
+ }
}
+ while (skip_past_comma (str) != FAIL);
- switch (num_regs)
+ if (**str != '}')
{
- case 1:
- inst.instruction |= CP_T_X;
- break;
- case 2:
- inst.instruction |= CP_T_Y;
- break;
- case 3:
- inst.instruction |= CP_T_Y | CP_T_X;
- break;
- case 4:
- break;
- default:
- abort ();
+ inst.error = _("invalid register list");
+ return FAIL;
}
- if (inst.instruction & (CP_T_Pre | CP_T_UD)) /* ed/fd format. */
- {
- int reg;
- int write_back;
- int offset;
+ (*str)++;
- /* The instruction specified "ea" or "fd", so we can only accept
- [Rn]{!}. The instruction does not really support stacking or
- unstacking, so we have to emulate these by setting appropriate
- bits and offsets. */
- if (skip_past_comma (&str) == FAIL
- || *str != '[')
+ range = count;
+
+ /* Sanity check -- should have raised a parse error above. */
+ if (count == 0 || count > 32)
+ abort ();
+
+ /* Final test -- the registers must be consecutive. */
+ while (count--)
+ {
+ if ((mask & (1 << base_reg++)) == 0)
{
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ inst.error = _("non-contiguous register range");
+ return FAIL;
}
+ }
- str++;
- skip_whitespace (str);
+ inst.instruction = tempinst | base_bits;
+ return range;
+}
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
+static long
+vfp_dp_reg_list (str)
+ char **str;
+{
+ long range = 0;
+ int base_reg = 0;
+ int new_base;
+ int count = 0;
+ long tempinst;
+ unsigned long mask = 0;
+ int warned = 0;
+
+ if (**str != '{')
+ return FAIL;
- skip_whitespace (str);
+ (*str)++;
+ skip_whitespace (*str);
- if (*str != ']')
+ tempinst = inst.instruction;
+
+ do
+ {
+ inst.instruction = 0;
+
+ if ((new_base = vfp_dp_reg_required_here (str, VFP_REG_Dd)) == FAIL)
+ return FAIL;
+
+ if (count == 0 || base_reg > new_base)
{
- inst.error = BAD_ARGS;
- return;
+ base_reg = new_base;
+ range = inst.instruction;
}
- str++;
- if (*str == '!')
+ if (mask & (1 << new_base))
{
- write_back = 1;
- str++;
- if (reg == REG_PC)
- {
- inst.error =
- _("R15 not allowed as base register with write-back");
- return;
- }
+ inst.error = _("invalid register list");
+ return FAIL;
}
- else
- write_back = 0;
- if (inst.instruction & CP_T_Pre)
+ if ((mask >> new_base) != 0 && ! warned)
{
- /* Pre-decrement. */
- offset = 3 * num_regs;
- if (write_back)
- inst.instruction |= CP_T_WB;
+ as_tsktsk (_("register list not in ascending order"));
+ warned = 1;
}
- else
+
+ mask |= 1 << new_base;
+ count++;
+
+ skip_whitespace (*str);
+
+ if (**str == '-') /* We have the start of a range expression */
{
- /* Post-increment. */
- if (write_back)
+ int high_range;
+
+ (*str)++;
+
+ if ((high_range
+ = arm_reg_parse (str, all_reg_maps[REG_TYPE_DN].htab))
+ == FAIL)
{
- inst.instruction |= CP_T_WB;
- offset = 3 * num_regs;
+ inst.error = _(all_reg_maps[REG_TYPE_DN].expected);
+ return FAIL;
}
- else
+
+ if (high_range <= new_base)
{
- /* No write-back, so convert this into a standard pre-increment
- instruction -- aesthetically more pleasing. */
- inst.instruction |= CP_T_Pre | CP_T_UD;
- offset = 0;
+ inst.error = _("register range not in ascending order");
+ return FAIL;
+ }
+
+ for (new_base++; new_base <= high_range; new_base++)
+ {
+ if (mask & (1 << new_base))
+ {
+ inst.error = _("invalid register list");
+ return FAIL;
+ }
+
+ mask |= 1 << new_base;
+ count++;
}
}
+ }
+ while (skip_past_comma (str) != FAIL);
- inst.instruction |= offset;
+ if (**str != '}')
+ {
+ inst.error = _("invalid register list");
+ return FAIL;
}
- else if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
+
+ (*str)++;
+
+ range |= 2 * count;
+
+ /* Sanity check -- should have raised a parse error above. */
+ if (count == 0 || count > 16)
+ abort ();
+
+ /* Final test -- the registers must be consecutive. */
+ while (count--)
{
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ if ((mask & (1 << base_reg++)) == 0)
+ {
+ inst.error = _("non-contiguous register range");
+ return FAIL;
+ }
}
- end_of_line (str);
+ inst.instruction = tempinst;
+ return range;
}
static void
-do_fpa_dyadic (str)
- char * str;
+vfp_sp_ldstm (str, ldstm_type)
+ char *str;
+ enum vfp_ldstm_type ldstm_type;
{
+ long range;
+
skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if (reg_required_here (&str, 16) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str == '!')
{
- if (! inst.error)
- inst.error = BAD_ARGS;
+ inst.instruction |= WRITE_BACK;
+ str++;
+ }
+ else if (ldstm_type != VFP_LDSTMIA)
+ {
+ inst.error = _("this addressing mode requires base-register writeback");
return;
}
if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 16) == FAIL)
+ || (range = vfp_sp_reg_list (&str, VFP_REG_Sd)) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
+ inst.instruction |= range;
+ end_of_line (str);
+}
+
+static void
+vfp_dp_ldstm (str, ldstm_type)
+ char *str;
+ enum vfp_ldstm_type ldstm_type;
+{
+ long range;
+
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 16) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ inst.instruction |= WRITE_BACK;
+ str++;
+ }
+ else if (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX)
+ {
+ inst.error = _("this addressing mode requires base-register writeback");
+ return;
+ }
+
if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
+ || (range = vfp_dp_reg_list (&str)) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
+ if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
+ range += 1;
+
+ inst.instruction |= range;
end_of_line (str);
- return;
}
static void
-do_fpa_monadic (str)
- char * str;
+do_vfp_sp_ldstmia (str)
+ char *str;
+{
+ vfp_sp_ldstm (str, VFP_LDSTMIA);
+}
+
+static void
+do_vfp_sp_ldstmdb (str)
+ char *str;
+{
+ vfp_sp_ldstm (str, VFP_LDSTMDB);
+}
+
+static void
+do_vfp_dp_ldstmia (str)
+ char *str;
+{
+ vfp_dp_ldstm (str, VFP_LDSTMIA);
+}
+
+static void
+do_vfp_dp_ldstmdb (str)
+ char *str;
+{
+ vfp_dp_ldstm (str, VFP_LDSTMDB);
+}
+
+static void
+do_vfp_xp_ldstmia (str)
+ char *str;
+{
+ vfp_dp_ldstm (str, VFP_LDSTMIAX);
+}
+
+static void
+do_vfp_xp_ldstmdb (str)
+ char *str;
+{
+ vfp_dp_ldstm (str, VFP_LDSTMDBX);
+}
+
+static void
+do_vfp_sp_compare_z (str)
+ char *str;
{
skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
}
static void
-do_fpa_cmp (str)
- char * str;
+do_vfp_dp_compare_z (str)
+ char *str;
{
skip_whitespace (str);
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
}
static void
-do_fpa_from_reg (str)
- char * str;
+do_vfp_dp_sp_cvt (str)
+ char *str;
{
skip_whitespace (str);
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
+ return;
if (skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 12) == FAIL)
+ || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
}
static void
-do_fpa_to_reg (str)
- char * str;
+do_vfp_sp_dp_cvt (str)
+ char *str;
{
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL)
+ if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
return;
if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 0) == FAIL)
+ || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
int offset = inst.reloc.exp.X_add_number;
if (subtract)
- offset = -offset;
+ offset = - offset;
if (offset < 0)
{
- offset = -offset;
+ offset = - offset;
subtract = 1;
/* Quick check, in case offset is MIN_INT. */
return;
}
}
- else
+ /* Note - you cannot convert a subtract of 0 into an
+ add of 0 because the carry flag is set differently. */
+ else if (offset > 0)
subtract = 0;
if (Rd == REG_SP)
if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
{
- inst.error = _("Invalid immediate for shift");
+ inst.error = _("invalid immediate for shift");
return;
}
return;
}
- if (is_immediate_prefix (*str))
+ if (move != THUMB_CPY && is_immediate_prefix (*str))
{
str++;
if (my_get_expression (&inst.reloc.exp, &str))
if (Rs != FAIL)
{
- if (Rs < 8 && Rd < 8)
+ if (move != THUMB_CPY && Rs < 8 && Rd < 8)
{
if (move == THUMB_MOVE)
/* A move of two lowregs is encoded as ADD Rd, Rs, #0
{
if (move == THUMB_MOVE)
inst.instruction = T_OPCODE_MOV_HR;
- else
+ else if (move != THUMB_CPY)
inst.instruction = T_OPCODE_CMP_HR;
if (Rd > 7)
}
else if (*str == '=')
{
+ if (load_store != THUMB_LOAD)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
str++;
}
else if (Rb == REG_PC && load_store != THUMB_LOAD)
{
- inst.error = _("R15 based store not allowed");
+ inst.error = _("r15 based store not allowed");
return;
}
else if (Ro != FAIL)
{
- inst.error = _("Invalid base register for register offset");
+ inst.error = _("invalid base register for register offset");
return;
}
if (offset & ~(0x1f << size))
{
- inst.error = _("Invalid offset");
+ inst.error = _("invalid offset");
return;
}
inst.instruction |= (offset >> size) << 6;
end_of_line (str);
}
-/* Given a register and a register type, return 1 if
- the register is of the given type, else return 0. */
+/* A register must be given at this point.
+
+ Shift is the place to put it in inst.instruction.
+
+ Restores input start point on err.
+ Returns the reg#, or FAIL. */
static int
-cirrus_valid_reg (reg, regtype)
- int reg;
- enum cirrus_regtype regtype;
+mav_reg_required_here (str, shift, regtype)
+ char ** str;
+ int shift;
+ enum arm_reg_type regtype;
{
- switch (regtype)
+ int reg;
+ char *start = *str;
+
+ if ((reg = arm_reg_parse (str, all_reg_maps[regtype].htab)) != FAIL)
{
- case CIRRUS_REGTYPE_ANY:
- return 1;
+ if (shift >= 0)
+ inst.instruction |= reg << shift;
- case CIRRUS_REGTYPE_MVF:
- return cirrus_mvf_register (reg);
+ return reg;
+ }
- case CIRRUS_REGTYPE_MVFX:
- return cirrus_mvfx_register (reg);
+ /* Restore the start point. */
+ *str = start;
- case CIRRUS_REGTYPE_MVD:
- return cirrus_mvd_register (reg);
+ /* In the few cases where we might be able to accept something else
+ this error can be overridden. */
+ inst.error = _(all_reg_maps[regtype].expected);
- case CIRRUS_REGTYPE_MVDX:
- return cirrus_mvdx_register (reg);
+ return FAIL;
+}
- case CIRRUS_REGTYPE_MVAX:
- return cirrus_mvax_register (reg);
+/* Cirrus Maverick Instructions. */
- case CIRRUS_REGTYPE_DSPSC:
- return ARM_EXT_MAVERICKsc_register (reg);
- }
+/* Wrapper functions. */
- return 0;
+static void
+do_mav_binops_1a (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVF);
}
-/* A register must be given at this point.
+static void
+do_mav_binops_1b (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVD);
+}
- If the register is a Cirrus register, convert it's reg# appropriately.
+static void
+do_mav_binops_1c (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVDX);
+}
- Shift is the place to put it in inst.instruction.
+static void
+do_mav_binops_1d (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVF);
+}
- regtype is type register type expected, and is:
- CIRRUS_REGTYPE_MVF
- CIRRUS_REGTYPE_MVFX
- CIRRUS_REGTYPE_MVD
- CIRRUS_REGTYPE_MVDX
- CIRRUS_REGTYPE_MVAX
- CIRRUS_REGTYPE_DSPSC
+static void
+do_mav_binops_1e (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVD);
+}
- Restores input start point on err.
- Returns the reg#, or FAIL. */
+static void
+do_mav_binops_1f (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVF);
+}
-static int
-cirrus_reg_required_here (str, shift, regtype)
- char ** str;
- int shift;
- enum cirrus_regtype regtype;
+static void
+do_mav_binops_1g (str)
+ char * str;
{
- static char buff [135]; /* XXX */
- int reg;
- char * start = * str;
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVD);
+}
- if ((reg = arm_reg_parse (str)) != FAIL
- && (int_register (reg)
- || cirrus_register (reg)))
- {
- int orig_reg = reg;
+static void
+do_mav_binops_1h (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVFX);
+}
- /* Calculate actual register # for opcode. */
- if (cirrus_register (reg)
- && !ARM_EXT_MAVERICKsc_register (reg)) /* Leave this one as is. */
- {
- if (reg >= 130)
- reg -= 130;
- else if (reg >= 110)
- reg -= 110;
- else if (reg >= 90)
- reg -= 90;
- else if (reg >= 70)
- reg -= 70;
- else if (reg >= 50)
- reg -= 50;
- }
+static void
+do_mav_binops_1i (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVFX);
+}
- if (!cirrus_valid_reg (orig_reg, regtype))
- {
- sprintf (buff, _("invalid register type at '%.100s'"), start);
- inst.error = buff;
- return FAIL;
- }
+static void
+do_mav_binops_1j (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVDX);
+}
- if (shift >= 0)
- inst.instruction |= reg << shift;
+static void
+do_mav_binops_1k (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVDX);
+}
- return orig_reg;
- }
+static void
+do_mav_binops_1l (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVF);
+}
- /* Restore the start point, we may have got a reg of the wrong class. */
- *str = start;
-
- /* In the few cases where we might be able to accept something else
- this error can be overridden. */
- sprintf (buff, _("Cirrus register expected, not '%.100s'"), start);
- inst.error = buff;
-
- return FAIL;
+static void
+do_mav_binops_1m (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVD);
}
-/* Cirrus Instructions. */
+static void
+do_mav_binops_1n (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVFX);
+}
-/* Wrapper functions. */
+static void
+do_mav_binops_1o (str)
+ char * str;
+{
+ do_mav_binops (str, MAV_MODE1, REG_TYPE_MVDX, REG_TYPE_MVDX);
+}
static void
-do_c_binops_1 (str)
+do_mav_binops_2a (str)
char * str;
{
- do_c_binops (str, CIRRUS_MODE1);
+ do_mav_binops (str, MAV_MODE2, REG_TYPE_MVF, REG_TYPE_RN);
}
static void
-do_c_binops_2 (str)
+do_mav_binops_2b (str)
char * str;
{
- do_c_binops (str, CIRRUS_MODE2);
+ do_mav_binops (str, MAV_MODE2, REG_TYPE_MVD, REG_TYPE_RN);
}
static void
-do_c_binops_3 (str)
+do_mav_binops_2c (str)
char * str;
{
- do_c_binops (str, CIRRUS_MODE3);
+ do_mav_binops (str, MAV_MODE2, REG_TYPE_MVDX, REG_TYPE_RN);
}
static void
-do_c_triple_4 (str)
+do_mav_binops_3a (str)
char * str;
{
- do_c_triple (str, CIRRUS_MODE4);
+ do_mav_binops (str, MAV_MODE3, REG_TYPE_MVAX, REG_TYPE_MVFX);
}
static void
-do_c_triple_5 (str)
+do_mav_binops_3b (str)
char * str;
{
- do_c_triple (str, CIRRUS_MODE5);
+ do_mav_binops (str, MAV_MODE3, REG_TYPE_MVFX, REG_TYPE_MVAX);
}
static void
-do_c_quad_6 (str)
+do_mav_binops_3c (str)
char * str;
{
- do_c_quad (str, CIRRUS_MODE6);
+ do_mav_binops (str, MAV_MODE3, REG_TYPE_MVAX, REG_TYPE_MVDX);
}
static void
-do_c_dspsc_1 (str)
+do_mav_binops_3d (str)
char * str;
{
- do_c_dspsc (str, CIRRUS_MODE1);
+ do_mav_binops (str, MAV_MODE3, REG_TYPE_MVDX, REG_TYPE_MVAX);
}
static void
-do_c_dspsc_2 (str)
+do_mav_triple_4a (str)
char * str;
{
- do_c_dspsc (str, CIRRUS_MODE2);
+ do_mav_triple (str, MAV_MODE4, REG_TYPE_MVFX, REG_TYPE_MVFX, REG_TYPE_RN);
}
static void
-do_c_shift_1 (str)
+do_mav_triple_4b (str)
char * str;
{
- do_c_shift (str, CIRRUS_MODE1);
+ do_mav_triple (str, MAV_MODE4, REG_TYPE_MVDX, REG_TYPE_MVDX, REG_TYPE_RN);
}
static void
-do_c_shift_2 (str)
+do_mav_triple_5a (str)
char * str;
{
- do_c_shift (str, CIRRUS_MODE2);
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVF, REG_TYPE_MVF);
}
static void
-do_c_ldst_1 (str)
+do_mav_triple_5b (str)
char * str;
{
- do_c_ldst (str, CIRRUS_MODE1);
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVD, REG_TYPE_MVD);
}
static void
-do_c_ldst_2 (str)
+do_mav_triple_5c (str)
char * str;
{
- do_c_ldst (str, CIRRUS_MODE2);
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVFX, REG_TYPE_MVFX);
}
static void
-do_c_ldst_3 (str)
+do_mav_triple_5d (str)
char * str;
{
- do_c_ldst (str, CIRRUS_MODE3);
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVDX, REG_TYPE_MVDX);
}
static void
-do_c_ldst_4 (str)
+do_mav_triple_5e (str)
char * str;
{
- do_c_ldst (str, CIRRUS_MODE4);
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_MVF, REG_TYPE_MVF, REG_TYPE_MVF);
}
-/* Isnsn like "foo X,Y". */
+static void
+do_mav_triple_5f (str)
+ char * str;
+{
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_MVD, REG_TYPE_MVD, REG_TYPE_MVD);
+}
static void
-do_c_binops (str, mode)
+do_mav_triple_5g (str)
+ char * str;
+{
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_MVFX, REG_TYPE_MVFX, REG_TYPE_MVFX);
+}
+
+static void
+do_mav_triple_5h (str)
+ char * str;
+{
+ do_mav_triple (str, MAV_MODE5, REG_TYPE_MVDX, REG_TYPE_MVDX, REG_TYPE_MVDX);
+}
+
+static void
+do_mav_quad_6a (str)
char * str;
- int mode;
{
- int shift1, shift2;
+ do_mav_quad (str, MAV_MODE6, REG_TYPE_MVAX, REG_TYPE_MVFX, REG_TYPE_MVFX,
+ REG_TYPE_MVFX);
+}
- shift1 = mode & 0xff;
- shift2 = (mode >> 8) & 0xff;
+static void
+do_mav_quad_6b (str)
+ char * str;
+{
+ do_mav_quad (str, MAV_MODE6, REG_TYPE_MVAX, REG_TYPE_MVAX, REG_TYPE_MVFX,
+ REG_TYPE_MVFX);
+}
+/* cfmvsc32<cond> DSPSC,MVFX[15:0]. */
+static void
+do_mav_dspsc_1 (str)
+ char * str;
+{
skip_whitespace (str);
- if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
+ /* cfmvsc32. */
+ if (mav_reg_required_here (&str, -1, REG_TYPE_DSPSC) == FAIL
|| skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL)
+ || mav_reg_required_here (&str, 16, REG_TYPE_MVFX) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
+
+ return;
}
- else
- end_of_line (str);
+
+ end_of_line (str);
}
-/* Isnsn like "foo X,Y,Z". */
+/* cfmv32sc<cond> MVFX[15:0],DSPSC. */
+static void
+do_mav_dspsc_2 (str)
+ char * str;
+{
+ skip_whitespace (str);
+
+ /* cfmv32sc. */
+ if (mav_reg_required_here (&str, 0, REG_TYPE_MVFX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || mav_reg_required_here (&str, -1, REG_TYPE_DSPSC) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+
+ return;
+ }
+
+ end_of_line (str);
+}
+
+static void
+do_mav_shift_1 (str)
+ char * str;
+{
+ do_mav_shift (str, REG_TYPE_MVFX, REG_TYPE_MVFX);
+}
+
+static void
+do_mav_shift_2 (str)
+ char * str;
+{
+ do_mav_shift (str, REG_TYPE_MVDX, REG_TYPE_MVDX);
+}
+
+static void
+do_mav_ldst_1 (str)
+ char * str;
+{
+ do_mav_ldst (str, REG_TYPE_MVF);
+}
+
+static void
+do_mav_ldst_2 (str)
+ char * str;
+{
+ do_mav_ldst (str, REG_TYPE_MVD);
+}
+
+static void
+do_mav_ldst_3 (str)
+ char * str;
+{
+ do_mav_ldst (str, REG_TYPE_MVFX);
+}
+
+static void
+do_mav_ldst_4 (str)
+ char * str;
+{
+ do_mav_ldst (str, REG_TYPE_MVDX);
+}
+
+/* Isnsn like "foo X,Y". */
static void
-do_c_triple (str, mode)
+do_mav_binops (str, mode, reg0, reg1)
char * str;
int mode;
+ enum arm_reg_type reg0;
+ enum arm_reg_type reg1;
{
- int shift1, shift2, shift3;
+ int shift0, shift1;
- shift1 = mode & 0xff;
- shift2 = (mode >> 8) & 0xff;
- shift3 = (mode >> 16) & 0xff;
+ shift0 = mode & 0xff;
+ shift1 = (mode >> 8) & 0xff;
skip_whitespace (str);
- if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
- || skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL
+ if (mav_reg_required_here (&str, shift0, reg0) == FAIL
|| skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_ANY) == FAIL)
+ || mav_reg_required_here (&str, shift1, reg1) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
end_of_line (str);
}
-/* Isnsn like "foo W,X,Y,Z".
- where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
+/* Isnsn like "foo X,Y,Z". */
static void
-do_c_quad (str, mode)
+do_mav_triple (str, mode, reg0, reg1, reg2)
char * str;
int mode;
+ enum arm_reg_type reg0;
+ enum arm_reg_type reg1;
+ enum arm_reg_type reg2;
{
- int shift1, shift2, shift3, shift4;
- enum cirrus_regtype rt;
-
- rt = (inst.instruction << 4 == 0xe2006000
- || inst.instruction << 4 == 0xe3006000) ? CIRRUS_REGTYPE_MVAX
- : CIRRUS_REGTYPE_MVFX;
+ int shift0, shift1, shift2;
- shift1 = mode & 0xff;
- shift2 = (mode >> 8) & 0xff;
- shift3 = (mode >> 16) & 0xff;
- shift4 = (mode >> 24) & 0xff;
+ shift0 = mode & 0xff;
+ shift1 = (mode >> 8) & 0xff;
+ shift2 = (mode >> 16) & 0xff;
skip_whitespace (str);
- if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_MVAX) == FAIL
+ if (mav_reg_required_here (&str, shift0, reg0) == FAIL
|| skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift2, rt) == FAIL
+ || mav_reg_required_here (&str, shift1, reg1) == FAIL
|| skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_MVFX) == FAIL
- || skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, shift4, CIRRUS_REGTYPE_MVFX) == FAIL)
+ || mav_reg_required_here (&str, shift2, reg2) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
end_of_line (str);
}
-/* cfmvsc32<cond> DSPSC,MVFX[15:0].
- cfmv32sc<cond> MVFX[15:0],DSPSC. */
+/* Isnsn like "foo W,X,Y,Z".
+ where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
static void
-do_c_dspsc (str, mode)
+do_mav_quad (str, mode, reg0, reg1, reg2, reg3)
char * str;
int mode;
+ enum arm_reg_type reg0;
+ enum arm_reg_type reg1;
+ enum arm_reg_type reg2;
+ enum arm_reg_type reg3;
{
- int error;
-
- skip_whitespace (str);
+ int shift0, shift1, shift2, shift3;
- error = 0;
+ shift0= mode & 0xff;
+ shift1 = (mode >> 8) & 0xff;
+ shift2 = (mode >> 16) & 0xff;
+ shift3 = (mode >> 24) & 0xff;
- if (mode == CIRRUS_MODE1)
- {
- /* cfmvsc32. */
- if (cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL
- || skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, 16, CIRRUS_REGTYPE_MVFX) == FAIL)
- error = 1;
- }
- else
- {
- /* cfmv32sc. */
- if (cirrus_reg_required_here (&str, 0, CIRRUS_REGTYPE_MVFX) == FAIL
- || skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL)
- error = 1;
- }
+ skip_whitespace (str);
- if (error)
+ if (mav_reg_required_here (&str, shift0, reg0) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || mav_reg_required_here (&str, shift1, reg1) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || mav_reg_required_here (&str, shift2, reg2) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || mav_reg_required_here (&str, shift3, reg3) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
}
else
- {
- end_of_line (str);
- }
+ end_of_line (str);
}
-/* Cirrus shift immediate instructions.
+/* Maverick shift immediate instructions.
cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
static void
-do_c_shift (str, mode)
+do_mav_shift (str, reg0, reg1)
char * str;
- int mode;
+ enum arm_reg_type reg0;
+ enum arm_reg_type reg1;
{
int error;
int imm, neg = 0;
error = 0;
- if (cirrus_reg_required_here (&str, 12,
- (mode == CIRRUS_MODE1)
- ? CIRRUS_REGTYPE_MVFX
- : CIRRUS_REGTYPE_MVDX) == FAIL
+ if (mav_reg_required_here (&str, 12, reg0) == FAIL
|| skip_past_comma (&str) == FAIL
- || cirrus_reg_required_here (&str, 16,
- (mode == CIRRUS_MODE1)
- ? CIRRUS_REGTYPE_MVFX
- : CIRRUS_REGTYPE_MVDX) == FAIL
+ || mav_reg_required_here (&str, 16, reg1) == FAIL
|| skip_past_comma (&str) == FAIL)
{
if (!inst.error)
}
static int
-cirrus_parse_offset (str, negative)
+mav_parse_offset (str, negative)
char ** str;
int *negative;
{
return *negative ? -offset : offset;
}
-/* Cirrus load/store instructions.
+/* Maverick load/store instructions.
<insn><cond> CRd,[Rn,<offset>]{!}.
<insn><cond> CRd,[Rn],<offset>. */
static void
-do_c_ldst (str, mode)
+do_mav_ldst (str, reg0)
char * str;
- int mode;
+ enum arm_reg_type reg0;
{
int offset, negative;
- enum cirrus_regtype rt;
-
- rt = mode == CIRRUS_MODE1 ? CIRRUS_REGTYPE_MVF
- : mode == CIRRUS_MODE2 ? CIRRUS_REGTYPE_MVD
- : mode == CIRRUS_MODE3 ? CIRRUS_REGTYPE_MVFX
- : mode == CIRRUS_MODE4 ? CIRRUS_REGTYPE_MVDX : CIRRUS_REGTYPE_MVF;
skip_whitespace (str);
- if (cirrus_reg_required_here (& str, 12, rt) == FAIL
- || skip_past_comma (& str) == FAIL
+ if (mav_reg_required_here (&str, 12, reg0) == FAIL
+ || skip_past_comma (&str) == FAIL
|| *str++ != '['
- || reg_required_here (& str, 16) == FAIL)
+ || reg_required_here (&str, 16) == FAIL)
goto fail_ldst;
- if (skip_past_comma (& str) == SUCCESS)
+ if (skip_past_comma (&str) == SUCCESS)
{
/* You are here: "<offset>]{!}". */
inst.instruction |= PRE_INDEX;
- offset = cirrus_parse_offset (&str, &negative);
+ offset = mav_parse_offset (&str, &negative);
if (inst.error)
return;
}
if (skip_past_comma (&str) == FAIL
- || (offset = cirrus_parse_offset (&str, &negative), inst.error))
+ || (offset = mav_parse_offset (&str, &negative), inst.error))
goto fail_ldst;
inst.instruction |= CP_T_WB; /* Post indexed, set bit W. */
if (negative)
offset = -offset;
else
- inst.instruction |= CP_T_UD; /* Postive, so set bit U. */
+ inst.instruction |= CP_T_UD; /* Positive, so set bit U. */
inst.instruction |= offset >> 2;
end_of_line (str);
const char * name = S_GET_NAME (symbolP);
symbolS * new_target;
- /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
+ /* This definition must agree with the one in gcc/config/arm/thumb.c. */
#define STUB_NAME ".real_start_of"
if (name == NULL)
return;
if (*str != '!')
- as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
+ as_warn (_("inserted missing '!': load/store multiple always writes back base register"));
else
str++;
{
/* This really doesn't seem worth it. */
inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
+ inst.error = _("expression too complex");
return;
}
|| *str++ != ']')
{
if (! inst.error)
- inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
+ inst.error = _("syntax: ldrs[b] Rd, [Rb, Ro]");
return;
}
{
/* This really doesn't seem worth it. */
inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
+ inst.error = _("expression too complex");
return;
}
}
static void
-insert_reg (entry)
- int entry;
+insert_reg (r, htab)
+ const struct reg_entry *r;
+ struct hash_control *htab;
{
- int len = strlen (reg_table[entry].name) + 2;
+ int len = strlen (r->name) + 2;
char * buf = (char *) xmalloc (len);
char * buf2 = (char *) xmalloc (len);
int i = 0;
buf[i++] = REGISTER_PREFIX;
#endif
- strcpy (buf + i, reg_table[entry].name);
+ strcpy (buf + i, r->name);
for (i = 0; buf[i]; i++)
buf2[i] = TOUPPER (buf[i]);
buf2[i] = '\0';
- hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
- hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
+ hash_insert (htab, buf, (PTR) r);
+ hash_insert (htab, buf2, (PTR) r);
+}
+
+static void
+build_reg_hsh (map)
+ struct reg_map *map;
+{
+ const struct reg_entry *r;
+
+ if ((map->htab = hash_new ()) == NULL)
+ as_fatal (_("virtual memory exhausted"));
+
+ for (r = map->names; r->name != NULL; r++)
+ insert_reg (r, map->htab);
}
static void
-insert_reg_alias (str, regnum)
+insert_reg_alias (str, regnum, htab)
char *str;
int regnum;
+ struct hash_control *htab;
{
- struct reg_entry *new =
- (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
- char *name = xmalloc (strlen (str) + 1);
- strcpy (name, str);
-
+ const char *error;
+ struct reg_entry *new = xmalloc (sizeof (struct reg_entry));
+ const char *name = xmalloc (strlen (str) + 1);
+
+ strcpy ((char *) name, str);
+
new->name = name;
new->number = regnum;
+ new->builtin = FALSE;
+
+ error = hash_insert (htab, name, (PTR) new);
+ if (error)
+ {
+ as_bad (_("failed to create an alias for %s, reason: %s"),
+ str, error);
+ free ((char *) name);
+ free (new);
+ }
+}
+
+/* Look for the .req directive. This is of the form:
+
+ new_register_name .req existing_register_name
+
+ If we find one, or if it looks sufficiently like one that we want to
+ handle any error here, return non-zero. Otherwise return zero. */
+static int
+create_register_alias (newname, p)
+ char *newname;
+ char *p;
+{
+ char *q;
+ char c;
+
+ q = p;
+ skip_whitespace (q);
+
+ c = *p;
+ *p = '\0';
+
+ if (*q && !strncmp (q, ".req ", 5))
+ {
+ char *copy_of_str;
+ char *r;
+
+#ifdef IGNORE_OPCODE_CASE
+ newname = original_case_string;
+#endif
+ copy_of_str = newname;
+
+ q += 4;
+ skip_whitespace (q);
+
+ for (r = q; *r != '\0'; r++)
+ if (*r == ' ')
+ break;
+
+ if (r != q)
+ {
+ enum arm_reg_type new_type, old_type;
+ int old_regno;
+ char d = *r;
+
+ *r = '\0';
+ old_type = arm_reg_parse_any (q);
+ *r = d;
+
+ new_type = arm_reg_parse_any (newname);
+
+ if (new_type == REG_TYPE_MAX)
+ {
+ if (old_type != REG_TYPE_MAX)
+ {
+ old_regno = arm_reg_parse (&q, all_reg_maps[old_type].htab);
+ insert_reg_alias (newname, old_regno,
+ all_reg_maps[old_type].htab);
+ }
+ else
+ as_warn (_("register '%s' does not exist\n"), q);
+ }
+ else if (old_type == REG_TYPE_MAX)
+ {
+ as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
+ copy_of_str, q);
+ }
+ else
+ {
+ /* Do not warn about redefinitions to the same alias. */
+ if (new_type != old_type
+ || (arm_reg_parse (&q, all_reg_maps[old_type].htab)
+ != arm_reg_parse (&q, all_reg_maps[new_type].htab)))
+ as_warn (_("ignoring redefinition of register alias '%s'"),
+ copy_of_str);
+
+ }
+ }
+ else
+ as_warn (_("ignoring incomplete .req pseuso op"));
- hash_insert (arm_reg_hsh, name, (PTR) new);
+ *p = c;
+ return 1;
+ }
+
+ *p = c;
+ return 0;
}
static void
for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
{
- CONST struct asm_opcode *insn = insns + i;
+ const struct asm_opcode *insn = insns + i;
if (insn->cond_offset != 0)
{
}
}
+#if 0 /* Suppressed - for now. */
+#if defined OBJ_ELF || defined OBJ_COFF
+
+#ifdef OBJ_ELF
+#define arm_Note Elf_External_Note
+#else
+typedef struct
+{
+ unsigned char namesz[4]; /* Size of entry's owner string. */
+ unsigned char descsz[4]; /* Size of the note descriptor. */
+ unsigned char type[4]; /* Interpretation of the descriptor. */
+ char name[1]; /* Start of the name+desc data. */
+} arm_Note;
+#endif
+
+/* The description is kept to a fix sized in order to make updating
+ it and merging it easier. */
+#define ARM_NOTE_DESCRIPTION_LENGTH 8
+
+static void
+arm_add_note (name, description, type)
+ const char * name;
+ const char * description;
+ unsigned int type;
+{
+ arm_Note note ATTRIBUTE_UNUSED;
+ char * p;
+ unsigned int name_len;
+
+ name_len = (strlen (name) + 1 + 3) & ~3;
+
+ p = frag_more (sizeof (note.namesz));
+ md_number_to_chars (p, (valueT) name_len, sizeof (note.namesz));
+
+ p = frag_more (sizeof (note.descsz));
+ md_number_to_chars (p, (valueT) ARM_NOTE_DESCRIPTION_LENGTH, sizeof (note.descsz));
+
+ p = frag_more (sizeof (note.type));
+ md_number_to_chars (p, (valueT) type, sizeof (note.type));
+
+ p = frag_more (name_len);
+ strcpy (p, name);
+
+ p = frag_more (ARM_NOTE_DESCRIPTION_LENGTH);
+ strncpy (p, description, ARM_NOTE_DESCRIPTION_LENGTH);
+ frag_align (2, 0, 0);
+}
+#endif
+#endif
+
void
md_begin ()
{
|| (arm_tops_hsh = hash_new ()) == NULL
|| (arm_cond_hsh = hash_new ()) == NULL
|| (arm_shift_hsh = hash_new ()) == NULL
- || (arm_reg_hsh = hash_new ()) == NULL
|| (arm_psr_hsh = hash_new ()) == NULL)
- as_fatal (_("Virtual memory exhausted"));
+ as_fatal (_("virtual memory exhausted"));
build_arm_ops_hsh ();
for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
- for (i = 0; reg_table[i].name; i++)
- insert_reg (i);
+ for (i = (int) REG_TYPE_FIRST; i < (int) REG_TYPE_MAX; i++)
+ build_reg_hsh (all_reg_maps + i);
set_constant_flonums ();
+ /* Set the cpu variant based on the command-line options. We prefer
+ -mcpu= over -march= if both are set (as for GCC); and we prefer
+ -mfpu= over any other way of setting the floating point unit.
+ Use of legacy options with new options are faulted. */
+ if (legacy_cpu != -1)
+ {
+ if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
+ as_bad (_("use of old and new-style options to set CPU type"));
+
+ mcpu_cpu_opt = legacy_cpu;
+ }
+ else if (mcpu_cpu_opt == -1)
+ mcpu_cpu_opt = march_cpu_opt;
+
+ if (legacy_fpu != -1)
+ {
+ if (mfpu_opt != -1)
+ as_bad (_("use of old and new-style options to set FPU type"));
+
+ mfpu_opt = legacy_fpu;
+ }
+ else if (mfpu_opt == -1)
+ {
+#if !(defined (TE_LINUX) || defined (TE_NetBSD))
+ /* Some environments specify a default FPU. If they don't, infer it
+ from the processor. */
+ if (mcpu_fpu_opt != -1)
+ mfpu_opt = mcpu_fpu_opt;
+ else
+ mfpu_opt = march_fpu_opt;
+#else
+ mfpu_opt = FPU_DEFAULT;
+#endif
+ }
+
+ if (mfpu_opt == -1)
+ {
+ if (mcpu_cpu_opt == -1)
+ mfpu_opt = FPU_DEFAULT;
+ else if (mcpu_cpu_opt & ARM_EXT_V5)
+ mfpu_opt = FPU_ARCH_VFP_V2;
+ else
+ mfpu_opt = FPU_ARCH_FPA;
+ }
+
+ if (mcpu_cpu_opt == -1)
+ mcpu_cpu_opt = CPU_DEFAULT;
+
+ cpu_variant = mcpu_cpu_opt | mfpu_opt;
+
#if defined OBJ_COFF || defined OBJ_ELF
{
unsigned int flags = 0;
if (support_interwork) flags |= F_INTERWORK;
if (uses_apcs_float) flags |= F_APCS_FLOAT;
if (pic_code) flags |= F_PIC;
- if ((cpu_variant & FPU_ANY) == FPU_NONE) flags |= F_SOFT_FLOAT;
+ if ((cpu_variant & FPU_ANY) == FPU_NONE
+ || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
+ flags |= F_SOFT_FLOAT;
+ /* Using VFP conventions (even if soft-float). */
+ if (cpu_variant & FPU_VFP_EXT_NONE) flags |= F_VFP_FLOAT;
+
+#if defined OBJ_ELF
+ if (cpu_variant & ARM_CEXT_MAVERICK)
+ {
+ flags &= ~ F_SOFT_FLOAT;
+ flags |= EF_ARM_MAVERICK_FLOAT;
+ }
+#endif
bfd_set_private_flags (stdoutput, flags);
break;
default:
- mach = bfd_mach_arm_4;
+ mach = bfd_mach_arm_unknown;
break;
-
}
/* Catch special cases. */
- if (cpu_variant & ARM_EXT_XSCALE)
+ if (cpu_variant & ARM_CEXT_IWMMXT)
+ mach = bfd_mach_arm_iWMMXt;
+ else if (cpu_variant & ARM_CEXT_XSCALE)
mach = bfd_mach_arm_XScale;
+ else if (cpu_variant & ARM_CEXT_MAVERICK)
+ mach = bfd_mach_arm_ep9312;
else if (cpu_variant & ARM_EXT_V5E)
mach = bfd_mach_arm_5TE;
else if (cpu_variant & ARM_EXT_V5)
else if (cpu_variant & ARM_EXT_V3M)
mach = bfd_mach_arm_3M;
+#if 0 /* Suppressed - for now. */
+#if defined (OBJ_ELF) || defined (OBJ_COFF)
+
+ /* Create a .note section to fully identify this arm binary. */
+
+#define NOTE_ARCH_STRING "arch: "
+
+#if defined OBJ_COFF && ! defined NT_VERSION
+#define NT_VERSION 1
+#define NT_ARCH 2
+#endif
+
+ {
+ segT current_seg = now_seg;
+ subsegT current_subseg = now_subseg;
+ asection * arm_arch;
+ const char * arch_string;
+
+ arm_arch = bfd_make_section_old_way (stdoutput, ARM_NOTE_SECTION);
+
+#ifdef OBJ_COFF
+ bfd_set_section_flags (stdoutput, arm_arch,
+ SEC_DATA | SEC_ALLOC | SEC_LOAD | SEC_LINK_ONCE \
+ | SEC_HAS_CONTENTS);
+#endif
+ arm_arch->output_section = arm_arch;
+ subseg_set (arm_arch, 0);
+
+ switch (mach)
+ {
+ default:
+ case bfd_mach_arm_unknown: arch_string = "unknown"; break;
+ case bfd_mach_arm_2: arch_string = "armv2"; break;
+ case bfd_mach_arm_2a: arch_string = "armv2a"; break;
+ case bfd_mach_arm_3: arch_string = "armv3"; break;
+ case bfd_mach_arm_3M: arch_string = "armv3M"; break;
+ case bfd_mach_arm_4: arch_string = "armv4"; break;
+ case bfd_mach_arm_4T: arch_string = "armv4t"; break;
+ case bfd_mach_arm_5: arch_string = "armv5"; break;
+ case bfd_mach_arm_5T: arch_string = "armv5t"; break;
+ case bfd_mach_arm_5TE: arch_string = "armv5te"; break;
+ case bfd_mach_arm_XScale: arch_string = "XScale"; break;
+ case bfd_mach_arm_ep9312: arch_string = "ep9312"; break;
+ case bfd_mach_arm_iWMMXt: arch_string = "iWMMXt"; break;
+ }
+
+ arm_add_note (NOTE_ARCH_STRING, arch_string, NT_ARCH);
+
+ subseg_set (current_seg, current_subseg);
+ }
+#endif
+#endif /* Suppressed code. */
+
bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
}
default:
*sizeP = 0;
- return _("Bad call to MD_ATOF()");
+ return _("bad call to MD_ATOF()");
}
t = atof_ieee (input_line_pointer, type, words);
}
else
{
- /* For a 4 byte float the order of elements in `words' is 1 0. For an
- 8 byte float the order is 1 0 3 2. */
- for (i = 0; i < prec; i += 2)
- {
- md_number_to_chars (litP, (valueT) words[i + 1], 2);
- md_number_to_chars (litP + 2, (valueT) words[i], 2);
- litP += 4;
- }
+ if (cpu_variant & FPU_ARCH_VFP)
+ for (i = prec - 1; i >= 0; i--)
+ {
+ md_number_to_chars (litP, (valueT) words[i], 2);
+ litP += 2;
+ }
+ else
+ /* For a 4 byte float the order of elements in `words' is 1 0.
+ For an 8 byte float the order is 1 0 3 2. */
+ for (i = 0; i < prec; i += 2)
+ {
+ md_number_to_chars (litP, (valueT) words[i + 1], 2);
+ md_number_to_chars (litP + 2, (valueT) words[i], 2);
+ litP += 4;
+ }
}
return 0;
}
#ifdef TE_WINCE
- /* The pattern was adjusted to accomodate CE's off-by-one fixups,
- so we un-adjust here to compensate for the accomodation. */
+ /* The pattern was adjusted to accommodate CE's off-by-one fixups,
+ so we un-adjust here to compensate for the accommodation. */
return fixP->fx_where + fixP->fx_frag->fr_address + 8;
#else
return fixP->fx_where + fixP->fx_frag->fr_address;
advance the pointer. */
static int
-arm_reg_parse (ccp)
+arm_reg_parse (ccp, htab)
register char ** ccp;
+ struct hash_control *htab;
{
char * start = * ccp;
char c;
c = *p++;
*--p = 0;
- reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
+ reg = (struct reg_entry *) hash_find (htab, start);
*p = c;
if (reg)
return FAIL;
}
+/* Search for the following register name in each of the possible reg name
+ tables. Return the classification if found, or REG_TYPE_MAX if not
+ present. */
+static enum arm_reg_type
+arm_reg_parse_any (cp)
+ char *cp;
+{
+ int i;
+
+ for (i = (int) REG_TYPE_FIRST; i < (int) REG_TYPE_MAX; i++)
+ if (arm_reg_parse (&cp, all_reg_maps[i].htab) != FAIL)
+ return (enum arm_reg_type) i;
+
+ return REG_TYPE_MAX;
+}
+
void
md_apply_fix3 (fixP, valP, seg)
fixS * fixP;
newimm |= (temp & 0xfffff000);
md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
+ fixP->fx_done = 1;
break;
case BFD_RELOC_ARM_ADRL_IMMEDIATE:
{
unsigned int highpart = 0;
unsigned int newinsn = 0xe1a00000; /* nop. */
+
newimm = validate_immediate (value);
temp = md_chars_to_number (buf, INSN_SIZE);
else
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
- value);
+ _("unable to compute ADRL instructions for PC offset of 0x%lx"),
+ (long) value);
break;
}
{
if (((unsigned long) value) > 0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
+ _("invalid swi expression"));
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
newval |= value;
md_number_to_chars (buf, newval, THUMB_SIZE);
{
if (((unsigned long) value) > 0x00ffffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
+ _("invalid swi expression"));
newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
newval |= value;
md_number_to_chars (buf, newval, INSN_SIZE);
case BFD_RELOC_ARM_MULTI:
if (((unsigned long) value) > 0xffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid expression in load/store multiple"));
+ _("invalid expression in load/store multiple"));
newval = value | md_chars_to_number (buf, INSN_SIZE);
md_number_to_chars (buf, newval, INSN_SIZE);
break;
the absolute address that is the destination of the branch in the
24 bits of the branch instruction. If however, we happen to know
that the destination of the branch is in the same section as the
- branch instruciton itself, then we can compute the relocation for
+ branch instruction itself, then we can compute the relocation for
ourselves and not have to bother the linker with it.
FIXME: The tests for OBJ_ELF and ! target_oabi are only here
if (! fixP->fx_done)
#endif
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("gas can't handle same-section branch dest >= 0x04000000"));
+ _("GAS can't handle same-section branch dest >= 0x04000000"));
}
value >>= 2;
value += diff;
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
+ _("branch out of range"));
newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
}
md_number_to_chars (buf, newval, THUMB_SIZE);
value += diff;
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
+ _("branch out of range"));
newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
}
md_number_to_chars (buf, newval, THUMB_SIZE);
value = fixP->fx_offset;
#endif
value += diff;
+
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch with link out of range"));
+ _("branch with link out of range"));
newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
- /* Remove bit zero of the adjusted offset. Bit zero can only be
- set if the upper insn is at a half-word boundary, since the
- destination address, an ARM instruction, must always be on a
- word boundary. The semantics of the BLX (1) instruction, however,
- are that bit zero in the offset must always be zero, and the
- corresponding bit one in the target address will be set from bit
- one of the source address. */
- newval2 &= ~1;
+ /* For a BLX instruction, make sure that the relocation is rounded up
+ to a word boundary. This follows the semantics of the instruction
+ which specifies that bit 1 of the target address will come from bit
+ 1 of the base address. */
+ newval2 = (newval2 + 1) & ~ 1;
md_number_to_chars (buf, newval, THUMB_SIZE);
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
}
break;
#endif
- case BFD_RELOC_ARM_GOTPC:
- md_number_to_chars (buf, value, 4);
- break;
-
case BFD_RELOC_ARM_CP_OFF_IMM:
sign = value >= 0;
if (value < -1023 || value > 1023 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal value for co-processor offset"));
+ _("illegal value for co-processor offset"));
if (value < 0)
value = -value;
newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
md_number_to_chars (buf, newval, INSN_SIZE);
break;
+ case BFD_RELOC_ARM_CP_OFF_IMM_S2:
+ sign = value >= 0;
+ if (value < -255 || value > 255)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("Illegal value for co-processor offset"));
+ if (value < 0)
+ value = -value;
+ newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
+ newval |= value | (sign ? INDEX_UP : 0);
+ md_number_to_chars (buf, newval , INSN_SIZE);
+ break;
+
case BFD_RELOC_ARM_THUMB_OFFSET:
newval = md_chars_to_number (buf, THUMB_SIZE);
/* Exactly what ranges, and where the offset is inserted depends
if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, target not word aligned (0x%08X)"),
+ _("invalid offset, target not word aligned (0x%08X)"),
(unsigned int) (fixP->fx_frag->fr_address
+ fixP->fx_where + value));
if ((value + 2) & ~0x3fe)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"),
+ (long) value);
/* Round up, since pc will be rounded down. */
newval |= (value + 2) >> 2;
case 9: /* SP load/store. */
if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"),
+ (long) value);
newval |= value >> 2;
break;
case 6: /* Word load/store. */
if (value & ~0x7c)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"),
+ (long) value);
newval |= value << 4; /* 6 - 2. */
break;
case 7: /* Byte load/store. */
if (value & ~0x1f)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"),
+ (long) value);
newval |= value << 6;
break;
case 8: /* Halfword load/store. */
if (value & ~0x3e)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"),
+ (long) value);
newval |= value << 5; /* 6 - 1. */
break;
{
if (value & ~0x1fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for stack address calculation"));
+ _("invalid immediate for stack address calculation"));
newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
newval |= value >> 2;
}
if (subtract ||
value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for address calculation (value = 0x%08lX)"),
+ _("invalid immediate for address calculation (value = 0x%08lX)"),
(unsigned long) value);
newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
newval |= rd << 8;
{
if (value & ~0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 8bit immediate"));
+ _("invalid 8bit immediate"));
newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
newval |= (rd << 8) | value;
}
{
if (value & ~0x7)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 3bit immediate"));
+ _("invalid 3bit immediate"));
newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
newval |= rd | (rs << 3) | (value << 6);
}
case 0x05: /* 8bit immediate CMP. */
if (value < 0 || value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate: %ld is too large"),
+ _("invalid immediate: %ld is too large"),
(long) value);
newval |= value;
break;
/* 5bit shift value (0..31). */
if (value < 0 || value > 31)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal Thumb shift value: %ld"), (long) value);
+ _("illegal Thumb shift value: %ld"), (long) value);
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
newval |= value << 6;
md_number_to_chars (buf, newval, THUMB_SIZE);
case BFD_RELOC_NONE:
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
+ _("bad relocation fixup type (%d)"), fixP->fx_r_type);
}
}
case BFD_RELOC_ARM_LITERAL:
case BFD_RELOC_ARM_HWLITERAL:
- /* If this is called then the a literal has been referenced across
- a section boundary - possibly due to an implicit dump. */
+ /* If this is called then the a literal has
+ been referenced across a section boundary. */
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Literal referenced across section boundary (Implicit dump?)"));
+ _("literal referenced across section boundary"));
return NULL;
#ifdef OBJ_ELF
case BFD_RELOC_ARM_IMMEDIATE:
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
- fixp->fx_r_type);
+ _("internal relocation (type: IMMEDIATE) not fixed up"));
return NULL;
case BFD_RELOC_ARM_ADRL_IMMEDIATE:
case BFD_RELOC_ARM_OFFSET_IMM:
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
- fixp->fx_r_type);
+ _("internal_relocation (type: OFFSET_IMM) not fixed up"));
return NULL;
default:
switch (fixp->fx_r_type)
{
- case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
- case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
case BFD_RELOC_ARM_SWI: type = "SWI"; break;
default: type = _("<unknown>"); break;
}
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Cannot represent %s relocation in this object file format"),
+ _("cannot represent %s relocation in this object file format"),
type);
return NULL;
}
}
#ifdef OBJ_ELF
- if (code == BFD_RELOC_32_PCREL
+ if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
&& GOT_symbol
&& fixp->fx_addsy == GOT_symbol)
{
if (reloc->howto == NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Can not represent %s relocation in this object file format"),
+ _("cannot represent %s relocation in this object file format"),
bfd_get_reloc_code_name (code));
return NULL;
}
}
static void
-output_inst PARAMS ((void))
+output_inst (str)
+ const char *str;
{
char * to = NULL;
if (inst.error)
{
- as_bad (inst.error);
+ as_bad ("%s -- `%s'", inst.error, str);
return;
}
md_assemble (str)
char * str;
{
- char c;
- char * p;
- char * q;
- char * start;
+ char c;
+ char *p;
+ char *start;
/* Align the instruction.
This may not be the right thing to do but ... */
#if 0
arm_align (2, 0);
#endif
- listing_prev_line (); /* Defined in listing.h. */
/* Align the previous label if needed. */
if (last_label_seen != NULL)
if (p == str)
{
- as_bad (_("No operator -- statement `%s'\n"), str);
+ as_bad (_("no operator -- statement `%s'\n"), str);
return;
}
/* Check that this instruction is supported for this CPU. */
if (thumb_mode == 1 && (opcode->variant & cpu_variant) == 0)
{
- as_bad (_("selected processor does not support this opcode"));
+ as_bad (_("selected processor does not support `%s'"), str);
return;
}
+ mapping_state (MAP_THUMB);
inst.instruction = opcode->value;
inst.size = opcode->size;
(*opcode->parms) (p);
- output_inst ();
+ output_inst (str);
return;
}
}
c = *p;
*p = '\0';
- opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
+ opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, str);
*p = c;
if (opcode)
/* Check that this instruction is supported for this CPU. */
if ((opcode->variant & cpu_variant) == 0)
{
- as_bad (_("selected processor does not support this opcode"));
+ as_bad (_("selected processor does not support `%s'"), str);
return;
}
+ mapping_state (MAP_ARM);
inst.instruction = opcode->value;
inst.size = INSN_SIZE;
(*opcode->parms) (p);
- output_inst ();
+ output_inst (str);
return;
}
}
/* It wasn't an instruction, but it might be a register alias of the form
alias .req reg. */
- q = p;
- skip_whitespace (q);
-
- c = *p;
- *p = '\0';
-
- if (*q && !strncmp (q, ".req ", 4))
- {
- int reg;
- char * copy_of_str;
- char * r;
-
-#ifdef IGNORE_OPCODE_CASE
- str = original_case_string;
-#endif
- copy_of_str = str;
-
- q += 4;
- skip_whitespace (q);
-
- for (r = q; *r != '\0'; r++)
- if (*r == ' ')
- break;
-
- if (r != q)
- {
- int regnum;
- char d = *r;
-
- *r = '\0';
- regnum = arm_reg_parse (& q);
- *r = d;
-
- reg = arm_reg_parse (& str);
-
- if (reg == FAIL)
- {
- if (regnum != FAIL)
- insert_reg_alias (str, regnum);
- else
- as_warn (_("register '%s' does not exist\n"), q);
- }
- else if (regnum != FAIL)
- {
- if (reg != regnum)
- as_warn (_("ignoring redefinition of register alias '%s'"),
- copy_of_str);
-
- /* Do not warn about redefinitions to the same alias. */
- }
- else
- as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
- copy_of_str, q);
- }
- else
- as_warn (_("ignoring incomplete .req pseuso op"));
-
- *p = c;
- return;
- }
+ if (create_register_alias (str, p))
+ return;
- *p = c;
as_bad (_("bad instruction `%s'"), start);
}
/* md_parse_option
Invocation line includes a switch not recognized by the base assembler.
- See if it's a processor-specific option. These are:
+ See if it's a processor-specific option.
+
+ This routine is somewhat complicated by the need for backwards
+ compatibility (since older releases of gcc can't be changed).
+ The new options try to make the interface as compatible as
+ possible with GCC.
+
+ New options (supported) are:
+
+ -mcpu=<cpu name> Assemble for selected processor
+ -march=<architecture name> Assemble for selected architecture
+ -mfpu=<fpu architecture> Assemble for selected FPU.
+ -EB/-mbig-endian Big-endian
+ -EL/-mlittle-endian Little-endian
+ -k Generate PIC code
+ -mthumb Start in Thumb mode
+ -mthumb-interwork Code supports ARM/Thumb interworking
+
+ For now we will also provide support for:
+
+ -mapcs-32 32-bit Program counter
+ -mapcs-26 26-bit Program counter
+ -macps-float Floats passed in FP registers
+ -mapcs-reentrant Reentrant code
+ -matpcs
+ (sometime these will probably be replaced with -mapcs=<list of options>
+ and -matpcs=<list of options>)
+
+ The remaining options are only supported for back-wards compatibility.
Cpu variants, the arm part is optional:
-m[arm]1 Currently not supported.
-m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
-m[arm]7[xx][t][[d]m] Arm 7 processors
-m[arm]8[10] Arm 8 processors
-m[arm]9[20][tdmi] Arm 9 processors
- -marm9e Allow Cirrus/DSP instructions
-mstrongarm[110[0]] StrongARM processors
-mxscale XScale processors
-m[arm]v[2345[t[e]]] Arm architectures
FP variants:
-mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
-mfpe-old (No float load/store multiples)
+ -mvfpxd VFP Single precision
+ -mvfp All VFP
-mno-fpu Disable all floating point instructions
- Run-time endian selection:
- -EB big endian cpu
- -EL little endian cpu
- ARM Procedure Calling Standard:
- -mapcs-32 32 bit APCS
- -mapcs-26 26 bit APCS
- -mapcs-float Pass floats in float regs
- -mapcs-reentrant Position independent code
- -mthumb-interwork Code supports Arm/Thumb interworking
- -matpcs ARM/Thumb Procedure Call Standard
- -moabi Old ELF ABI */
-const char * md_shortopts = "m:k";
+ The following CPU names are recognized:
+ arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
+ arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
+ arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
+ arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
+ arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
+ arm10t arm10e, arm1020t, arm1020e, arm10200e,
+ strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
+
+ */
+
+const char * md_shortopts = "m:k";
+
+#ifdef ARM_BI_ENDIAN
+#define OPTION_EB (OPTION_MD_BASE + 0)
+#define OPTION_EL (OPTION_MD_BASE + 1)
+#else
+#if TARGET_BYTES_BIG_ENDIAN
+#define OPTION_EB (OPTION_MD_BASE + 0)
+#else
+#define OPTION_EL (OPTION_MD_BASE + 1)
+#endif
+#endif
+
+struct option md_longopts[] =
+{
+#ifdef OPTION_EB
+ {"EB", no_argument, NULL, OPTION_EB},
+#endif
+#ifdef OPTION_EL
+ {"EL", no_argument, NULL, OPTION_EL},
+#endif
+ {NULL, no_argument, NULL, 0}
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+struct arm_option_table
+{
+ char *option; /* Option name to match. */
+ char *help; /* Help information. */
+ int *var; /* Variable to change. */
+ int value; /* What to change it to. */
+ char *deprecated; /* If non-null, print this message. */
+};
+
+struct arm_option_table arm_opts[] =
+{
+ {"k", N_("generate PIC code"), &pic_code, 1, NULL},
+ {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
+ {"mthumb-interwork", N_("support ARM/Thumb interworking"),
+ &support_interwork, 1, NULL},
+ {"moabi", N_("use old ABI (ELF only)"), &target_oabi, 1, NULL},
+ {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
+ {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
+ {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
+ 1, NULL},
+ {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
+ {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
+ {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
+ {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 1,
+ NULL},
+
+ /* These are recognized by the assembler, but have no affect on code. */
+ {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
+ {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
+
+ /* DON'T add any new processors to this list -- we want the whole list
+ to go away... Add them to the processors table instead. */
+ {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
+ {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
+ {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
+ {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
+ {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
+ {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
+ {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
+ {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
+ {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
+ {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
+ {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
+ {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
+ {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
+ {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
+ {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
+ {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
+ {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
+ {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
+ {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
+ {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
+ {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
+ {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
+ {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
+ {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
+ {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
+ {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
+ {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
+ {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
+ {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
+ {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
+ {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
+ {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
+ {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
+ {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
+ {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
+ {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
+ {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
+ {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
+ {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
+ {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
+ {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
+ {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
+ {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
+ {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
+ {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
+ {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
+ {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+ {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+ {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+ {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+ {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
+ {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
+ {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
+ {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
+ {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
+ {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
+ {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
+ {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
+ {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
+ {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
+ {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
+ {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
+ {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
+ {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
+ {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
+ {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
+ {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
+ {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
+ {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
+ {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
+ N_("use -mcpu=strongarm110")},
+ {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
+ N_("use -mcpu=strongarm1100")},
+ {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
+ N_("use -mcpu=strongarm1110")},
+ {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
+ {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
+ {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
+
+ /* Architecture variants -- don't add any more to this list either. */
+ {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
+ {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
+ {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
+ {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
+ {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
+ {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
+ {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
+ {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
+ {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
+ {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
+ {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
+ {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
+ {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
+ {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
+ {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
+ {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
+ {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
+ {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
+
+ /* Floating point variants -- don't add any more to this list either. */
+ {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
+ {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
+ {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
+ {"mno-fpu", NULL, &legacy_fpu, 0,
+ N_("use either -mfpu=softfpa or -mfpu=softvfp")},
+
+ {NULL, NULL, NULL, 0, NULL}
+};
+
+struct arm_cpu_option_table
+{
+ char *name;
+ int value;
+ /* For some CPUs we assume an FPU unless the user explicitly sets
+ -mfpu=... */
+ int default_fpu;
+};
+
+/* This list should, at a minimum, contain all the cpu names
+ recognized by GCC. */
+static struct arm_cpu_option_table arm_cpus[] =
+{
+ {"all", ARM_ANY, FPU_ARCH_FPA},
+ {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
+ {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
+ {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
+ {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
+ {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
+ {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
+ {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
+ {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ /* For V5 or later processors we default to using VFP; but the user
+ should really set the FPU type explicitly. */
+ {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
+ {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
+ {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
+ {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
+ {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
+ {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
+ {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm1136js", ARM_ARCH_V6, FPU_NONE},
+ {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
+ /* ??? XSCALE is really an architecture. */
+ {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
+ /* ??? iwmmxt is not a processor. */
+ {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
+ {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
+ /* Maverick */
+ {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_NONE},
+ {NULL, 0, 0}
+};
+
+struct arm_arch_option_table
+{
+ char *name;
+ int value;
+ int default_fpu;
+};
-struct option md_longopts[] =
+/* This list should, at a minimum, contain all the architecture names
+ recognized by GCC. */
+static struct arm_arch_option_table arm_archs[] =
+{
+ {"all", ARM_ANY, FPU_ARCH_FPA},
+ {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
+ {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
+ {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
+ {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
+ {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
+ {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
+ {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
+ {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
+ {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
+ {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
+ {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
+ {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
+ {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
+ {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
+ {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
+ {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
+ {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
+ {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
+ {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
+ {NULL, 0, 0}
+};
+
+/* ISA extensions in the co-processor space. */
+struct arm_arch_extension_table
{
-#ifdef ARM_BI_ENDIAN
-#define OPTION_EB (OPTION_MD_BASE + 0)
- {"EB", no_argument, NULL, OPTION_EB},
-#define OPTION_EL (OPTION_MD_BASE + 1)
- {"EL", no_argument, NULL, OPTION_EL},
-#ifdef OBJ_ELF
-#define OPTION_OABI (OPTION_MD_BASE +2)
- {"oabi", no_argument, NULL, OPTION_OABI},
-#endif
-#endif
- {NULL, no_argument, NULL, 0}
+ char *name;
+ int value;
};
-size_t md_longopts_size = sizeof (md_longopts);
+static struct arm_arch_extension_table arm_extensions[] =
+{
+ {"maverick", ARM_CEXT_MAVERICK},
+ {"xscale", ARM_CEXT_XSCALE},
+ {"iwmmxt", ARM_CEXT_IWMMXT},
+ {NULL, 0}
+};
-int
-md_parse_option (c, arg)
- int c;
- char * arg;
+struct arm_fpu_option_table
+{
+ char *name;
+ int value;
+};
+
+/* This list should, at a minimum, contain all the fpu names
+ recognized by GCC. */
+static struct arm_fpu_option_table arm_fpus[] =
+{
+ {"softfpa", FPU_NONE},
+ {"fpe", FPU_ARCH_FPE},
+ {"fpe2", FPU_ARCH_FPE},
+ {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
+ {"fpa", FPU_ARCH_FPA},
+ {"fpa10", FPU_ARCH_FPA},
+ {"fpa11", FPU_ARCH_FPA},
+ {"arm7500fe", FPU_ARCH_FPA},
+ {"softvfp", FPU_ARCH_VFP},
+ {"softvfp+vfp", FPU_ARCH_VFP_V2},
+ {"vfp", FPU_ARCH_VFP_V2},
+ {"vfp9", FPU_ARCH_VFP_V2},
+ {"vfp10", FPU_ARCH_VFP_V2},
+ {"vfp10-r0", FPU_ARCH_VFP_V1},
+ {"vfpxd", FPU_ARCH_VFP_V1xD},
+ {"arm1020t", FPU_ARCH_VFP_V1},
+ {"arm1020e", FPU_ARCH_VFP_V2},
+ {"arm1136jfs", FPU_ARCH_VFP_V2},
+ {NULL, 0}
+};
+
+struct arm_long_option_table
{
- char * str = arg;
+ char *option; /* Substring to match. */
+ char *help; /* Help information. */
+ int (*func) PARAMS ((char *subopt)); /* Function to decode sub-option. */
+ char *deprecated; /* If non-null, print this message. */
+};
- switch (c)
+static int
+arm_parse_extension (str, opt_p)
+ char *str;
+ int *opt_p;
+{
+ while (str != NULL && *str != 0)
{
-#ifdef ARM_BI_ENDIAN
- case OPTION_EB:
- target_big_endian = 1;
- break;
- case OPTION_EL:
- target_big_endian = 0;
- break;
-#endif
+ struct arm_arch_extension_table *opt;
+ char *ext;
+ int optlen;
- case 'm':
- switch (*str)
+ if (*str != '+')
{
- case 'f':
- if (streq (str, "fpa10") || streq (str, "fpa11"))
- cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_ARCH_FPA;
- else if (streq (str, "fpe-old"))
- cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_ARCH_FPE;
- else
- goto bad;
- break;
+ as_bad (_("invalid architectural extension"));
+ return 0;
+ }
- case 'n':
- if (streq (str, "no-fpu"))
- cpu_variant &= ~FPU_ANY;
- break;
+ str++;
+ ext = strchr (str, '+');
-#ifdef OBJ_ELF
- case 'o':
- if (streq (str, "oabi"))
- target_oabi = true;
- break;
-#endif
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
- case 't':
- /* Limit assembler to generating only Thumb instructions: */
- if (streq (str, "thumb"))
- {
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_V4T;
- cpu_variant = (cpu_variant & ~FPU_ANY) | FPU_NONE;
- thumb_mode = 1;
- }
- else if (streq (str, "thumb-interwork"))
- {
- if ((cpu_variant & ARM_EXT_V4T) == 0)
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
-#if defined OBJ_COFF || defined OBJ_ELF
- support_interwork = true;
-#endif
- }
- else
- goto bad;
- break;
+ if (optlen == 0)
+ {
+ as_bad (_("missing architectural extension"));
+ return 0;
+ }
- default:
- if (streq (str, "all"))
- {
- cpu_variant = ARM_ALL | FPU_DEFAULT;
- return 1;
- }
-#if defined OBJ_COFF || defined OBJ_ELF
- if (! strncmp (str, "apcs-", 5))
- {
- /* GCC passes on all command line options starting "-mapcs-..."
- to us, so we must parse them here. */
+ for (opt = arm_extensions; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ *opt_p |= opt->value;
+ break;
+ }
- str += 5;
+ if (opt->name == NULL)
+ {
+ as_bad (_("unknown architectural extnsion `%s'"), str);
+ return 0;
+ }
- if (streq (str, "32"))
- {
- uses_apcs_26 = false;
- return 1;
- }
- else if (streq (str, "26"))
- {
- uses_apcs_26 = true;
- return 1;
- }
- else if (streq (str, "frame"))
- {
- /* Stack frames are being generated - does not affect
- linkage of code. */
- return 1;
- }
- else if (streq (str, "stack-check"))
- {
- /* Stack checking is being performed - does not affect
- linkage, but does require that the functions
- __rt_stkovf_split_small and __rt_stkovf_split_big be
- present in the final link. */
+ str = ext;
+ };
- return 1;
- }
- else if (streq (str, "float"))
- {
- /* Floating point arguments are being passed in the floating
- point registers. This does affect linking, since this
- version of the APCS is incompatible with the version that
- passes floating points in the integer registers. */
+ return 1;
+}
- uses_apcs_float = true;
- return 1;
- }
- else if (streq (str, "reentrant"))
- {
- /* Reentrant code has been generated. This does affect
- linking, since there is no point in linking reentrant/
- position independent code with absolute position code. */
- pic_code = true;
- return 1;
- }
+static int
+arm_parse_cpu (str)
+ char *str;
+{
+ struct arm_cpu_option_table *opt;
+ char *ext = strchr (str, '+');
+ int optlen;
- as_bad (_("Unrecognised APCS switch -m%s"), arg);
- return 0;
- }
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
- if (! strcmp (str, "atpcs"))
- {
- atpcs = true;
- return 1;
- }
-#endif
- /* Strip off optional "arm". */
- if (! strncmp (str, "arm", 3))
- str += 3;
+ if (optlen == 0)
+ {
+ as_bad (_("missing cpu name `%s'"), str);
+ return 0;
+ }
- switch (*str)
- {
- case '1':
- if (streq (str, "1"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
- else
- goto bad;
- break;
+ for (opt = arm_cpus; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ mcpu_cpu_opt = opt->value;
+ mcpu_fpu_opt = opt->default_fpu;
- case '2':
- if (streq (str, "2"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
- else if (streq (str, "250"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
- else
- goto bad;
- break;
+ if (ext != NULL)
+ return arm_parse_extension (ext, &mcpu_cpu_opt);
- case '3':
- if (streq (str, "3"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
- else
- goto bad;
- break;
+ return 1;
+ }
- case '6':
- switch (strtol (str, NULL, 10))
- {
- case 6:
- case 60:
- case 600:
- case 610:
- case 620:
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
- break;
- default:
- goto bad;
- }
- break;
+ as_bad (_("unknown cpu `%s'"), str);
+ return 0;
+}
- case '7':
- /* Eat the processor name. */
- switch (strtol (str, & str, 10))
- {
- case 7:
- case 70:
- case 700:
- case 710:
- case 720:
- case 7100:
- case 7500:
- break;
- default:
- goto bad;
- }
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
- for (; *str; str++)
- {
- switch (*str)
- {
- case 't':
- cpu_variant |= ARM_ARCH_V4T;
- break;
+static int
+arm_parse_arch (str)
+ char *str;
+{
+ struct arm_arch_option_table *opt;
+ char *ext = strchr (str, '+');
+ int optlen;
- case 'm':
- cpu_variant |= ARM_EXT_V3M;
- break;
+ if (ext != NULL)
+ optlen = ext - str;
+ else
+ optlen = strlen (str);
- case 'f': /* fe => fp enabled cpu. */
- if (str[1] == 'e')
- ++ str;
- else
- goto bad;
+ if (optlen == 0)
+ {
+ as_bad (_("missing architecture name `%s'"), str);
+ return 0;
+ }
- case 'c': /* Left over from 710c processor name. */
- case 'd': /* Debug. */
- case 'i': /* Embedded ICE. */
- /* Included for completeness in ARM processor naming. */
- break;
- default:
- goto bad;
- }
- }
- break;
+ for (opt = arm_archs; opt->name != NULL; opt++)
+ if (strcmp (opt->name, str) == 0)
+ {
+ march_cpu_opt = opt->value;
+ march_fpu_opt = opt->default_fpu;
- case '8':
- if (streq (str, "8") || streq (str, "810"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4;
- else
- goto bad;
- break;
+ if (ext != NULL)
+ return arm_parse_extension (ext, &march_cpu_opt);
- case '9':
- if (streq (str, "9"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else if (streq (str, "920"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4;
- else if (streq (str, "920t"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else if (streq (str, "9tdmi"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else if (streq (str, "9e"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T | ARM_EXT_MAVERICK;
- else
- goto bad;
- break;
+ return 1;
+ }
- case 's':
- if (streq (str, "strongarm")
- || streq (str, "strongarm110")
- || streq (str, "strongarm1100"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4;
- else
- goto bad;
- break;
+ as_bad (_("unknown architecture `%s'\n"), str);
+ return 0;
+}
- case 'x':
- if (streq (str, "xscale"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_XSCALE;
- else
- goto bad;
- break;
-
- case 'v':
- /* Select variant based on architecture rather than
- processor. */
- switch (*++str)
- {
- case '2':
- switch (*++str)
- {
- case 'a':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
- break;
- case 0:
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
- break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
+static int
+arm_parse_fpu (str)
+ char *str;
+{
+ struct arm_fpu_option_table *opt;
- case '3':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
+ for (opt = arm_fpus; opt->name != NULL; opt++)
+ if (strcmp (opt->name, str) == 0)
+ {
+ mfpu_opt = opt->value;
+ return 1;
+ }
- switch (*++str)
- {
- case 'm': cpu_variant |= ARM_EXT_V3M; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
+ as_bad (_("unknown floating point format `%s'\n"), str);
+ return 0;
+}
- case '4':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
+struct arm_long_option_table arm_long_opts[] =
+{
+ {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
+ arm_parse_cpu, NULL},
+ {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
+ arm_parse_arch, NULL},
+ {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
+ arm_parse_fpu, NULL},
+ {NULL, NULL, 0, NULL}
+};
- switch (*++str)
- {
- case 't': cpu_variant |= ARM_EXT_V4T; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
+int
+md_parse_option (c, arg)
+ int c;
+ char * arg;
+{
+ struct arm_option_table *opt;
+ struct arm_long_option_table *lopt;
- case '5':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
- switch (*++str)
- {
- case 't': cpu_variant |= ARM_EXT_V4T; break;
- case 'e': cpu_variant |= ARM_EXT_V5E; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
+ switch (c)
+ {
+#ifdef OPTION_EB
+ case OPTION_EB:
+ target_big_endian = 1;
+ break;
+#endif
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
+#ifdef OPTION_EL
+ case OPTION_EL:
+ target_big_endian = 0;
+ break;
+#endif
- default:
- bad:
- as_bad (_("Invalid processor variant -m%s"), arg);
- return 0;
+ case 'a':
+ /* Listing option. Just ignore these, we don't support additional
+ ones. */
+ return 0;
+
+ default:
+ for (opt = arm_opts; opt->option != NULL; opt++)
+ {
+ if (c == opt->option[0]
+ && ((arg == NULL && opt->option[1] == 0)
+ || strcmp (arg, opt->option + 1) == 0))
+ {
+#if WARN_DEPRECATED
+ /* If the option is deprecated, tell the user. */
+ if (opt->deprecated != NULL)
+ as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
+ arg ? arg : "", _(opt->deprecated));
+#endif
+
+ if (opt->var != NULL)
+ *opt->var = opt->value;
+
+ return 1;
}
}
- break;
-#if defined OBJ_ELF || defined OBJ_COFF
- case 'k':
- pic_code = 1;
- break;
+ for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
+ {
+ /* These options are expected to have an argument. */
+ if (c == lopt->option[0]
+ && arg != NULL
+ && strncmp (arg, lopt->option + 1,
+ strlen (lopt->option + 1)) == 0)
+ {
+#if WARN_DEPRECATED
+ /* If the option is deprecated, tell the user. */
+ if (lopt->deprecated != NULL)
+ as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
+ _(lopt->deprecated));
#endif
- default:
+ /* Call the sup-option parser. */
+ return (*lopt->func)(arg + strlen (lopt->option) - 1);
+ }
+ }
+
+ as_bad (_("unrecognized option `-%c%s'"), c, arg ? arg : "");
return 0;
}
md_show_usage (fp)
FILE * fp;
{
+ struct arm_option_table *opt;
+ struct arm_long_option_table *lopt;
+
+ fprintf (fp, _(" ARM-specific assembler options:\n"));
+
+ for (opt = arm_opts; opt->option != NULL; opt++)
+ if (opt->help != NULL)
+ fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
+
+ for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
+ if (lopt->help != NULL)
+ fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
+
+#ifdef OPTION_EB
fprintf (fp, _("\
- ARM Specific Assembler Options:\n\
- -m[arm][<processor name>] select processor variant\n\
- -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
- -marm9e allow Cirrus/DSP instructions\n\
- -mthumb only allow Thumb instructions\n\
- -mthumb-interwork mark the assembled code as supporting interworking\n\
- -mall allow any instruction\n\
- -mfpa10, -mfpa11 select floating point architecture\n\
- -mfpe-old don't allow floating-point multiple instructions\n\
- -mno-fpu don't allow any floating-point instructions.\n\
- -k generate PIC code.\n"));
-#if defined OBJ_COFF || defined OBJ_ELF
- fprintf (fp, _("\
- -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
- -matpcs use ARM/Thumb Procedure Calling Standard\n\
- -mapcs-float floating point args are passed in FP regs\n\
- -mapcs-reentrant the code is position independent/reentrant\n"));
-#endif
-#ifdef OBJ_ELF
- fprintf (fp, _("\
- -moabi support the old ELF ABI\n"));
+ -EB assemble code for a big-endian cpu\n"));
#endif
-#ifdef ARM_BI_ENDIAN
+
+#ifdef OPTION_EL
fprintf (fp, _("\
- -EB assemble code for a big endian cpu\n\
- -EL assemble code for a little endian cpu\n"));
+ -EL assemble code for a little-endian cpu\n"));
#endif
}
void
arm_cleanup ()
{
- if (current_poolP == NULL)
- return;
+ literal_pool * pool;
- /* Put it at the end of text section. */
- subseg_set (text_section, 0);
- s_ltorg (0);
- listing_prev_line ();
+ for (pool = list_of_pools; pool; pool = pool->next)
+ {
+ /* Put it at the end of the relevent section. */
+ subseg_set (pool->section, pool->sub_section);
+ s_ltorg (0);
+ }
}
void
lsl r3, r3, #2
ldr r2, [r3, r2]
mov pc, r2
-
+
.Lbbb: .word .Lxxx
.Lccc: .word .Lyyy
..etc...
The second instruction converts a table index into a byte offset.
The third instruction gets the jump address out of the table.
The fourth instruction performs the jump.
-
+
If the address stored at .Laaa is that of a symbol which has the
Thumb_Func bit set, then the linker will arrange for this address
to have the bottom bit set, which in turn would mean that the
THUMB_SET_FUNC (sym, 1);
- label_is_thumb_function_name = false;
+ label_is_thumb_function_name = FALSE;
}
}
as_bad (_("%s: unexpected function type: %d"),
S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
}
- else switch (S_GET_STORAGE_CLASS (sym))
+ else switch (S_GET_STORAGE_CLASS (sym))
{
case C_EXT:
S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
return name;
}
-boolean
+#if defined OBJ_COFF || defined OBJ_ELF
+void
arm_validate_fix (fixP)
fixS * fixP;
{
&& ! THUMB_IS_FUNC (fixP->fx_addsy))
{
fixP->fx_addsy = find_real_start (fixP->fx_addsy);
- return true;
}
+}
+#endif
+
+int
+arm_force_relocation (fixp)
+ struct fix * fixp;
+{
+#if defined (OBJ_COFF) && defined (TE_PE)
+ if (fixp->fx_r_type == BFD_RELOC_RVA)
+ return 1;
+#endif
+#ifdef OBJ_ELF
+ if (fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
+ || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
+ || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
+ || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
+ return 1;
+#endif
+
+ /* Resolve these relocations even if the symbol is extern or weak. */
+ if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
+ || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
+ || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+ return 0;
- return false;
+ return generic_force_reloc (fixp);
}
#ifdef OBJ_COFF
be resolved before the binbary is emitted, so it is safe to say that
it is adjustable. */
-boolean
+bfd_boolean
arm_fix_adjustable (fixP)
fixS * fixP;
{
return 0;
}
#endif
+
#ifdef OBJ_ELF
/* Relocations against Thumb function names must be left unadjusted,
so that the linker can use this information to correctly set the
addresses also ought to have their bottom bit set (assuming that
they reside in Thumb code), but at the moment they will not. */
-boolean
+bfd_boolean
arm_fix_adjustable (fixP)
fixS * fixP;
{
if (fixP->fx_addsy == NULL)
return 1;
- /* Prevent all adjustments to global symbols. */
- if (S_IS_EXTERN (fixP->fx_addsy))
- return 0;
-
- if (S_IS_WEAK (fixP->fx_addsy))
- return 0;
-
if (THUMB_IS_FUNC (fixP->fx_addsy)
&& fixP->fx_subsy == NULL)
return 0;
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
+ /* Don't allow symbols to be discarded on GOT related relocs. */
+ if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
+ || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
+ || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF)
+ return 0;
+
return 1;
}
elf_frob_symbol (symp, puntp);
}
-int
-arm_force_relocation (fixp)
- struct fix * fixp;
-{
- if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
- || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
- || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
- || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
- || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
- return 1;
-
- return 0;
-}
-
static bfd_reloc_code_real_type
arm_parse_reloc ()
{
md_cons_align (nbytes);
#endif
+ mapping_state (MAP_DATA);
do
{
bfd_reloc_code_real_type reloc;
int bytes, fix, noop_size;
char * p;
const char * noop;
-
+
if (fragP->fr_type != rs_align_code)
return;
bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
p = fragP->fr_literal + fragP->fr_fix;
fix = 0;
-
+
if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
-
+
if (fragP->tc_frag_data)
{
if (target_big_endian)
noop = arm_noop;
noop_size = sizeof (arm_noop);
}
-
+
if (bytes & (noop_size - 1))
{
fix = bytes & (noop_size - 1);
bytes -= noop_size;
fix += noop_size;
}
-
+
fragP->fr_fix += fix;
fragP->fr_var = noop_size;
}
{
char * p;
- /* We assume that there will never be a requirment
+ /* We assume that there will never be a requirement
to support alignments greater than 32 bytes. */
if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
-
+
p = frag_var (rs_align_code,
MAX_MEM_FOR_RS_ALIGN_CODE,
1,
projects / deliverable / binutils-gdb.git / blobdiff