#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
+#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */
#define FPU_NONE 0
#define FPU_ARCH_FPE FPU_FPA_EXT_V1
#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
+#define FPU_ARCH_MAVERICK FPU_MAVERICK
+
+enum arm_float_abi
+{
+ ARM_FLOAT_ABI_HARD,
+ ARM_FLOAT_ABI_SOFTFP,
+ ARM_FLOAT_ABI_SOFT
+};
+
/* Types of processor to assemble for. */
#define ARM_1 ARM_ARCH_V1
#define ARM_2 ARM_ARCH_V2
static int march_cpu_opt = -1;
static int march_fpu_opt = -1;
static int mfpu_opt = -1;
+static int mfloat_abi_opt = -1;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
static void do_vfp_dp_dyadic PARAMS ((char *));
static void do_vfp_reg_from_sp PARAMS ((char *));
static void do_vfp_sp_from_reg PARAMS ((char *));
-static void do_vfp_sp_reg2 PARAMS ((char *));
+static void do_vfp_reg2_from_sp2 PARAMS ((char *));
+static void do_vfp_sp2_from_reg2 PARAMS ((char *));
static void do_vfp_reg_from_dp PARAMS ((char *));
static void do_vfp_reg2_from_dp PARAMS ((char *));
static void do_vfp_dp_from_reg PARAMS ((char *));
{"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
/* VFP V2. */
- {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
- {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
+ {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp2_from_reg2},
+ {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_sp2},
{"fmdrr", 0xec400b10, 5, FPU_VFP_EXT_V2, do_vfp_dp_from_reg2},
{"fmrrd", 0xec500b10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_dp},
static int arm_parse_cpu PARAMS ((char *));
static int arm_parse_arch PARAMS ((char *));
static int arm_parse_fpu PARAMS ((char *));
+static int arm_parse_float_abi PARAMS ((char *));
#if 0 /* Suppressed - for now. */
#if defined OBJ_COFF || defined OBJ_ELF
static void arm_add_note PARAMS ((const char *, const char *, unsigned int));
{
/* Do nothing really. */
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
/* Expects *str -> the characters "acc0", possibly with leading blanks.
}
inst.instruction |= expr.X_add_number;
- return;
}
static void
if (reg != REG_PC && !inst.error)
inst.error = _("only r15 allowed here");
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tbcst, 0);
-
- return;
}
static void
return;
inst.instruction |= number & 0x7;
- return;
}
static void
return;
inst.instruction |= number & 0x7;
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmcr, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmcrr, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmia, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmovmsk, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmrc, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_tmrrc, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_rd, 0);
- return;
}
static void
return;
inst.instruction |= ((number & 0x7) << 20);
- return;
}
static void
return;
inst.instruction |= ((inst.instruction >> 16) & 0xf);
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_wrwr, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_wrwrwcg, 0);
-
- return;
}
static void
char * str;
{
check_iwmmxt_insn (str, check_wrwrwr, 0);
-
- return;
}
static void
return;
inst.instruction |= ((number & 0xf0) << 16) | (number & 0xf);
- return;
}
static void
return;
inst.instruction |= ((inst.instruction & 0xf) << 12) | ((inst.instruction & 0xf) << 16);
- return;
}
/* Xscale multiply-accumulate (argument parse)
}
end_of_line (str);
- return;
}
static void
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+#ifndef TE_WINCE
inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
+#endif
inst.reloc.pc_rel = 1;
end_of_line (str);
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+#ifndef TE_WINCE
inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
+#endif
inst.reloc.pc_rel = 1;
inst.size = INSN_SIZE * 2;
-
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static int
inst.instruction |= (pre_inc ? PRE_INDEX : 0);
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static int
inst.instruction |= (pre_inc ? PRE_INDEX : 0);
end_of_line (str);
- return;
}
static long
inst.instruction |= range;
end_of_line (str);
- return;
}
static void
inst.reloc.type = BFD_RELOC_ARM_SWI;
inst.reloc.pc_rel = 0;
end_of_line (str);
-
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
#endif /* OBJ_ELF */
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static int
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
-do_vfp_sp_reg2 (str)
+do_vfp_reg2_from_sp2 (str)
char *str;
{
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL)
- return;
-
- if (skip_past_comma (&str) == FAIL
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
|| reg_required_here (&str, 16) == FAIL
|| skip_past_comma (&str) == FAIL)
{
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
+}
+
+static void
+do_vfp_sp2_from_reg2 (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ /* We require exactly two consecutive SP registers. */
+ if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
+ {
+ if (! inst.error)
+ inst.error = _("only two consecutive VFP SP registers allowed here");
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
if (skip_past_comma (&str) == FAIL
|| reg_required_here (&str, 12) == FAIL
|| skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 16))
+ || reg_required_here (&str, 16) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
}
end_of_line (str);
- return;
}
static const struct vfp_reg *
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
/* Parse and encode a VFP SP register list, storing the initial
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
static void
}
end_of_line (str);
- return;
}
/* Thumb specific routines. */
fail_ldst:
if (!inst.error)
inst.error = BAD_ARGS;
- return;
}
static void
{
/* Do nothing. */
end_of_line (str);
- return;
}
/* Handle the Format 4 instructions that do not have equivalents in other
inst.reloc.type = BFD_RELOC_ARM_SWI;
end_of_line (str);
- return;
}
static void
if (uses_apcs_float) flags |= F_APCS_FLOAT;
if (pic_code) flags |= F_PIC;
if ((cpu_variant & FPU_ANY) == FPU_NONE
- || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
- flags |= F_SOFT_FLOAT;
+ || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
+ {
+ flags |= F_SOFT_FLOAT;
+ }
+ switch (mfloat_abi_opt)
+ {
+ case ARM_FLOAT_ABI_SOFT:
+ case ARM_FLOAT_ABI_SOFTFP:
+ flags |= F_SOFT_FLOAT;
+ break;
+
+ case ARM_FLOAT_ABI_HARD:
+ if (flags & F_SOFT_FLOAT)
+ as_bad (_("hard-float conflicts with specified fpu"));
+ break;
+ }
/* Using VFP conventions (even if soft-float). */
if (cpu_variant & FPU_VFP_EXT_NONE) flags |= F_VFP_FLOAT;
#if defined OBJ_ELF
- if (cpu_variant & ARM_CEXT_MAVERICK)
- {
- flags &= ~ F_SOFT_FLOAT;
+ if (cpu_variant & FPU_ARCH_MAVERICK)
flags |= EF_ARM_MAVERICK_FLOAT;
- }
#endif
bfd_set_private_flags (stdoutput, flags);
return NULL;
case BFD_RELOC_ARM_OFFSET_IMM:
+ if (fixp->fx_addsy != NULL
+ && !S_IS_DEFINED (fixp->fx_addsy)
+ && S_IS_LOCAL (fixp->fx_addsy))
+ {
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("undefined local label `%s'"),
+ S_GET_NAME (fixp->fx_addsy));
+ return NULL;
+ }
+
as_bad_where (fixp->fx_file, fixp->fx_line,
_("internal_relocation (type: OFFSET_IMM) not fixed up"));
return NULL;
{"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
+ {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
{"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm1026ejs", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm1136js", ARM_ARCH_V6, FPU_NONE},
{"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
/* ??? XSCALE is really an architecture. */
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
{"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
/* Maverick */
- {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_NONE},
+ {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
{NULL, 0, 0}
};
{"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
{"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
{"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
+ {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
{NULL, 0, 0}
{"arm1020t", FPU_ARCH_VFP_V1},
{"arm1020e", FPU_ARCH_VFP_V2},
{"arm1136jfs", FPU_ARCH_VFP_V2},
+ {"maverick", FPU_ARCH_MAVERICK},
+ {NULL, 0}
+};
+
+struct arm_float_abi_option_table
+{
+ char *name;
+ int value;
+};
+
+static struct arm_float_abi_option_table arm_float_abis[] =
+{
+ {"hard", ARM_FLOAT_ABI_HARD},
+ {"softfp", ARM_FLOAT_ABI_SOFTFP},
+ {"soft", ARM_FLOAT_ABI_SOFT},
{NULL, 0}
};
return 0;
}
+static int
+arm_parse_float_abi (str)
+ char * str;
+{
+ struct arm_float_abi_option_table *opt;
+
+ for (opt = arm_float_abis; opt->name != NULL; opt++)
+ if (strcmp (opt->name, str) == 0)
+ {
+ mfloat_abi_opt = opt->value;
+ return 1;
+ }
+
+ as_bad (_("unknown floating point abi `%s'\n"), str);
+ return 0;
+}
+
struct arm_long_option_table arm_long_opts[] =
{
{"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
arm_parse_arch, NULL},
{"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
arm_parse_fpu, NULL},
+ {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
+ arm_parse_float_abi, NULL},
{NULL, NULL, 0, NULL}
};
arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
new_fix->tc_fix_data = (PTR) arm_data;
arm_data->thumb_mode = thumb_mode;
-
- return;
}
/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
projects / deliverable / binutils-gdb.git / blobdiff