/* tc-bfin.c -- Assembler for the ADI Blackfin.
- Copyright 2005, 2006, 2007, 2008
- Free Software Foundation, Inc.
+ Copyright (C) 2005-2019 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
02110-1301, USA. */
#include "as.h"
-#include "struc-symbol.h"
#include "bfin-defs.h"
#include "obstack.h"
#include "safe-ctype.h"
#ifdef OBJ_ELF
#include "dwarf2dbg.h"
#endif
-#include "libbfd.h"
#include "elf/common.h"
#include "elf/bfin.h"
static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
-/* Registers list. */
-struct bfin_reg_entry
-{
- const char *name;
- int number;
-};
-
-static const struct bfin_reg_entry bfin_reg_info[] = {
- {"R0.L", REG_RL0},
- {"R1.L", REG_RL1},
- {"R2.L", REG_RL2},
- {"R3.L", REG_RL3},
- {"R4.L", REG_RL4},
- {"R5.L", REG_RL5},
- {"R6.L", REG_RL6},
- {"R7.L", REG_RL7},
- {"R0.H", REG_RH0},
- {"R1.H", REG_RH1},
- {"R2.H", REG_RH2},
- {"R3.H", REG_RH3},
- {"R4.H", REG_RH4},
- {"R5.H", REG_RH5},
- {"R6.H", REG_RH6},
- {"R7.H", REG_RH7},
- {"R0", REG_R0},
- {"R1", REG_R1},
- {"R2", REG_R2},
- {"R3", REG_R3},
- {"R4", REG_R4},
- {"R5", REG_R5},
- {"R6", REG_R6},
- {"R7", REG_R7},
- {"P0", REG_P0},
- {"P0.H", REG_P0},
- {"P0.L", REG_P0},
- {"P1", REG_P1},
- {"P1.H", REG_P1},
- {"P1.L", REG_P1},
- {"P2", REG_P2},
- {"P2.H", REG_P2},
- {"P2.L", REG_P2},
- {"P3", REG_P3},
- {"P3.H", REG_P3},
- {"P3.L", REG_P3},
- {"P4", REG_P4},
- {"P4.H", REG_P4},
- {"P4.L", REG_P4},
- {"P5", REG_P5},
- {"P5.H", REG_P5},
- {"P5.L", REG_P5},
- {"SP", REG_SP},
- {"SP.L", REG_SP},
- {"SP.H", REG_SP},
- {"FP", REG_FP},
- {"FP.L", REG_FP},
- {"FP.H", REG_FP},
- {"A0x", REG_A0x},
- {"A1x", REG_A1x},
- {"A0w", REG_A0w},
- {"A1w", REG_A1w},
- {"A0.x", REG_A0x},
- {"A1.x", REG_A1x},
- {"A0.w", REG_A0w},
- {"A1.w", REG_A1w},
- {"A0", REG_A0},
- {"A0.L", REG_A0},
- {"A0.H", REG_A0},
- {"A1", REG_A1},
- {"A1.L", REG_A1},
- {"A1.H", REG_A1},
- {"I0", REG_I0},
- {"I0.L", REG_I0},
- {"I0.H", REG_I0},
- {"I1", REG_I1},
- {"I1.L", REG_I1},
- {"I1.H", REG_I1},
- {"I2", REG_I2},
- {"I2.L", REG_I2},
- {"I2.H", REG_I2},
- {"I3", REG_I3},
- {"I3.L", REG_I3},
- {"I3.H", REG_I3},
- {"M0", REG_M0},
- {"M0.H", REG_M0},
- {"M0.L", REG_M0},
- {"M1", REG_M1},
- {"M1.H", REG_M1},
- {"M1.L", REG_M1},
- {"M2", REG_M2},
- {"M2.H", REG_M2},
- {"M2.L", REG_M2},
- {"M3", REG_M3},
- {"M3.H", REG_M3},
- {"M3.L", REG_M3},
- {"B0", REG_B0},
- {"B0.H", REG_B0},
- {"B0.L", REG_B0},
- {"B1", REG_B1},
- {"B1.H", REG_B1},
- {"B1.L", REG_B1},
- {"B2", REG_B2},
- {"B2.H", REG_B2},
- {"B2.L", REG_B2},
- {"B3", REG_B3},
- {"B3.H", REG_B3},
- {"B3.L", REG_B3},
- {"L0", REG_L0},
- {"L0.H", REG_L0},
- {"L0.L", REG_L0},
- {"L1", REG_L1},
- {"L1.H", REG_L1},
- {"L1.L", REG_L1},
- {"L2", REG_L2},
- {"L2.H", REG_L2},
- {"L2.L", REG_L2},
- {"L3", REG_L3},
- {"L3.H", REG_L3},
- {"L3.L", REG_L3},
- {"AZ", S_AZ},
- {"AN", S_AN},
- {"AC0", S_AC0},
- {"AC1", S_AC1},
- {"AV0", S_AV0},
- {"AV0S", S_AV0S},
- {"AV1", S_AV1},
- {"AV1S", S_AV1S},
- {"AQ", S_AQ},
- {"V", S_V},
- {"VS", S_VS},
- {"sftreset", REG_sftreset},
- {"omode", REG_omode},
- {"excause", REG_excause},
- {"emucause", REG_emucause},
- {"idle_req", REG_idle_req},
- {"hwerrcause", REG_hwerrcause},
- {"CC", REG_CC},
- {"LC0", REG_LC0},
- {"LC1", REG_LC1},
- {"ASTAT", REG_ASTAT},
- {"RETS", REG_RETS},
- {"LT0", REG_LT0},
- {"LB0", REG_LB0},
- {"LT1", REG_LT1},
- {"LB1", REG_LB1},
- {"CYCLES", REG_CYCLES},
- {"CYCLES2", REG_CYCLES2},
- {"USP", REG_USP},
- {"SEQSTAT", REG_SEQSTAT},
- {"SYSCFG", REG_SYSCFG},
- {"RETI", REG_RETI},
- {"RETX", REG_RETX},
- {"RETN", REG_RETN},
- {"RETE", REG_RETE},
- {"EMUDAT", REG_EMUDAT},
- {0, 0}
-};
-
/* Blackfin specific function to handle FD-PIC pointer initializations. */
static void
do
{
bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC;
-
+
if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
{
input_line_pointer += 9;
static void
bfin_s_bss (int ignore ATTRIBUTE_UNUSED)
{
- register int temp;
+ int temp;
temp = get_absolute_expression ();
subseg_set (bss_section, (subsegT) temp);
};
/* Characters that are used to denote comments and line separators. */
-const char comment_chars[] = "";
+const char comment_chars[] = "#";
const char line_comment_chars[] = "#";
const char line_separator_chars[] = ";";
typedef enum bfin_cpu_type
{
BFIN_CPU_UNKNOWN,
+ BFIN_CPU_BF504,
+ BFIN_CPU_BF506,
BFIN_CPU_BF512,
BFIN_CPU_BF514,
BFIN_CPU_BF516,
BFIN_CPU_BF548M,
BFIN_CPU_BF549,
BFIN_CPU_BF549M,
- BFIN_CPU_BF561
+ BFIN_CPU_BF561,
+ BFIN_CPU_BF592,
} bfin_cpu_t;
bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
struct bfin_cpu bfin_cpus[] =
{
+ {"bf504", BFIN_CPU_BF504, 0x0000, AC_05000074},
+
+ {"bf506", BFIN_CPU_BF506, 0x0000, AC_05000074},
+
+ {"bf512", BFIN_CPU_BF512, 0x0002, AC_05000074},
{"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
{"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
+ {"bf514", BFIN_CPU_BF514, 0x0002, AC_05000074},
{"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
{"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
+ {"bf516", BFIN_CPU_BF516, 0x0002, AC_05000074},
{"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
{"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
+ {"bf518", BFIN_CPU_BF518, 0x0002, AC_05000074},
{"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
{"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
{"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
+ {"bf542", BFIN_CPU_BF542, 0x0004, AC_05000074},
{"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
{"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
{"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
{"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
+ {"bf544", BFIN_CPU_BF544, 0x0004, AC_05000074},
{"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
{"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
{"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
{"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
+ {"bf547", BFIN_CPU_BF547, 0x0004, AC_05000074},
{"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
{"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
{"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
{"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
+ {"bf548", BFIN_CPU_BF548, 0x0004, AC_05000074},
{"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
{"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
{"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
{"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
+ {"bf549", BFIN_CPU_BF549, 0x0004, AC_05000074},
{"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
{"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
{"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
{"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
{"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
- {NULL, 0, 0, 0}
+ {"bf592", BFIN_CPU_BF592, 0x0001, AC_05000074},
+ {"bf592", BFIN_CPU_BF592, 0x0000, AC_05000074},
};
/* Define bfin-specific command-line options (there are none). */
int
-md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED)
{
switch (c)
{
case OPTION_MCPU:
{
- const char *p, *q;
- int i;
+ const char *q;
+ unsigned int i;
- i = 0;
- while ((p = bfin_cpus[i].name) != NULL)
+ for (i = 0; i < ARRAY_SIZE (bfin_cpus); i++)
{
+ const char *p = bfin_cpus[i].name;
if (strncmp (arg, p, strlen (p)) == 0)
break;
- i++;
}
- if (p == NULL)
- {
- error ("-mcpu=%s is not valid", arg);
- return 0;
- }
+ if (i == ARRAY_SIZE (bfin_cpus))
+ as_fatal ("-mcpu=%s is not valid", arg);
bfin_cpu_type = bfin_cpus[i].type;
- q = arg + strlen (p);
+ q = arg + strlen (bfin_cpus[i].name);
if (*q == '\0')
{
else if (strcmp (q, "-any") == 0)
{
bfin_si_revision = 0xffff;
- while (bfin_cpus[i].type == bfin_cpu_type)
+ while (i < ARRAY_SIZE (bfin_cpus)
+ && bfin_cpus[i].type == bfin_cpu_type)
{
bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
i++;
|| si_major > 0xff || si_minor > 0xff)
{
invalid_silicon_revision:
- error ("-mcpu=%s has invalid silicon revision", arg);
- return 0;
+ as_fatal ("-mcpu=%s has invalid silicon revision", arg);
}
bfin_si_revision = (si_major << 8) | si_minor;
- while (bfin_cpus[i].type == bfin_cpu_type
+ while (i < ARRAY_SIZE (bfin_cpus)
+ && bfin_cpus[i].type == bfin_cpu_type
&& bfin_cpus[i].si_revision != bfin_si_revision)
i++;
- if (bfin_cpus[i].type != bfin_cpu_type)
+ if (i == ARRAY_SIZE (bfin_cpus)
+ || bfin_cpus[i].type != bfin_cpu_type)
goto invalid_silicon_revision;
bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
}
void
-md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+md_show_usage (FILE * stream)
{
- fprintf (stream, _(" BFIN specific command line options:\n"));
+ fprintf (stream, _(" Blackfin specific assembler options:\n"));
+ fprintf (stream, _(" -mcpu=<cpu[-sirevision]> specify the name of the target CPU\n"));
+ fprintf (stream, _(" -mfdpic assemble for the FDPIC ABI\n"));
+ fprintf (stream, _(" -mno-fdpic/-mnopic disable -mfdpic\n"));
}
/* Perform machine-specific initializations. */
void
-md_begin ()
+md_begin (void)
{
/* Set the ELF flags if desired. */
if (bfin_flags)
/* Ensure that lines can begin with '(', for multiple
register stack pops. */
lex_type ['('] = LEX_BEGIN_NAME;
-
+
#ifdef OBJ_ELF
record_alignment (text_section, 2);
record_alignment (data_section, 2);
#ifdef DEBUG
extern int debug_codeselection;
debug_codeselection = 1;
-#endif
+#endif
last_insn_size = 0;
}
md_assemble (char *line)
{
char *toP = 0;
- extern char *current_inputline;
int size, insn_size;
struct bfin_insn *tmp_insn;
size_t len;
static size_t buffer_len = 0;
+ static char *current_inputline;
parse_state state;
len = strlen (line);
if (len + 2 > buffer_len)
{
- if (buffer_len > 0)
- free (current_inputline);
buffer_len = len + 40;
- current_inputline = xmalloc (buffer_len);
+ current_inputline = XRESIZEVEC (char, current_inputline, buffer_len);
}
memcpy (current_inputline, line, len);
current_inputline[len] = ';';
#ifdef OBJ_ELF
dwarf2_emit_insn (insn_size);
#endif
+
+ while (*line++ != '\0')
+ if (*line == '\n')
+ bump_line_counters ();
}
/* Parse one line of instructions, and generate opcode for it.
/* Round up a section size to the appropriate boundary. */
valueT
-md_section_align (segment, size)
- segT segment;
- valueT size;
+md_section_align (segT segment, valueT size)
{
- int boundary = bfd_get_section_alignment (stdoutput, segment);
- return ((size + (1 << boundary) - 1) & (-1 << boundary));
+ int boundary = bfd_section_alignment (segment);
+ return ((size + (1 << boundary) - 1) & -(1 << boundary));
}
-char *
+const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
then it is done here. */
arelent *
-tc_gen_reloc (seg, fixp)
- asection *seg ATTRIBUTE_UNUSED;
- fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
{
arelent *reloc;
- reloc = (arelent *) xmalloc (sizeof (arelent));
- reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ reloc = XNEW (arelent);
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
given a PC relative reloc. */
long
-md_pcrel_from_section (fixP, sec)
- fixS *fixP;
- segT sec;
+md_pcrel_from_section (fixS *fixP, segT sec)
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (!S_IS_DEFINED (fixP->fx_addsy)
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
-bfd_boolean
+bfd_boolean
bfin_fix_adjustable (fixS *fixP)
-{
+{
switch (fixP->fx_r_type)
- {
+ {
/* Adjust_reloc_syms doesn't know about the GOT. */
case BFD_RELOC_BFIN_GOT:
- case BFD_RELOC_BFIN_GOT17M4:
- case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
case BFD_RELOC_BFIN_PLTPC:
/* We need the symbol name for the VTABLE entries. */
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
return 0;
-
+
default:
return 1;
- }
-}
-
-
-/* Handle the LOOP_BEGIN and LOOP_END statements.
- Parse the Loop_Begin/Loop_End and create a label. */
-void
-bfin_start_line_hook ()
-{
- bfd_boolean maybe_begin = FALSE;
- bfd_boolean maybe_end = FALSE;
-
- char *c1, *label_name;
- symbolS *line_label;
- char *c = input_line_pointer;
- int cr_num = 0;
-
- while (ISSPACE (*c))
- {
- if (*c == '\n')
- cr_num++;
- c++;
- }
-
- /* Look for Loop_Begin or Loop_End statements. */
-
- if (*c != 'L' && *c != 'l')
- return;
-
- c++;
- if (*c != 'O' && *c != 'o')
- return;
-
- c++;
- if (*c != 'O' && *c != 'o')
- return;
-
- c++;
- if (*c != 'P' && *c != 'p')
- return;
-
- c++;
- if (*c != '_')
- return;
-
- c++;
- if (*c == 'E' || *c == 'e')
- maybe_end = TRUE;
- else if (*c == 'B' || *c == 'b')
- maybe_begin = TRUE;
- else
- return;
-
- if (maybe_end)
- {
- c++;
- if (*c != 'N' && *c != 'n')
- return;
-
- c++;
- if (*c != 'D' && *c != 'd')
- return;
- }
-
- if (maybe_begin)
- {
- c++;
- if (*c != 'E' && *c != 'e')
- return;
-
- c++;
- if (*c != 'G' && *c != 'g')
- return;
-
- c++;
- if (*c != 'I' && *c != 'i')
- return;
-
- c++;
- if (*c != 'N' && *c != 'n')
- return;
- }
-
- c++;
- while (ISSPACE (*c)) c++;
- c1 = c;
- while (ISALPHA (*c) || ISDIGIT (*c) || *c == '_') c++;
-
- if (input_line_pointer[-1] == '\n')
- bump_line_counters ();
-
- while (cr_num--)
- bump_line_counters ();
-
- input_line_pointer = c;
- if (maybe_end)
- {
- label_name = (char *) xmalloc ((c - c1) + strlen ("__END") + 5);
- label_name[0] = 0;
- strcat (label_name, "L$L$");
- strncat (label_name, c1, c-c1);
- strcat (label_name, "__END");
- }
- else /* maybe_begin. */
- {
- label_name = (char *) xmalloc ((c - c1) + strlen ("__BEGIN") + 5);
- label_name[0] = 0;
- strcat (label_name, "L$L$");
- strncat (label_name, c1, c-c1);
- strcat (label_name, "__BEGIN");
}
-
- line_label = colon (label_name);
-
- /* Loop_End follows the last instruction in the loop.
- Adjust label address. */
- if (maybe_end)
- ((struct local_symbol *) line_label)->lsy_value -= last_insn_size;
}
/* Special extra functions that help bfin-parse.y perform its job. */
INSTR_T
gencode (unsigned long x)
{
- INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn));
+ INSTR_T cell = XOBNEW (&mempool, struct bfin_insn);
memset (cell, 0, sizeof (struct bfin_insn));
cell->value = (x);
return cell;
int count_insns;
static void *
-allocate (int n)
+allocate (size_t n)
{
return obstack_alloc (&mempool, n);
}
INSTR_T
Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
{
- /* Top level reloction expression generator VDSP style.
+ /* Top level relocation expression generator VDSP style.
If the relocation is just by itself, generate one item
else generate this convoluted expression. */
INSTR_T note = NULL_CODE;
INSTR_T note1 = NULL_CODE;
- int pcrel = 1; /* Is the parent reloc pcrelative?
+ int pcrel = 1; /* Is the parent reloc pc-relative?
This calculation here and HOWTO should match. */
if (parent_reloc)
#define INIT(t) t c_code = init_##t
#define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
+#define ASSIGNF(x,f) c_code.opcode |= ((x & c_code.mask_##f)<<c_code.bits_##f)
#define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
#define HI(x) ((x >> 16) & 0xffff)
{
int val;
int high_val;
- int reloc = 0;
+ int rel = 0;
INIT (CALLa);
switch(S){
- case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
- case 1 : reloc = BFD_RELOC_24_PCREL; break;
- case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
+ case 0 : rel = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
+ case 1 : rel = BFD_RELOC_24_PCREL; break;
+ case 2 : rel = BFD_RELOC_BFIN_PLTPC; break;
default : break;
}
high_val = val >> 16;
return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
- Expr_Node_Gen_Reloc (addr, reloc));
+ Expr_Node_Gen_Reloc (addr, rel));
}
INSTR_T
/* Load and Store. */
INSTR_T
-bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc)
+bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int rel)
{
int grp, hword;
unsigned val = EXPR_VALUE (phword);
ASSIGN_R (reg);
grp = (GROUP (reg));
ASSIGN (grp);
- if (reloc == 2)
+ if (rel == 2)
{
return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
}
- else if (reloc == 1)
+ else if (rel == 1)
{
return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
}
}
INSTR_T
-bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op)
+bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int opc)
{
int offset;
int value = 0;
INIT (LDSTii);
-
if (!IS_PREG (*ptr))
{
fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
return 0;
}
- switch (op)
+ switch (opc)
{
case 1:
case 2:
offset = value;
ASSIGN (offset);
ASSIGN (W);
- ASSIGN (op);
+ ASSIGNF (opc, op);
return GEN_OPCODE16 ();
}
}
INSTR_T
-bfin_gen_compi2opd (REG_T dst, int src, int op)
+bfin_gen_compi2opd (REG_T dst, int src, int opc)
{
INIT (COMPI2opD);
ASSIGN_R (dst);
ASSIGN (src);
- ASSIGN (op);
+ ASSIGNF (opc, op);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_compi2opp (REG_T dst, int src, int op)
+bfin_gen_compi2opp (REG_T dst, int src, int opc)
{
INIT (COMPI2opP);
ASSIGN_R (dst);
ASSIGN (src);
- ASSIGN (op);
+ ASSIGNF (opc, op);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_dagmodik (REG_T i, int op)
+bfin_gen_dagmodik (REG_T i, int opc)
{
INIT (DagMODik);
ASSIGN_R (i);
- ASSIGN (op);
+ ASSIGNF (opc, op);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
+bfin_gen_dagmodim (REG_T i, REG_T m, int opc, int br)
{
INIT (DagMODim);
ASSIGN_R (i);
ASSIGN_R (m);
- ASSIGN (op);
+ ASSIGNF (opc, op);
ASSIGN (br);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_cc2stat (int cbit, int op, int D)
+bfin_gen_cc2stat (int cbit, int opc, int D)
{
INIT (CC2stat);
ASSIGN (cbit);
- ASSIGN (op);
+ ASSIGNF (opc, op);
ASSIGN (D);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_cc2dreg (int op, REG_T reg)
+bfin_gen_cc2dreg (int opc, REG_T reg)
{
INIT (CC2dreg);
- ASSIGN (op);
+ ASSIGNF (opc, op);
ASSIGN_R (reg);
return GEN_OPCODE16 ();
}
INSTR_T
-bfin_gen_cactrl (REG_T reg, int a, int op)
+bfin_gen_cactrl (REG_T reg, int a, int opc)
{
INIT (CaCTRL);
ASSIGN_R (reg);
ASSIGN (a);
- ASSIGN (op);
+ ASSIGNF (opc, op);
return GEN_OPCODE16 ();
}
INSTR_T
bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
{
+ int grp;
INIT (PseudoDbg_Assert);
ASSIGN (dbgop);
ASSIGN_R (regtest);
+ grp = GROUP (regtest);
+ ASSIGN (grp);
ASSIGN (expected);
return GEN_OPCODE32 ();
}
+INSTR_T
+bfin_gen_pseudochr (int ch)
+{
+ INIT (PseudoChr);
+
+ ASSIGN (ch);
+
+ return GEN_OPCODE16 ();
+}
+
/* Multiple instruction generation. */
INSTR_T
}
INSTR_T
-bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
+bfin_gen_loop (Expr_Node *exp, REG_T reg, int rop, REG_T preg)
{
const char *loopsym;
char *lbeginsym, *lendsym;
Expr_Node_Value lbeginval, lendval;
Expr_Node *lbegin, *lend;
+ symbolS *sym;
- loopsym = expr->value.s_value;
+ loopsym = exp->value.s_value;
lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5);
lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5);
lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
lend = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
- symbol_remove (symbol_find (loopsym), &symbol_rootP, &symbol_lastP);
+ sym = symbol_find(loopsym);
+ if (!S_IS_LOCAL (sym) || (S_IS_LOCAL (sym) && !symbol_used_p (sym)))
+ symbol_remove (sym, &symbol_rootP, &symbol_lastP);
+
+ return bfin_gen_loopsetup (lbegin, reg, rop, lend, preg);
+}
+
+void
+bfin_loop_attempt_create_label (Expr_Node *exp, int is_begin)
+{
+ char *name;
+ name = fb_label_name (exp->value.i_value, is_begin);
+ exp->value.s_value = xstrdup (name);
+ exp->type = Expr_Node_Reloc;
+}
+
+void
+bfin_loop_beginend (Expr_Node *exp, int begin)
+{
+ const char *loopsym;
+ char *label_name;
+ symbolS *linelabel;
+ const char *suffix = begin ? "__BEGIN" : "__END";
+
+ loopsym = exp->value.s_value;
+ label_name = (char *) xmalloc (strlen (loopsym) + strlen (suffix) + 5);
- return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
+ label_name[0] = 0;
+
+ strcat (label_name, "L$L$");
+ strcat (label_name, loopsym);
+ strcat (label_name, suffix);
+
+ linelabel = colon (label_name);
+
+ /* LOOP_END follows the last instruction in the loop.
+ Adjust label address. */
+ if (!begin)
+ *symbol_X_add_number (linelabel) -= last_insn_size;
}
bfd_boolean
}
bfd_boolean
-bfin_start_label (char *s, char *ptr)
+bfin_start_label (char *s)
{
- while (s != ptr)
+ while (*s != 0)
{
if (*s == '(' || *s == '[')
return FALSE;
}
return TRUE;
-}
+}
int
bfin_force_relocation (struct fix *fixp)
| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
- int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
+ int opc = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
- if (op == 0 || op == 1)
+ if (opc == 0 || opc == 1)
return IREG_MASK (i);
else
return 0;
| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
- int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
+ int opc = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
- if (W == 0 && op != 3)
+ if (W == 0 && opc != 3)
return DREG_MASK (reg);
- else if (W == 0 && op == 3)
+ else if (W == 0 && opc == 3)
return 0;
- else if (W == 1 && op == 0)
+ else if (W == 1 && opc == 0)
return 0;
- else if (W == 1 && op == 1)
+ else if (W == 1 && opc == 1)
return 0;
- else if (W == 1 && op == 3)
+ else if (W == 1 && opc == 3)
return 0;
abort ();
else if (aop == 0 && aopcde == 24)
return DREG_MASK (dst0);
- else if (aop == 1 && aopcde == 24)
+ else if (aop == 1 && aopcde == 24)
return DREG_MASK (dst0) | DREG_MASK (dst1);
else if (aopcde == 13)
return DREG_MASK (dst0) | DREG_MASK (dst1);
projects / deliverable / binutils-gdb.git / blobdiff