/* tc-cr16.c -- Assembler code for the CR16 CPU core.
- Copyright (C) 2007-2017 Free Software Foundation, Inc.
+ Copyright (C) 2007-2020 Free Software Foundation, Inc.
Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
if ((width = exp.X_add_number) >
(unsigned int)(BITS_PER_CHAR * nbytes))
{
- as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
+ as_warn (ngettext ("field width %lu too big to fit in %d"
+ " byte: truncated to %d bits",
+ "field width %lu too big to fit in %d"
+ " bytes: truncated to %d bits",
+ nbytes),
+ width, nbytes, (BITS_PER_CHAR * nbytes));
width = BITS_PER_CHAR * nbytes;
} /* Too big. */
{
/* 'opcode' points to the start of the instruction, whether
we need to change the instruction's fixed encoding. */
- char *opcode = fragP->fr_literal + fragP->fr_fix;
+ char *opcode = &fragP->fr_literal[0] + fragP->fr_fix;
bfd_reloc_code_real_type reloc;
subseg_change (sec, 0);
/* Issue a error message when register is illegal. */
#define IMAGE_ERR \
as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
- reg_name, ins_parse); \
- break;
+ reg_name, ins_parse);
switch (rreg->type)
{
return rreg->image;
else
IMAGE_ERR;
+ break;
case CR16_P_REGTYPE:
return rreg->image;
default:
IMAGE_ERR;
+ break;
}
return 0;
match = 1;
break;
-/* Try again with next instruction. */
-next_insn:
+ /* Try again with next instruction. */
+ next_insn:
instruction++;
}
if (streq ("cinv", op))
{
/* Validate the cinv options. */
+ unsigned int op_len, param_len;
check_cinv_options (param);
- strcat (op, param);
+ op_len = strlen (op);
+ param_len = strlen (param) + 1;
+ memmove (op + op_len, param, param_len);
}
/* MAPPING - SHIFT INSN, if imm4/imm16 positive values