/* tc-cr16.c -- Assembler code for the CR16 CPU core.
- Copyright 2007, 2008, 2009, 2010, 2011
- Free Software Foundation, Inc.
+ Copyright (C) 2007-2020 Free Software Foundation, Inc.
Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
if ((width = exp.X_add_number) >
(unsigned int)(BITS_PER_CHAR * nbytes))
{
- as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
+ as_warn (ngettext ("field width %lu too big to fit in %d"
+ " byte: truncated to %d bits",
+ "field width %lu too big to fit in %d"
+ " bytes: truncated to %d bits",
+ nbytes),
+ width, nbytes, (BITS_PER_CHAR * nbytes));
width = BITS_PER_CHAR * nbytes;
} /* Too big. */
return;
}
- value |= ((~(-1 << width) & exp.X_add_number)
+ value |= ((~(-(1 << width)) & exp.X_add_number)
<< ((BITS_PER_CHAR * nbytes) - bits_available));
if ((bits_available -= width) == 0
const reg_entry *rreg;
char tmp_rp[16]="\0";
- /* Add '(' and ')' to the reg pair, if its not present. */
- if (reg_name[0] != '(')
+ /* Add '(' and ')' to the reg pair, if it's not present. */
+ if (reg_name[0] != '(')
{
tmp_rp[0] = '(';
strcat (tmp_rp, reg_name);
return rreg->value.reg_val;
return nullregister;
-}
+}
/* Get the index register 'reg_name'. */
/* Record a fixup for a cons expression. */
void
-cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp)
+cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp,
+ bfd_reloc_code_real_type rtype)
{
- int rtype = BFD_RELOC_UNUSED;
-
switch (len)
{
default: rtype = BFD_RELOC_NONE; break;
arelent * reloc;
/* If symbols are local and resolved, then no relocation needed. */
- if ( ((fixP->fx_addsy)
+ if ( ((fixP->fx_addsy)
&& (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section))
- || ((fixP->fx_subsy)
+ || ((fixP->fx_subsy)
&& (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)))
return NULL;
- reloc = xmalloc (sizeof (arelent));
- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc = XNEW (arelent);
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
reloc->addend = fixP->fx_offset;
{
/* 'opcode' points to the start of the instruction, whether
we need to change the instruction's fixed encoding. */
- char *opcode = fragP->fr_literal + fragP->fr_fix;
+ char *opcode = &fragP->fr_literal[0] + fragP->fr_fix;
bfd_reloc_code_real_type reloc;
subseg_change (sec, 0);
GAS does not understand. */
int
-md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED)
{
return 0;
}
return;
}
-char *
+const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, target_big_endian);
else if (strneq (input_line_pointer, "@GOT", 4)
|| strneq (input_line_pointer, "@got", 4))
{
- if ((strneq (input_line_pointer, "+", 1))
+ if ((strneq (input_line_pointer, "+", 1))
|| (strneq (input_line_pointer, "-", 1)))
as_warn (_("GOT bad expression with %s."), input_line_pointer);
/* Issue a error message when register is illegal. */
#define IMAGE_ERR \
as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
- reg_name, ins_parse); \
- break;
+ reg_name, ins_parse);
switch (rreg->type)
{
return rreg->image;
else
IMAGE_ERR;
+ break;
case CR16_P_REGTYPE:
return rreg->image;
default:
IMAGE_ERR;
+ break;
}
return 0;
static void
set_operand (char *operand, ins * cr16_ins)
{
- char *operandS; /* Pointer to start of sub-opearand. */
- char *operandE; /* Pointer to end of sub-opearand. */
+ char *operandS; /* Pointer to start of sub-operand. */
+ char *operandE; /* Pointer to end of sub-operand. */
argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */
{
case arg_ic: /* Case $0x18. */
operandS++;
+ /* Fall through. */
case arg_c: /* Case 0x18. */
/* Set constant. */
process_label_constant (operandS, cr16_ins);
*operandE = '\0';
process_label_constant (operandS, cr16_ins);
operandS = operandE;
+ /* Fall through. */
case arg_rbase: /* Case (r1) or (r1,r0). */
operandS++;
/* Set register base. */
if (strcasecmp (trap->name, s) == 0)
return trap->entry;
- /* To make compatable with CR16 4.1 tools, the below 3-lines of
+ /* To make compatible with CR16 4.1 tools, the below 3-lines of
* code added. Refer: Development Tracker item #123 */
for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
if (trap->entry == (unsigned int) atoi (s))
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
break;
case 21:
- if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20;
+ if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS)))
+ nbits = 20;
+ /* Fall through. */
case 24:
case 22:
case 20:
/* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
- will be overriden.
+ will be overridden.
0 1 2 3
+---------+---------+---------+---------+
| 'match' | | X X X X | |
check_range (long *num, int bits, int unsigned flags, int update)
{
long min, max;
- int retval = OP_LEGAL;
+ op_err retval = OP_LEGAL;
long value = *num;
if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
- /* For hosts witah longs bigger than 32-bits make sure that the top
+ /* For hosts with longs bigger than 32-bits make sure that the top
bits of a 32-bit negative value read in by the parser are set,
so that the correct comparisons are made. */
if (value & 0x80000000)
- value |= (-1L << 31);
+ value |= (-1UL << 31);
/* Verify operand value is even. */
return retval;
}
-/* Bunch of error checkings.
+/* Bunch of error checking.
The checks are made after a matching instruction was found. */
static void
{
unsigned int count = insn->arg[0].constant, reg_val;
- /* Check if count operand caused to save/retrive the RA twice
+ /* Check if count operand caused to save/retrieve the RA twice
to generate warning message. */
if (insn->nargs > 2)
{
Returns 1 upon success, 0 upon failure. */
static int
-assemble_insn (char *mnemonic, ins *insn)
+assemble_insn (const char *mnemonic, ins *insn)
{
/* Type of each operand in the current template. */
argtype cur_type[MAX_OPERANDS];
goto next_insn;
/* If 'storb' instruction with 'sp' reg and 16-bit disp of
- * reg-pair, leads to undifined trap, so this should use
+ * reg-pair, leads to undefined trap, so this should use
* 20-bit disp of reg-pair. */
if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
&& (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
match = 1;
break;
-/* Try again with next instruction. */
-next_insn:
+ /* Try again with next instruction. */
+ next_insn:
instruction++;
}
else
/* Full match - print the encoding to output file. */
{
- /* Make further checkings (such that couldn't be made earlier).
+ /* Make further checking (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
for (i = 0; i < insn->nargs; i++)
{
- /* For BAL (ra),disp17 instuction only. And also set the
+ /* For BAL (ra),disp17 instruction only. And also set the
DISP24a relocation type. */
if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
{
int size;
reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
-
+
if (!reloc_howto)
abort ();
}
}
+/* Actually assemble an instruction. */
+
+static void
+cr16_assemble (const char *op, char *param)
+{
+ ins cr16_ins;
+
+ /* Find the instruction. */
+ instruction = (const inst *) hash_find (cr16_inst_hash, op);
+ if (instruction == NULL)
+ {
+ as_bad (_("Unknown opcode: `%s'"), op);
+ return;
+ }
+
+ /* Tie dwarf2 debug info to the address at the start of the insn. */
+ dwarf2_emit_insn (0);
+
+ /* Parse the instruction's operands. */
+ parse_insn (&cr16_ins, param);
+
+ /* Assemble the instruction - return upon failure. */
+ if (assemble_insn (op, &cr16_ins) == 0)
+ return;
+
+ /* Print the instruction. */
+ print_insn (&cr16_ins);
+}
+
/* This is the guts of the machine-dependent assembler. OP points to a
machine dependent instruction. This function is supposed to emit
the frags/bytes it assembles to. */
;
*param++ = '\0';
- /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */
+ /* bCC instructions and adjust the mnemonic by adding extra white spaces. */
if (is_bcc_insn (op))
{
strcpy (param1, get_b_cc (op));
- op = "b";
strcat (param1,",");
strcat (param1, param);
param = (char *) ¶m1;
+ cr16_assemble ("b", param);
+ return;
}
/* Checking the cinv options and adjust the mnemonic by removing the
if (streq ("cinv", op))
{
/* Validate the cinv options. */
+ unsigned int op_len, param_len;
check_cinv_options (param);
- strcat (op, param);
+ op_len = strlen (op);
+ param_len = strlen (param) + 1;
+ memmove (op + op_len, param, param_len);
}
/* MAPPING - SHIFT INSN, if imm4/imm16 positive values
lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
- as CR16 core doesn't support lsh[b/w] right shift operaions. */
+ as CR16 core doesn't support lsh[b/w] right shift operations. */
if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
&& (param [0] == '$'))
{
&& ((&cr16_ins)->arg[0].constant >= 0))
{
if (streq ("lshb", op))
- op = "ashub";
+ cr16_assemble ("ashub", param);
else if (streq ("lshd", op))
- op = "ashud";
+ cr16_assemble ("ashud", param);
else
- op = "ashuw";
+ cr16_assemble ("ashuw", param);
+ return;
}
}
- /* Find the instruction. */
- instruction = (const inst *) hash_find (cr16_inst_hash, op);
- if (instruction == NULL)
- {
- as_bad (_("Unknown opcode: `%s'"), op);
- return;
- }
-
- /* Tie dwarf2 debug info to the address at the start of the insn. */
- dwarf2_emit_insn (0);
-
- /* Parse the instruction's operands. */
- parse_insn (&cr16_ins, param);
-
- /* Assemble the instruction - return upon failure. */
- if (assemble_insn (op, &cr16_ins) == 0)
- return;
-
- /* Print the instruction. */
- print_insn (&cr16_ins);
+ cr16_assemble (op, param);
}
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