/* i386.c -- Assemble code for the Intel 80386
- Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
/* Intel 80386 machine specific gas.
Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
x86_64 support by Jan Hubicka (jh@suse.cz)
+ VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
Bugs & suggestions are completely welcome. This is free software.
Please help us make it better. */
-#include <ctype.h>
-
#include "as.h"
+#include "safe-ctype.h"
#include "subsegs.h"
#include "dwarf2dbg.h"
+#include "dw2gencfi.h"
#include "opcode/i386.h"
+#include "elf/x86-64.h"
#ifndef REGISTER_WARNINGS
#define REGISTER_WARNINGS 1
#define SCALE1_WHEN_NO_INDEX 1
#endif
-#define true 1
-#define false 0
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "i386"
+#endif
+
+#ifndef INLINE
+#if __GNUC__ >= 2
+#define INLINE __inline__
+#else
+#define INLINE
+#endif
+#endif
-static unsigned int mode_from_disp_size PARAMS ((unsigned int));
-static int fits_in_signed_byte PARAMS ((offsetT));
-static int fits_in_unsigned_byte PARAMS ((offsetT));
-static int fits_in_unsigned_word PARAMS ((offsetT));
-static int fits_in_signed_word PARAMS ((offsetT));
-static int fits_in_unsigned_long PARAMS ((offsetT));
-static int fits_in_signed_long PARAMS ((offsetT));
+static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
+static INLINE int fits_in_signed_byte PARAMS ((offsetT));
+static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
+static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
+static INLINE int fits_in_signed_word PARAMS ((offsetT));
+static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
+static INLINE int fits_in_signed_long PARAMS ((offsetT));
static int smallest_imm_type PARAMS ((offsetT));
static offsetT offset_in_range PARAMS ((offsetT, int));
static int add_prefix PARAMS ((unsigned int));
static void set_16bit_gcc_code_flag PARAMS ((int));
static void set_intel_syntax PARAMS ((int));
static void set_cpu_arch PARAMS ((int));
-
-#ifdef BFD_ASSEMBLER
-static bfd_reloc_code_real_type reloc
- PARAMS ((int, int, int, bfd_reloc_code_real_type));
+#ifdef TE_PE
+static void pe_directive_secrel PARAMS ((int));
#endif
-
-#ifndef DEFAULT_ARCH
-#define DEFAULT_ARCH "i386"
+static char *output_invalid PARAMS ((int c));
+static int i386_operand PARAMS ((char *operand_string));
+static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
+static const reg_entry *parse_register PARAMS ((char *reg_string,
+ char **end_op));
+static char *parse_insn PARAMS ((char *, char *));
+static char *parse_operands PARAMS ((char *, const char *));
+static void swap_operands PARAMS ((void));
+static void optimize_imm PARAMS ((void));
+static void optimize_disp PARAMS ((void));
+static int match_template PARAMS ((void));
+static int check_string PARAMS ((void));
+static int process_suffix PARAMS ((void));
+static int check_byte_reg PARAMS ((void));
+static int check_long_reg PARAMS ((void));
+static int check_qword_reg PARAMS ((void));
+static int check_word_reg PARAMS ((void));
+static int finalize_imm PARAMS ((void));
+static int process_operands PARAMS ((void));
+static const seg_entry *build_modrm_byte PARAMS ((void));
+static void output_insn PARAMS ((void));
+static void output_branch PARAMS ((void));
+static void output_jump PARAMS ((void));
+static void output_interseg_jump PARAMS ((void));
+static void output_imm PARAMS ((fragS *insn_start_frag,
+ offsetT insn_start_off));
+static void output_disp PARAMS ((fragS *insn_start_frag,
+ offsetT insn_start_off));
+#ifndef I386COFF
+static void s_bss PARAMS ((int));
#endif
-static char *default_arch = DEFAULT_ARCH;
+
+static const char *default_arch = DEFAULT_ARCH;
/* 'md_assemble ()' gathers together information and puts it into a
i386_insn. */
#define Operand_PCrel 1
/* Relocation type for operand */
-#ifdef BFD_ASSEMBLER
- enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
-#else
- int disp_reloc[MAX_OPERANDS];
-#endif
+ enum bfd_reloc_code_real reloc[MAX_OPERANDS];
/* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
the base index byte below. */
/* List of chars besides those in app.c:symbol_chars that can start an
operand. Used to prevent the scrubber eating vital white-space. */
+const char extra_symbol_chars[] = "*%-(["
#ifdef LEX_AT
-const char extra_symbol_chars[] = "*%-(@";
-#else
-const char extra_symbol_chars[] = "*%-(";
+ "@"
+#endif
+#ifdef LEX_QM
+ "?"
#endif
+ ;
+#if (defined (TE_I386AIX) \
+ || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
+ && !defined (TE_LINUX) \
+ && !defined (TE_NETWARE) \
+ && !defined (TE_FreeBSD) \
+ && !defined (TE_NetBSD)))
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
-#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
-/* Putting '/' here makes it impossible to use the divide operator.
- However, we need it for compatibility with SVR4 systems. */
const char comment_chars[] = "#/";
#define PREFIX_SEPARATOR '\\'
-#else
-const char comment_chars[] = "#";
-#define PREFIX_SEPARATOR '/'
-#endif
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
#NO_APP at the beginning of its output.
Also note that comments started like this one will always work if
'/' isn't otherwise defined. */
-#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
-const char line_comment_chars[] = "";
+const char line_comment_chars[] = "#";
+
#else
-const char line_comment_chars[] = "/";
+/* Putting '/' here makes it impossible to use the divide operator.
+ However, we need it for compatibility with SVR4 systems. */
+const char comment_chars[] = "#";
+#define PREFIX_SEPARATOR '/'
+
+const char line_comment_chars[] = "/#";
#endif
const char line_separator_chars[] = ";";
#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
#define is_digit_char(x) (digit_chars[(unsigned char) x])
-/* All non-digit non-letter charcters that may occur in an operand. */
+/* All non-digit non-letter characters that may occur in an operand. */
static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
/* md_assemble() always leaves the strings it's passed unaltered. To
CODE_32BIT,
CODE_16BIT,
CODE_64BIT };
+#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
static enum flag_code flag_code;
static int use_rela_relocations = 0;
frame as in 32 bit mode. */
static char stackop_size = '\0';
+/* Non-zero to optimize code alignment. */
+int optimize_align_code = 1;
+
/* Non-zero to quieten some warnings. */
static int quiet_warnings = 0;
/* CPU name. */
static const char *cpu_arch_name = NULL;
+static const char *cpu_sub_arch_name = NULL;
/* CPU feature flags. */
-static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
+static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
/* If set, conditional jumps are not automatically promoted to handle
larger than a byte offset. */
static unsigned int no_cond_jump_promotion = 0;
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
+static symbolS *GOT_symbol;
+
+/* The dwarf2 return column, adjusted for 32 or 64 bit. */
+unsigned int x86_dwarf2_return_column;
+
+/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
+int x86_cie_data_alignment;
+
/* Interface to relax_segment.
There are 3 major relax states for 386 jump insns because the
different types of jumps add different sizes to frags when we're
figuring out what sort of jump to choose to reach a given label. */
/* Types. */
-#define UNCOND_JUMP 1
-#define COND_JUMP 2
-#define COND_JUMP86 3
+#define UNCOND_JUMP 0
+#define COND_JUMP 1
+#define COND_JUMP86 2
/* Sizes. */
#define CODE16 1
#define SMALL 0
-#define SMALL16 (SMALL|CODE16)
+#define SMALL16 (SMALL | CODE16)
#define BIG 2
-#define BIG16 (BIG|CODE16)
+#define BIG16 (BIG | CODE16)
#ifndef INLINE
#ifdef __GNUC__
/* The fields are:
1) most positive reach of this state,
2) most negative reach of this state,
- 3) how many bytes this mode will add to the size of the current frag
+ 3) how many bytes this mode will have in the variable part of the frag
4) which index into the table to try if we can't fit into this one. */
- {1, 1, 0, 0},
- {1, 1, 0, 0},
- {1, 1, 0, 0},
- {1, 1, 0, 0},
/* UNCOND_JUMP states. */
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
- /* dword jmp adds 3 bytes to frag:
- 0 extra opcode bytes, 3 extra displacement bytes. */
- {0, 0, 3, 0},
- /* word jmp adds 1 byte to frag:
- 0 extra opcode bytes, 1 extra displacement byte. */
- {0, 0, 1, 0},
-
- /* COND_JUMP states. */
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
- /* dword conditionals adds 4 bytes to frag:
- 1 extra opcode byte, 3 extra displacement bytes. */
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
+ /* dword jmp adds 4 bytes to frag:
+ 0 extra opcode bytes, 4 displacement bytes. */
{0, 0, 4, 0},
- /* word conditionals add 2 bytes to frag:
- 1 extra opcode byte, 1 extra displacement byte. */
+ /* word jmp adds 2 byte2 to frag:
+ 0 extra opcode bytes, 2 displacement bytes. */
{0, 0, 2, 0},
- /* COND_JUMP86 states. */
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
- {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
- /* dword conditionals adds 4 bytes to frag:
- 1 extra opcode byte, 3 extra displacement bytes. */
- {0, 0, 4, 0},
+ /* COND_JUMP states. */
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
+ /* dword conditionals adds 5 bytes to frag:
+ 1 extra opcode byte, 4 displacement bytes. */
+ {0, 0, 5, 0},
/* word conditionals add 3 bytes to frag:
- 1 extra opcode byte, 2 extra displacement bytes. */
- {0, 0, 3, 0}
+ 1 extra opcode byte, 2 displacement bytes. */
+ {0, 0, 3, 0},
+
+ /* COND_JUMP86 states. */
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
+ {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
+ /* dword conditionals adds 5 bytes to frag:
+ 1 extra opcode byte, 4 displacement bytes. */
+ {0, 0, 5, 0},
+ /* word conditionals add 4 bytes to frag:
+ 1 displacement byte and a 3 byte long branch insn. */
+ {0, 0, 4, 0}
};
static const arch_entry cpu_arch[] = {
{"i286", Cpu086|Cpu186|Cpu286 },
{"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
{"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
- {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
- {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
- {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
- {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
- {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
- {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
- {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
- {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
+ {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
+ {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
+ {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
+ {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
+ {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
+ {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
+ {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
+ {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
+ {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
+ {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
+ {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
+ {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
+ {".mmx", CpuMMX },
+ {".sse", CpuMMX|CpuMMX2|CpuSSE },
+ {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
+ {".3dnow", CpuMMX|Cpu3dnow },
+ {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
+ {".padlock", CpuPadLock },
{NULL, 0 }
};
+const pseudo_typeS md_pseudo_table[] =
+{
+#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
+ {"align", s_align_bytes, 0},
+#else
+ {"align", s_align_ptwo, 0},
+#endif
+ {"arch", set_cpu_arch, 0},
+#ifndef I386COFF
+ {"bss", s_bss, 0},
+#endif
+ {"ffloat", float_cons, 'f'},
+ {"dfloat", float_cons, 'd'},
+ {"tfloat", float_cons, 'x'},
+ {"value", cons, 2},
+ {"noopt", s_ignore, 0},
+ {"optim", s_ignore, 0},
+ {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
+ {"code16", set_code_flag, CODE_16BIT},
+ {"code32", set_code_flag, CODE_32BIT},
+ {"code64", set_code_flag, CODE_64BIT},
+ {"intel_syntax", set_intel_syntax, 1},
+ {"att_syntax", set_intel_syntax, 0},
+ {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
+ {"loc", dwarf2_directive_loc, 0},
+#ifdef TE_PE
+ {"secrel32", pe_directive_secrel, 0},
+#endif
+ {0, 0, 0}
+};
+
+/* For interface with expression (). */
+extern char *input_line_pointer;
+
+/* Hash table for instruction mnemonic lookup. */
+static struct hash_control *op_hash;
+
+/* Hash table for register lookup. */
+static struct hash_control *reg_hash;
+\f
void
i386_align_code (fragP, count)
fragS *fragP;
f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
- /* ??? We can't use these fillers for x86_64, since they often kills the
- upper halves. Solve later. */
- if (flag_code == CODE_64BIT)
- count = 1;
+ if (count <= 0 || count > 15)
+ return;
- if (count > 0 && count <= 15)
+ /* The recommended way to pad 64bit code is to use NOPs preceded by
+ maximally four 0x66 prefixes. Balance the size of nops. */
+ if (flag_code == CODE_64BIT)
{
- if (flag_code == CODE_16BIT)
+ int i;
+ int nnops = (count + 3) / 4;
+ int len = count / nnops;
+ int remains = count - nnops * len;
+ int pos = 0;
+
+ for (i = 0; i < remains; i++)
{
- memcpy (fragP->fr_literal + fragP->fr_fix,
- f16_patt[count - 1], count);
- if (count > 8)
- /* Adjust jump offset. */
- fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
+ memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
+ fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
+ pos += len + 1;
+ }
+ for (; i < nnops; i++)
+ {
+ memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
+ fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
+ pos += len;
}
- else
- memcpy (fragP->fr_literal + fragP->fr_fix,
- f32_patt[count - 1], count);
- fragP->fr_var = count;
}
+ else
+ if (flag_code == CODE_16BIT)
+ {
+ memcpy (fragP->fr_literal + fragP->fr_fix,
+ f16_patt[count - 1], count);
+ if (count > 8)
+ /* Adjust jump offset. */
+ fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
+ }
+ else
+ memcpy (fragP->fr_literal + fragP->fr_fix,
+ f32_patt[count - 1], count);
+ fragP->fr_var = count;
}
-static char *output_invalid PARAMS ((int c));
-static int i386_operand PARAMS ((char *operand_string));
-static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
-static const reg_entry *parse_register PARAMS ((char *reg_string,
- char **end_op));
-
-#ifndef I386COFF
-static void s_bss PARAMS ((int));
-#endif
-
-symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
-
static INLINE unsigned int
mode_from_disp_size (t)
unsigned int t;
smallest_imm_type (num)
offsetT num;
{
- if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
- && !(cpu_arch_flags & (CpuUnknown)))
+ if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
{
/* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486. They're the
int ret = 1;
int q;
- if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
+ if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
+ && flag_code == CODE_64BIT)
q = REX_PREFIX;
else
switch (prefix)
break;
}
- if (i.prefix[q])
+ if (i.prefix[q] != 0)
{
as_bad (_("same type of prefix used twice"));
return 0;
flag_code = new_code_flag;
cpu_arch_flags &= ~(Cpu64 | CpuNo64);
cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
- stackop_size = 'l';
+ stackop_size = LONG_MNEM_SUFFIX;
}
static void
int ask_naked_reg = 0;
SKIP_WHITESPACE ();
- if (! is_end_of_line[(unsigned char) *input_line_pointer])
+ if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
char *string = input_line_pointer;
int e = get_symbol_end ();
intel_syntax = syntax_flag;
if (ask_naked_reg == 0)
- {
-#ifdef BFD_ASSEMBLER
- allow_naked_reg = (intel_syntax
- && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
-#else
- /* Conservative default. */
- allow_naked_reg = 0;
-#endif
- }
+ allow_naked_reg = (intel_syntax
+ && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
else
allow_naked_reg = (ask_naked_reg < 0);
+
+ identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
+ identifier_chars['$'] = intel_syntax ? '$' : 0;
}
static void
{
SKIP_WHITESPACE ();
- if (! is_end_of_line[(unsigned char) *input_line_pointer])
+ if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
char *string = input_line_pointer;
int e = get_symbol_end ();
{
if (strcmp (string, cpu_arch[i].name) == 0)
{
- cpu_arch_name = cpu_arch[i].name;
- cpu_arch_flags = (cpu_arch[i].flags
- | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
- break;
+ if (*string != '.')
+ {
+ cpu_arch_name = cpu_arch[i].name;
+ cpu_sub_arch_name = NULL;
+ cpu_arch_flags = (cpu_arch[i].flags
+ | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
+ break;
+ }
+ if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
+ {
+ cpu_sub_arch_name = cpu_arch[i].name;
+ cpu_arch_flags |= cpu_arch[i].flags;
+ }
+ *input_line_pointer = e;
+ demand_empty_rest_of_line ();
+ return;
}
}
if (!cpu_arch[i].name)
no_cond_jump_promotion = 0;
if (*input_line_pointer == ','
- && ! is_end_of_line[(unsigned char) input_line_pointer[1]])
+ && !is_end_of_line[(unsigned char) input_line_pointer[1]])
{
char *string = ++input_line_pointer;
int e = get_symbol_end ();
demand_empty_rest_of_line ();
}
-const pseudo_typeS md_pseudo_table[] =
-{
-#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
- {"align", s_align_bytes, 0},
-#else
- {"align", s_align_ptwo, 0},
-#endif
- {"arch", set_cpu_arch, 0},
-#ifndef I386COFF
- {"bss", s_bss, 0},
-#endif
- {"ffloat", float_cons, 'f'},
- {"dfloat", float_cons, 'd'},
- {"tfloat", float_cons, 'x'},
- {"value", cons, 2},
- {"noopt", s_ignore, 0},
- {"optim", s_ignore, 0},
- {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
- {"code16", set_code_flag, CODE_16BIT},
- {"code32", set_code_flag, CODE_32BIT},
- {"code64", set_code_flag, CODE_64BIT},
- {"intel_syntax", set_intel_syntax, 1},
- {"att_syntax", set_intel_syntax, 0},
- {"file", dwarf2_directive_file, 0},
- {"loc", dwarf2_directive_loc, 0},
- {0, 0, 0}
-};
-
-/* For interface with expression (). */
-extern char *input_line_pointer;
-
-/* Hash table for instruction mnemonic lookup. */
-static struct hash_control *op_hash;
-
-/* Hash table for register lookup. */
-static struct hash_control *reg_hash;
-\f
-#ifdef BFD_ASSEMBLER
unsigned long
i386_mach ()
{
else
as_fatal (_("Unknown architecture"));
}
-#endif
\f
void
md_begin ()
op_hash = hash_new ();
{
- register const template *optab;
- register templates *core_optab;
+ const template *optab;
+ templates *core_optab;
/* Setup for loop. */
optab = i386_optab;
/* Initialize reg_hash hash table. */
reg_hash = hash_new ();
{
- register const reg_entry *regtab;
+ const reg_entry *regtab;
for (regtab = i386_regtab;
regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
/* Fill in lexical tables: mnemonic_chars, operand_chars. */
{
- register int c;
- register char *p;
+ int c;
+ char *p;
for (c = 0; c < 256; c++)
{
- if (isdigit (c))
+ if (ISDIGIT (c))
{
digit_chars[c] = c;
mnemonic_chars[c] = c;
register_chars[c] = c;
operand_chars[c] = c;
}
- else if (islower (c))
+ else if (ISLOWER (c))
{
mnemonic_chars[c] = c;
register_chars[c] = c;
operand_chars[c] = c;
}
- else if (isupper (c))
+ else if (ISUPPER (c))
{
- mnemonic_chars[c] = tolower (c);
+ mnemonic_chars[c] = TOLOWER (c);
register_chars[c] = mnemonic_chars[c];
operand_chars[c] = c;
}
- if (isalpha (c) || isdigit (c))
+ if (ISALPHA (c) || ISDIGIT (c))
identifier_chars[c] = c;
else if (c >= 128)
{
#ifdef LEX_AT
identifier_chars['@'] = '@';
+#endif
+#ifdef LEX_QM
+ identifier_chars['?'] = '?';
+ operand_chars['?'] = '?';
#endif
digit_chars['-'] = '-';
+ mnemonic_chars['-'] = '-';
identifier_chars['_'] = '_';
identifier_chars['.'] = '.';
record_alignment (bss_section, 2);
}
#endif
+
+ if (flag_code == CODE_64BIT)
+ {
+ x86_dwarf2_return_column = 16;
+ x86_cie_data_alignment = -8;
+ }
+ else
+ {
+ x86_dwarf2_return_column = 8;
+ x86_cie_data_alignment = -4;
+ }
}
void
fprintf (stdout, " sib: base %x index %x scale %x\n",
x->sib.base, x->sib.index, x->sib.scale);
fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
- x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
+ (x->rex & REX_MODE64) != 0,
+ (x->rex & REX_EXTX) != 0,
+ (x->rex & REX_EXTY) != 0,
+ (x->rex & REX_EXTZ) != 0);
for (i = 0; i < x->operands; i++)
{
fprintf (stdout, " #%d: ", i + 1);
char *tname;
}
-type_names[] =
+static const type_names[] =
{
{ Reg8, "r8" },
{ Reg16, "r16" },
pt (t)
unsigned int t;
{
- register struct type_name *ty;
+ const struct type_name *ty;
for (ty = type_names; ty->mask; ty++)
if (t & ty->mask)
#endif /* DEBUG386 */
\f
-int
-tc_i386_force_relocation (fixp)
- struct fix *fixp;
-{
-#ifdef BFD_ASSEMBLER
- if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return 1;
- return 0;
-#else
- /* For COFF. */
- return fixp->fx_r_type == 7;
-#endif
-}
-
-#ifdef BFD_ASSEMBLER
+static bfd_reloc_code_real_type reloc
+ PARAMS ((int, int, int, bfd_reloc_code_real_type));
static bfd_reloc_code_real_type
reloc (size, pcrel, sign, other)
int
tc_i386_fix_adjustable (fixP)
- fixS *fixP;
+ fixS *fixP ATTRIBUTE_UNUSED;
{
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
- /* Prevent all adjustments to global symbols, or else dynamic
- linking will not work correctly. */
- if (S_IS_EXTERNAL (fixP->fx_addsy)
- || S_IS_WEAK (fixP->fx_addsy))
+ if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ return 1;
+
+ /* Don't adjust pc-relative references to merge sections in 64-bit
+ mode. */
+ if (use_rela_relocations
+ && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
+ && fixP->fx_pcrel)
return 0;
-#endif
+
+ /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
+ and changed later by validate_fix. */
+ if (GOT_symbol && fixP->fx_subsy == GOT_symbol
+ && fixP->fx_r_type == BFD_RELOC_32_PCREL)
+ return 0;
+
/* adjust_reloc_syms doesn't know about the GOT. */
if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
|| fixP->fx_r_type == BFD_RELOC_386_PLT32
|| fixP->fx_r_type == BFD_RELOC_386_GOT32
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
+ || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
|| fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
|| fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
+ || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
+ || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
+ || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
+ || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
+ || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
+ || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
+#endif
return 1;
}
-#else
-#define reloc(SIZE,PCREL,SIGN,OTHER) 0
-#define BFD_RELOC_16 0
-#define BFD_RELOC_32 0
-#define BFD_RELOC_16_PCREL 0
-#define BFD_RELOC_32_PCREL 0
-#define BFD_RELOC_386_PLT32 0
-#define BFD_RELOC_386_GOT32 0
-#define BFD_RELOC_386_GOTOFF 0
-#define BFD_RELOC_X86_64_PLT32 0
-#define BFD_RELOC_X86_64_GOT32 0
-#define BFD_RELOC_X86_64_GOTPCREL 0
-#endif
-static int intel_float_operand PARAMS ((char *mnemonic));
+static int intel_float_operand PARAMS ((const char *mnemonic));
static int
intel_float_operand (mnemonic)
- char *mnemonic;
+ const char *mnemonic;
{
- if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
- return 2;
+ /* Note that the value returned is meaningful only for opcodes with (memory)
+ operands, hence the code here is free to improperly handle opcodes that
+ have no operands (for better performance and smaller code). */
- if (mnemonic[0] == 'f')
- return 1;
+ if (mnemonic[0] != 'f')
+ return 0; /* non-math */
- return 0;
+ switch (mnemonic[1])
+ {
+ /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
+ the fs segment override prefix not currently handled because no
+ call path can make opcodes without operands get here */
+ case 'i':
+ return 2 /* integer op */;
+ case 'l':
+ if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
+ return 3; /* fldcw/fldenv */
+ break;
+ case 'n':
+ if (mnemonic[2] != 'o' /* fnop */)
+ return 3; /* non-waiting control op */
+ break;
+ case 'r':
+ if (mnemonic[2] == 's')
+ return 3; /* frstor/frstpm */
+ break;
+ case 's':
+ if (mnemonic[2] == 'a')
+ return 3; /* fsave */
+ if (mnemonic[2] == 't')
+ {
+ switch (mnemonic[3])
+ {
+ case 'c': /* fstcw */
+ case 'd': /* fstdw */
+ case 'e': /* fstenv */
+ case 's': /* fsts[gw] */
+ return 3;
+ }
+ }
+ break;
+ case 'x':
+ if (mnemonic[2] == 'r' || mnemonic[2] == 's')
+ return 0; /* fxsave/fxrstor are not really math ops */
+ break;
+ }
+
+ return 1;
}
/* This is the guts of the machine-dependent assembler. LINE points to a
md_assemble (line)
char *line;
{
- /* Points to template once we've found it. */
- const template *t;
-
- /* Count the size of the instruction generated. Does not include
- variable part of jump insns before relax. */
- int insn_size = 0;
-
int j;
-
char mnemonic[MAX_MNEM_SIZE];
/* Initialize globals. */
memset (&i, '\0', sizeof (i));
for (j = 0; j < MAX_OPERANDS; j++)
- i.disp_reloc[j] = NO_RELOC;
+ i.reloc[j] = NO_RELOC;
memset (disp_expressions, '\0', sizeof (disp_expressions));
memset (im_expressions, '\0', sizeof (im_expressions));
save_stack_p = save_stack;
/* First parse an instruction mnemonic & call i386_operand for the operands.
We assume that the scrubber has arranged it so that line[0] is the valid
start of a (possibly prefixed) mnemonic. */
- {
- char *l = line;
- char *token_start = l;
- char *mnem_p;
- /* Non-zero if we found a prefix only acceptable with string insns. */
- const char *expecting_string_instruction = NULL;
+ line = parse_insn (line, mnemonic);
+ if (line == NULL)
+ return;
- while (1)
- {
- mnem_p = mnemonic;
- while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
- {
- mnem_p++;
- if (mnem_p >= mnemonic + sizeof (mnemonic))
- {
- as_bad (_("no such instruction: `%s'"), token_start);
- return;
- }
- l++;
- }
- if (!is_space_char (*l)
- && *l != END_OF_INSN
- && *l != PREFIX_SEPARATOR)
- {
- as_bad (_("invalid character %s in mnemonic"),
- output_invalid (*l));
- return;
- }
- if (token_start == l)
- {
- if (*l == PREFIX_SEPARATOR)
- as_bad (_("expecting prefix; got nothing"));
- else
- as_bad (_("expecting mnemonic; got nothing"));
- return;
- }
+ line = parse_operands (line, mnemonic);
+ if (line == NULL)
+ return;
- /* Look up instruction (or prefix) via hash table. */
- current_templates = hash_find (op_hash, mnemonic);
+ /* Now we've parsed the mnemonic into a set of templates, and have the
+ operands at hand. */
+
+ /* All intel opcodes have reversed operands except for "bound" and
+ "enter". We also don't reverse intersegment "jmp" and "call"
+ instructions with 2 immediate operands so that the immediate segment
+ precedes the offset, as it does when in AT&T mode. "enter" and the
+ intersegment "jmp" and "call" instructions are the only ones that
+ have two immediate operands. */
+ if (intel_syntax && i.operands > 1
+ && (strcmp (mnemonic, "bound") != 0)
+ && !((i.types[0] & Imm) && (i.types[1] & Imm)))
+ swap_operands ();
+
+ if (i.imm_operands)
+ optimize_imm ();
+
+ if (i.disp_operands)
+ optimize_disp ();
+
+ /* Next, we find a template that matches the given insn,
+ making sure the overlap of the given operands types is consistent
+ with the template operand types. */
- if (*l != END_OF_INSN
- && (! is_space_char (*l) || l[1] != END_OF_INSN)
- && current_templates
- && (current_templates->start->opcode_modifier & IsPrefix))
- {
- /* If we are in 16-bit mode, do not allow addr16 or data16.
- Similarly, in 32-bit mode, do not allow addr32 or data32. */
- if ((current_templates->start->opcode_modifier & (Size16 | Size32))
- && (((current_templates->start->opcode_modifier & Size32) != 0)
- ^ (flag_code == CODE_16BIT)))
- {
- as_bad (_("redundant %s prefix"),
- current_templates->start->name);
- return;
- }
- /* Add prefix, checking for repeated prefixes. */
- switch (add_prefix (current_templates->start->base_opcode))
- {
- case 0:
- return;
- case 2:
- expecting_string_instruction = current_templates->start->name;
- break;
- }
- /* Skip past PREFIX_SEPARATOR and reset token_start. */
- token_start = ++l;
- }
- else
- break;
- }
+ if (!match_template ())
+ return;
- if (!current_templates)
- {
- /* See if we can get a match by trimming off a suffix. */
- switch (mnem_p[-1])
- {
- case WORD_MNEM_SUFFIX:
- case BYTE_MNEM_SUFFIX:
- case QWORD_MNEM_SUFFIX:
- i.suffix = mnem_p[-1];
- mnem_p[-1] = '\0';
- current_templates = hash_find (op_hash, mnemonic);
- break;
- case SHORT_MNEM_SUFFIX:
- case LONG_MNEM_SUFFIX:
- if (!intel_syntax)
- {
- i.suffix = mnem_p[-1];
- mnem_p[-1] = '\0';
- current_templates = hash_find (op_hash, mnemonic);
- }
- break;
+ if (intel_syntax)
+ {
+ /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
+ if (SYSV386_COMPAT
+ && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
+ i.tm.base_opcode ^= FloatR;
+
+ /* Zap movzx and movsx suffix. The suffix may have been set from
+ "word ptr" or "byte ptr" on the source operand, but we'll use
+ the suffix later to choose the destination register. */
+ if ((i.tm.base_opcode & ~9) == 0x0fb6)
+ {
+ if (i.reg_operands < 2
+ && !i.suffix
+ && (~i.tm.opcode_modifier
+ & (No_bSuf
+ | No_wSuf
+ | No_lSuf
+ | No_sSuf
+ | No_xSuf
+ | No_qSuf)))
+ as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+
+ i.suffix = 0;
+ }
+ }
- /* Intel Syntax. */
- case 'd':
- if (intel_syntax)
- {
- if (intel_float_operand (mnemonic))
- i.suffix = SHORT_MNEM_SUFFIX;
- else
- i.suffix = LONG_MNEM_SUFFIX;
- mnem_p[-1] = '\0';
- current_templates = hash_find (op_hash, mnemonic);
- }
- break;
- }
- if (!current_templates)
- {
- as_bad (_("no such instruction: `%s'"), token_start);
- return;
- }
- }
+ if (i.tm.opcode_modifier & FWait)
+ if (!add_prefix (FWAIT_OPCODE))
+ return;
- /* Check if instruction is supported on specified architecture. */
- if (cpu_arch_flags != 0)
- {
- if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
- & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
- {
- as_warn (_("`%s' is not supported on `%s'"),
- current_templates->start->name, cpu_arch_name);
- }
- else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
- {
- as_warn (_("use .code16 to ensure correct addressing mode"));
- }
- }
+ /* Check string instruction segment overrides. */
+ if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
+ {
+ if (!check_string ())
+ return;
+ }
- /* Check for rep/repne without a string instruction. */
- if (expecting_string_instruction
- && !(current_templates->start->opcode_modifier & IsString))
- {
- as_bad (_("expecting string instruction after `%s'"),
- expecting_string_instruction);
+ if (!process_suffix ())
+ return;
+
+ /* Make still unresolved immediate matches conform to size of immediate
+ given in i.suffix. */
+ if (!finalize_imm ())
+ return;
+
+ if (i.types[0] & Imm1)
+ i.imm_operands = 0; /* kludge for shift insns. */
+ if (i.types[0] & ImplicitRegister)
+ i.reg_operands--;
+ if (i.types[1] & ImplicitRegister)
+ i.reg_operands--;
+ if (i.types[2] & ImplicitRegister)
+ i.reg_operands--;
+
+ if (i.tm.opcode_modifier & ImmExt)
+ {
+ expressionS *exp;
+
+ if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+ {
+ /* These Intel Prescott New Instructions have the fixed
+ operands with an opcode suffix which is coded in the same
+ place as an 8-bit immediate field would be. Here we check
+ those operands and remove them afterwards. */
+ unsigned int x;
+
+ for (x = 0; x < i.operands; x++)
+ if (i.op[x].regs->reg_num != x)
+ as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
+ i.op[x].regs->reg_name, x + 1, i.tm.name);
+ i.operands = 0;
+ }
+
+ /* These AMD 3DNow! and Intel Katmai New Instructions have an
+ opcode suffix which is coded in the same place as an 8-bit
+ immediate field would be. Here we fake an 8-bit immediate
+ operand from the opcode suffix stored in tm.extension_opcode. */
+
+ assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
+
+ exp = &im_expressions[i.imm_operands++];
+ i.op[i.operands].imms = exp;
+ i.types[i.operands++] = Imm8;
+ exp->X_op = O_constant;
+ exp->X_add_number = i.tm.extension_opcode;
+ i.tm.extension_opcode = None;
+ }
+
+ /* For insns with operands there are more diddles to do to the opcode. */
+ if (i.operands)
+ {
+ if (!process_operands ())
return;
- }
+ }
+ else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
+ {
+ /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
+ as_warn (_("translating to `%sp'"), i.tm.name);
+ }
- /* There may be operands to parse. */
- if (*l != END_OF_INSN)
- {
- /* 1 if operand is pending after ','. */
- unsigned int expecting_operand = 0;
+ /* Handle conversion of 'int $3' --> special int3 insn. */
+ if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
+ {
+ i.tm.base_opcode = INT3_OPCODE;
+ i.imm_operands = 0;
+ }
+
+ if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
+ && i.op[0].disps->X_op == O_constant)
+ {
+ /* Convert "jmp constant" (and "call constant") to a jump (call) to
+ the absolute address given by the constant. Since ix86 jumps and
+ calls are pc relative, we need to generate a reloc. */
+ i.op[0].disps->X_add_symbol = &abs_symbol;
+ i.op[0].disps->X_op = O_symbol;
+ }
+
+ if ((i.tm.opcode_modifier & Rex64) != 0)
+ i.rex |= REX_MODE64;
+
+ /* For 8 bit registers we need an empty rex prefix. Also if the
+ instruction already has a prefix, we need to convert old
+ registers to new ones. */
+
+ if (((i.types[0] & Reg8) != 0
+ && (i.op[0].regs->reg_flags & RegRex64) != 0)
+ || ((i.types[1] & Reg8) != 0
+ && (i.op[1].regs->reg_flags & RegRex64) != 0)
+ || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
+ && i.rex != 0))
+ {
+ int x;
+
+ i.rex |= REX_OPCODE;
+ for (x = 0; x < 2; x++)
+ {
+ /* Look for 8 bit operand that uses old registers. */
+ if ((i.types[x] & Reg8) != 0
+ && (i.op[x].regs->reg_flags & RegRex64) == 0)
+ {
+ /* In case it is "hi" register, give up. */
+ if (i.op[x].regs->reg_num > 3)
+ as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
+ i.op[x].regs->reg_name);
+
+ /* Otherwise it is equivalent to the extended register.
+ Since the encoding doesn't change this is merely
+ cosmetic cleanup for debug output. */
+
+ i.op[x].regs = i.op[x].regs + 8;
+ }
+ }
+ }
+
+ if (i.rex != 0)
+ add_prefix (REX_OPCODE | i.rex);
+
+ /* We are ready to output the insn. */
+ output_insn ();
+}
+
+static char *
+parse_insn (line, mnemonic)
+ char *line;
+ char *mnemonic;
+{
+ char *l = line;
+ char *token_start = l;
+ char *mnem_p;
+ int supported;
+ const template *t;
+
+ /* Non-zero if we found a prefix only acceptable with string insns. */
+ const char *expecting_string_instruction = NULL;
+
+ while (1)
+ {
+ mnem_p = mnemonic;
+ while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
+ {
+ mnem_p++;
+ if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
+ {
+ as_bad (_("no such instruction: `%s'"), token_start);
+ return NULL;
+ }
+ l++;
+ }
+ if (!is_space_char (*l)
+ && *l != END_OF_INSN
+ && *l != PREFIX_SEPARATOR
+ && *l != ',')
+ {
+ as_bad (_("invalid character %s in mnemonic"),
+ output_invalid (*l));
+ return NULL;
+ }
+ if (token_start == l)
+ {
+ if (*l == PREFIX_SEPARATOR)
+ as_bad (_("expecting prefix; got nothing"));
+ else
+ as_bad (_("expecting mnemonic; got nothing"));
+ return NULL;
+ }
+
+ /* Look up instruction (or prefix) via hash table. */
+ current_templates = hash_find (op_hash, mnemonic);
+
+ if (*l != END_OF_INSN
+ && (!is_space_char (*l) || l[1] != END_OF_INSN)
+ && current_templates
+ && (current_templates->start->opcode_modifier & IsPrefix))
+ {
+ /* If we are in 16-bit mode, do not allow addr16 or data16.
+ Similarly, in 32-bit mode, do not allow addr32 or data32. */
+ if ((current_templates->start->opcode_modifier & (Size16 | Size32))
+ && flag_code != CODE_64BIT
+ && (((current_templates->start->opcode_modifier & Size32) != 0)
+ ^ (flag_code == CODE_16BIT)))
+ {
+ as_bad (_("redundant %s prefix"),
+ current_templates->start->name);
+ return NULL;
+ }
+ /* Add prefix, checking for repeated prefixes. */
+ switch (add_prefix (current_templates->start->base_opcode))
+ {
+ case 0:
+ return NULL;
+ case 2:
+ expecting_string_instruction = current_templates->start->name;
+ break;
+ }
+ /* Skip past PREFIX_SEPARATOR and reset token_start. */
+ token_start = ++l;
+ }
+ else
+ break;
+ }
+
+ if (!current_templates)
+ {
+ /* See if we can get a match by trimming off a suffix. */
+ switch (mnem_p[-1])
+ {
+ case WORD_MNEM_SUFFIX:
+ if (intel_syntax && (intel_float_operand (mnemonic) & 2))
+ i.suffix = SHORT_MNEM_SUFFIX;
+ else
+ case BYTE_MNEM_SUFFIX:
+ case QWORD_MNEM_SUFFIX:
+ i.suffix = mnem_p[-1];
+ mnem_p[-1] = '\0';
+ current_templates = hash_find (op_hash, mnemonic);
+ break;
+ case SHORT_MNEM_SUFFIX:
+ case LONG_MNEM_SUFFIX:
+ if (!intel_syntax)
+ {
+ i.suffix = mnem_p[-1];
+ mnem_p[-1] = '\0';
+ current_templates = hash_find (op_hash, mnemonic);
+ }
+ break;
- /* Non-zero if operand parens not balanced. */
- unsigned int paren_not_balanced;
+ /* Intel Syntax. */
+ case 'd':
+ if (intel_syntax)
+ {
+ if (intel_float_operand (mnemonic) == 1)
+ i.suffix = SHORT_MNEM_SUFFIX;
+ else
+ i.suffix = LONG_MNEM_SUFFIX;
+ mnem_p[-1] = '\0';
+ current_templates = hash_find (op_hash, mnemonic);
+ }
+ break;
+ }
+ if (!current_templates)
+ {
+ as_bad (_("no such instruction: `%s'"), token_start);
+ return NULL;
+ }
+ }
+
+ if (current_templates->start->opcode_modifier & (Jump | JumpByte))
+ {
+ /* Check for a branch hint. We allow ",pt" and ",pn" for
+ predict taken and predict not taken respectively.
+ I'm not sure that branch hints actually do anything on loop
+ and jcxz insns (JumpByte) for current Pentium4 chips. They
+ may work in the future and it doesn't hurt to accept them
+ now. */
+ if (l[0] == ',' && l[1] == 'p')
+ {
+ if (l[2] == 't')
+ {
+ if (!add_prefix (DS_PREFIX_OPCODE))
+ return NULL;
+ l += 3;
+ }
+ else if (l[2] == 'n')
+ {
+ if (!add_prefix (CS_PREFIX_OPCODE))
+ return NULL;
+ l += 3;
+ }
+ }
+ }
+ /* Any other comma loses. */
+ if (*l == ',')
+ {
+ as_bad (_("invalid character %s in mnemonic"),
+ output_invalid (*l));
+ return NULL;
+ }
+
+ /* Check if instruction is supported on specified architecture. */
+ supported = 0;
+ for (t = current_templates->start; t < current_templates->end; ++t)
+ {
+ if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
+ & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
+ supported |= 1;
+ if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
+ supported |= 2;
+ }
+ if (!(supported & 2))
+ {
+ as_bad (flag_code == CODE_64BIT
+ ? _("`%s' is not supported in 64-bit mode")
+ : _("`%s' is only supported in 64-bit mode"),
+ current_templates->start->name);
+ return NULL;
+ }
+ if (!(supported & 1))
+ {
+ as_warn (_("`%s' is not supported on `%s%s'"),
+ current_templates->start->name,
+ cpu_arch_name,
+ cpu_sub_arch_name ? cpu_sub_arch_name : "");
+ }
+ else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
+ {
+ as_warn (_("use .code16 to ensure correct addressing mode"));
+ }
+
+ /* Check for rep/repne without a string instruction. */
+ if (expecting_string_instruction
+ && !(current_templates->start->opcode_modifier & IsString))
+ {
+ as_bad (_("expecting string instruction after `%s'"),
+ expecting_string_instruction);
+ return NULL;
+ }
+
+ return l;
+}
+
+static char *
+parse_operands (l, mnemonic)
+ char *l;
+ const char *mnemonic;
+{
+ char *token_start;
+
+ /* 1 if operand is pending after ','. */
+ unsigned int expecting_operand = 0;
+
+ /* Non-zero if operand parens not balanced. */
+ unsigned int paren_not_balanced;
+
+ while (*l != END_OF_INSN)
+ {
+ /* Skip optional white space before operand. */
+ if (is_space_char (*l))
+ ++l;
+ if (!is_operand_char (*l) && *l != END_OF_INSN)
+ {
+ as_bad (_("invalid character %s before operand %d"),
+ output_invalid (*l),
+ i.operands + 1);
+ return NULL;
+ }
+ token_start = l; /* after white space */
+ paren_not_balanced = 0;
+ while (paren_not_balanced || *l != ',')
+ {
+ if (*l == END_OF_INSN)
+ {
+ if (paren_not_balanced)
+ {
+ if (!intel_syntax)
+ as_bad (_("unbalanced parenthesis in operand %d."),
+ i.operands + 1);
+ else
+ as_bad (_("unbalanced brackets in operand %d."),
+ i.operands + 1);
+ return NULL;
+ }
+ else
+ break; /* we are done */
+ }
+ else if (!is_operand_char (*l) && !is_space_char (*l))
+ {
+ as_bad (_("invalid character %s in operand %d"),
+ output_invalid (*l),
+ i.operands + 1);
+ return NULL;
+ }
+ if (!intel_syntax)
+ {
+ if (*l == '(')
+ ++paren_not_balanced;
+ if (*l == ')')
+ --paren_not_balanced;
+ }
+ else
+ {
+ if (*l == '[')
+ ++paren_not_balanced;
+ if (*l == ']')
+ --paren_not_balanced;
+ }
+ l++;
+ }
+ if (l != token_start)
+ { /* Yes, we've read in another operand. */
+ unsigned int operand_ok;
+ this_operand = i.operands++;
+ if (i.operands > MAX_OPERANDS)
+ {
+ as_bad (_("spurious operands; (%d operands/instruction max)"),
+ MAX_OPERANDS);
+ return NULL;
+ }
+ /* Now parse operand adding info to 'i' as we go along. */
+ END_STRING_AND_SAVE (l);
+
+ if (intel_syntax)
+ operand_ok =
+ i386_intel_operand (token_start,
+ intel_float_operand (mnemonic));
+ else
+ operand_ok = i386_operand (token_start);
+
+ RESTORE_END_STRING (l);
+ if (!operand_ok)
+ return NULL;
+ }
+ else
+ {
+ if (expecting_operand)
+ {
+ expecting_operand_after_comma:
+ as_bad (_("expecting operand after ','; got nothing"));
+ return NULL;
+ }
+ if (*l == ',')
+ {
+ as_bad (_("expecting operand before ','; got nothing"));
+ return NULL;
+ }
+ }
+
+ /* Now *l must be either ',' or END_OF_INSN. */
+ if (*l == ',')
+ {
+ if (*++l == END_OF_INSN)
+ {
+ /* Just skip it, if it's \n complain. */
+ goto expecting_operand_after_comma;
+ }
+ expecting_operand = 1;
+ }
+ }
+ return l;
+}
+
+static void
+swap_operands ()
+{
+ union i386_op temp_op;
+ unsigned int temp_type;
+ enum bfd_reloc_code_real temp_reloc;
+ int xchg1 = 0;
+ int xchg2 = 0;
+
+ if (i.operands == 2)
+ {
+ xchg1 = 0;
+ xchg2 = 1;
+ }
+ else if (i.operands == 3)
+ {
+ xchg1 = 0;
+ xchg2 = 2;
+ }
+ temp_type = i.types[xchg2];
+ i.types[xchg2] = i.types[xchg1];
+ i.types[xchg1] = temp_type;
+ temp_op = i.op[xchg2];
+ i.op[xchg2] = i.op[xchg1];
+ i.op[xchg1] = temp_op;
+ temp_reloc = i.reloc[xchg2];
+ i.reloc[xchg2] = i.reloc[xchg1];
+ i.reloc[xchg1] = temp_reloc;
+
+ if (i.mem_operands == 2)
+ {
+ const seg_entry *temp_seg;
+ temp_seg = i.seg[0];
+ i.seg[0] = i.seg[1];
+ i.seg[1] = temp_seg;
+ }
+}
+
+/* Try to ensure constant immediates are represented in the smallest
+ opcode possible. */
+static void
+optimize_imm ()
+{
+ char guess_suffix = 0;
+ int op;
- do
+ if (i.suffix)
+ guess_suffix = i.suffix;
+ else if (i.reg_operands)
+ {
+ /* Figure out a suffix from the last register operand specified.
+ We can't do this properly yet, ie. excluding InOutPortReg,
+ but the following works for instructions with immediates.
+ In any case, we can't set i.suffix yet. */
+ for (op = i.operands; --op >= 0;)
+ if (i.types[op] & Reg)
+ {
+ if (i.types[op] & Reg8)
+ guess_suffix = BYTE_MNEM_SUFFIX;
+ else if (i.types[op] & Reg16)
+ guess_suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[op] & Reg32)
+ guess_suffix = LONG_MNEM_SUFFIX;
+ else if (i.types[op] & Reg64)
+ guess_suffix = QWORD_MNEM_SUFFIX;
+ break;
+ }
+ }
+ else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
+ guess_suffix = WORD_MNEM_SUFFIX;
+
+ for (op = i.operands; --op >= 0;)
+ if (i.types[op] & Imm)
+ {
+ switch (i.op[op].imms->X_op)
{
- /* Skip optional white space before operand. */
- if (is_space_char (*l))
- ++l;
- if (!is_operand_char (*l) && *l != END_OF_INSN)
+ case O_constant:
+ /* If a suffix is given, this operand may be shortened. */
+ switch (guess_suffix)
{
- as_bad (_("invalid character %s before operand %d"),
- output_invalid (*l),
- i.operands + 1);
- return;
+ case LONG_MNEM_SUFFIX:
+ i.types[op] |= Imm32 | Imm64;
+ break;
+ case WORD_MNEM_SUFFIX:
+ i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
+ break;
+ case BYTE_MNEM_SUFFIX:
+ i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
+ break;
}
- token_start = l; /* after white space */
- paren_not_balanced = 0;
- while (paren_not_balanced || *l != ',')
+
+ /* If this operand is at most 16 bits, convert it
+ to a signed 16 bit number before trying to see
+ whether it will fit in an even smaller size.
+ This allows a 16-bit operand such as $0xffe0 to
+ be recognised as within Imm8S range. */
+ if ((i.types[op] & Imm16)
+ && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
{
- if (*l == END_OF_INSN)
- {
- if (paren_not_balanced)
- {
- if (!intel_syntax)
- as_bad (_("unbalanced parenthesis in operand %d."),
- i.operands + 1);
- else
- as_bad (_("unbalanced brackets in operand %d."),
- i.operands + 1);
- return;
- }
- else
- break; /* we are done */
- }
- else if (!is_operand_char (*l) && !is_space_char (*l))
- {
- as_bad (_("invalid character %s in operand %d"),
- output_invalid (*l),
- i.operands + 1);
- return;
- }
- if (!intel_syntax)
- {
- if (*l == '(')
- ++paren_not_balanced;
- if (*l == ')')
- --paren_not_balanced;
- }
- else
- {
- if (*l == '[')
- ++paren_not_balanced;
- if (*l == ']')
- --paren_not_balanced;
- }
- l++;
- }
- if (l != token_start)
- { /* Yes, we've read in another operand. */
- unsigned int operand_ok;
- this_operand = i.operands++;
- if (i.operands > MAX_OPERANDS)
- {
- as_bad (_("spurious operands; (%d operands/instruction max)"),
- MAX_OPERANDS);
- return;
- }
- /* Now parse operand adding info to 'i' as we go along. */
- END_STRING_AND_SAVE (l);
-
- if (intel_syntax)
- operand_ok =
- i386_intel_operand (token_start,
- intel_float_operand (mnemonic));
- else
- operand_ok = i386_operand (token_start);
-
- RESTORE_END_STRING (l);
- if (!operand_ok)
- return;
+ i.op[op].imms->X_add_number =
+ (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
}
- else
+ if ((i.types[op] & Imm32)
+ && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
+ == 0))
{
- if (expecting_operand)
- {
- expecting_operand_after_comma:
- as_bad (_("expecting operand after ','; got nothing"));
- return;
- }
- if (*l == ',')
- {
- as_bad (_("expecting operand before ','; got nothing"));
- return;
- }
+ i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
+ ^ ((offsetT) 1 << 31))
+ - ((offsetT) 1 << 31));
}
+ i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
+
+ /* We must avoid matching of Imm32 templates when 64bit
+ only immediate is available. */
+ if (guess_suffix == QWORD_MNEM_SUFFIX)
+ i.types[op] &= ~Imm32;
+ break;
+
+ case O_absent:
+ case O_register:
+ abort ();
- /* Now *l must be either ',' or END_OF_INSN. */
- if (*l == ',')
+ /* Symbols and expressions. */
+ default:
+ /* Convert symbolic operand to proper sizes for matching. */
+ switch (guess_suffix)
{
- if (*++l == END_OF_INSN)
- {
- /* Just skip it, if it's \n complain. */
- goto expecting_operand_after_comma;
- }
- expecting_operand = 1;
+ case QWORD_MNEM_SUFFIX:
+ i.types[op] = Imm64 | Imm32S;
+ break;
+ case LONG_MNEM_SUFFIX:
+ i.types[op] = Imm32;
+ break;
+ case WORD_MNEM_SUFFIX:
+ i.types[op] = Imm16;
+ break;
+ case BYTE_MNEM_SUFFIX:
+ i.types[op] = Imm8 | Imm8S;
+ break;
}
+ break;
}
- while (*l != END_OF_INSN);
}
- }
-
- /* Now we've parsed the mnemonic into a set of templates, and have the
- operands at hand.
-
- Next, we find a template that matches the given insn,
- making sure the overlap of the given operands types is consistent
- with the template operand types. */
-
-#define MATCH(overlap, given, template) \
- ((overlap & ~JumpAbsolute) \
- && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
+}
- /* If given types r0 and r1 are registers they must be of the same type
- unless the expected operand type register overlap is null.
- Note that Acc in a template matches every size of reg. */
-#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
- ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
- ((g0) & Reg) == ((g1) & Reg) || \
- ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
+/* Try to use the smallest displacement type too. */
+static void
+optimize_disp ()
+{
+ int op;
- {
- register unsigned int overlap0, overlap1;
- unsigned int overlap2;
- unsigned int found_reverse_match;
- int suffix_check;
-
- /* All intel opcodes have reversed operands except for "bound" and
- "enter". We also don't reverse intersegment "jmp" and "call"
- instructions with 2 immediate operands so that the immediate segment
- precedes the offset, as it does when in AT&T mode. "enter" and the
- intersegment "jmp" and "call" instructions are the only ones that
- have two immediate operands. */
- if (intel_syntax && i.operands > 1
- && (strcmp (mnemonic, "bound") != 0)
- && !((i.types[0] & Imm) && (i.types[1] & Imm)))
+ for (op = i.operands; --op >= 0;)
+ if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
{
- union i386_op temp_op;
- unsigned int temp_type;
-#ifdef BFD_ASSEMBLER
- enum bfd_reloc_code_real temp_reloc;
-#else
- int temp_reloc;
-#endif
- int xchg1 = 0;
- int xchg2 = 0;
+ offsetT disp = i.op[op].disps->X_add_number;
- if (i.operands == 2)
+ if (i.types[op] & Disp16)
{
- xchg1 = 0;
- xchg2 = 1;
+ /* We know this operand is at most 16 bits, so
+ convert to a signed 16 bit number before trying
+ to see whether it will fit in an even smaller
+ size. */
+
+ disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
}
- else if (i.operands == 3)
+ else if (i.types[op] & Disp32)
{
- xchg1 = 0;
- xchg2 = 2;
+ /* We know this operand is at most 32 bits, so convert to a
+ signed 32 bit number before trying to see whether it will
+ fit in an even smaller size. */
+ disp &= (((offsetT) 2 << 31) - 1);
+ disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
}
- temp_type = i.types[xchg2];
- i.types[xchg2] = i.types[xchg1];
- i.types[xchg1] = temp_type;
- temp_op = i.op[xchg2];
- i.op[xchg2] = i.op[xchg1];
- i.op[xchg1] = temp_op;
- temp_reloc = i.disp_reloc[xchg2];
- i.disp_reloc[xchg2] = i.disp_reloc[xchg1];
- i.disp_reloc[xchg1] = temp_reloc;
-
- if (i.mem_operands == 2)
+ if (flag_code == CODE_64BIT)
{
- const seg_entry *temp_seg;
- temp_seg = i.seg[0];
- i.seg[0] = i.seg[1];
- i.seg[1] = temp_seg;
+ if (fits_in_signed_long (disp))
+ i.types[op] |= Disp32S;
+ if (fits_in_unsigned_long (disp))
+ i.types[op] |= Disp32;
}
+ if ((i.types[op] & (Disp32 | Disp32S | Disp16))
+ && fits_in_signed_byte (disp))
+ i.types[op] |= Disp8;
}
+}
- if (i.imm_operands)
- {
- /* Try to ensure constant immediates are represented in the smallest
- opcode possible. */
- char guess_suffix = 0;
- int op;
-
- if (i.suffix)
- guess_suffix = i.suffix;
- else if (i.reg_operands)
- {
- /* Figure out a suffix from the last register operand specified.
- We can't do this properly yet, ie. excluding InOutPortReg,
- but the following works for instructions with immediates.
- In any case, we can't set i.suffix yet. */
- for (op = i.operands; --op >= 0;)
- if (i.types[op] & Reg)
+static int
+match_template ()
+{
+ /* Points to template once we've found it. */
+ const template *t;
+ unsigned int overlap0, overlap1, overlap2;
+ unsigned int found_reverse_match;
+ int suffix_check;
+
+#define MATCH(overlap, given, template) \
+ ((overlap & ~JumpAbsolute) \
+ && (((given) & (BaseIndex | JumpAbsolute)) \
+ == ((overlap) & (BaseIndex | JumpAbsolute))))
+
+ /* If given types r0 and r1 are registers they must be of the same type
+ unless the expected operand type register overlap is null.
+ Note that Acc in a template matches every size of reg. */
+#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
+ (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
+ || ((g0) & Reg) == ((g1) & Reg) \
+ || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
+
+ overlap0 = 0;
+ overlap1 = 0;
+ overlap2 = 0;
+ found_reverse_match = 0;
+ suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
+ ? No_bSuf
+ : (i.suffix == WORD_MNEM_SUFFIX
+ ? No_wSuf
+ : (i.suffix == SHORT_MNEM_SUFFIX
+ ? No_sSuf
+ : (i.suffix == LONG_MNEM_SUFFIX
+ ? No_lSuf
+ : (i.suffix == QWORD_MNEM_SUFFIX
+ ? No_qSuf
+ : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
+ ? No_xSuf : 0))))));
+
+ t = current_templates->start;
+ if (i.suffix == QWORD_MNEM_SUFFIX
+ && flag_code != CODE_64BIT
+ && (intel_syntax
+ ? !(t->opcode_modifier & IgnoreSize)
+ && !intel_float_operand (t->name)
+ : intel_float_operand (t->name) != 2)
+ && (!(t->operand_types[0] & (RegMMX | RegXMM))
+ || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
+ && (t->base_opcode != 0x0fc7
+ || t->extension_opcode != 1 /* cmpxchg8b */))
+ t = current_templates->end;
+ for (; t < current_templates->end; t++)
+ {
+ /* Must have right number of operands. */
+ if (i.operands != t->operands)
+ continue;
+
+ /* Check the suffix, except for some instructions in intel mode. */
+ if ((t->opcode_modifier & suffix_check)
+ && !(intel_syntax
+ && (t->opcode_modifier & IgnoreSize)))
+ continue;
+
+ /* Do not verify operands when there are none. */
+ else if (!t->operands)
+ {
+ if (t->cpu_flags & ~cpu_arch_flags)
+ continue;
+ /* We've found a match; break out of loop. */
+ break;
+ }
+
+ overlap0 = i.types[0] & t->operand_types[0];
+ switch (t->operands)
+ {
+ case 1:
+ if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
+ continue;
+ break;
+ case 2:
+ case 3:
+ overlap1 = i.types[1] & t->operand_types[1];
+ if (!MATCH (overlap0, i.types[0], t->operand_types[0])
+ || !MATCH (overlap1, i.types[1], t->operand_types[1])
+ || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
+ t->operand_types[0],
+ overlap1, i.types[1],
+ t->operand_types[1]))
+ {
+ /* Check if other direction is valid ... */
+ if ((t->opcode_modifier & (D | FloatD)) == 0)
+ continue;
+
+ /* Try reversing direction of operands. */
+ overlap0 = i.types[0] & t->operand_types[1];
+ overlap1 = i.types[1] & t->operand_types[0];
+ if (!MATCH (overlap0, i.types[0], t->operand_types[1])
+ || !MATCH (overlap1, i.types[1], t->operand_types[0])
+ || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
+ t->operand_types[1],
+ overlap1, i.types[1],
+ t->operand_types[0]))
{
- if (i.types[op] & Reg8)
- guess_suffix = BYTE_MNEM_SUFFIX;
- else if (i.types[op] & Reg16)
- guess_suffix = WORD_MNEM_SUFFIX;
- else if (i.types[op] & Reg32)
- guess_suffix = LONG_MNEM_SUFFIX;
- else if (i.types[op] & Reg64)
- guess_suffix = QWORD_MNEM_SUFFIX;
- break;
+ /* Does not match either direction. */
+ continue;
}
- }
- else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
- guess_suffix = WORD_MNEM_SUFFIX;
+ /* found_reverse_match holds which of D or FloatDR
+ we've found. */
+ found_reverse_match = t->opcode_modifier & (D | FloatDR);
+ }
+ /* Found a forward 2 operand match here. */
+ else if (t->operands == 3)
+ {
+ /* Here we make use of the fact that there are no
+ reverse match 3 operand instructions, and all 3
+ operand instructions only need to be checked for
+ register consistency between operands 2 and 3. */
+ overlap2 = i.types[2] & t->operand_types[2];
+ if (!MATCH (overlap2, i.types[2], t->operand_types[2])
+ || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
+ t->operand_types[1],
+ overlap2, i.types[2],
+ t->operand_types[2]))
+
+ continue;
+ }
+ /* Found either forward/reverse 2 or 3 operand match here:
+ slip through to break. */
+ }
+ if (t->cpu_flags & ~cpu_arch_flags)
+ {
+ found_reverse_match = 0;
+ continue;
+ }
+ /* We've found a match; break out of loop. */
+ break;
+ }
+
+ if (t == current_templates->end)
+ {
+ /* We found no match. */
+ as_bad (_("suffix or operands invalid for `%s'"),
+ current_templates->start->name);
+ return 0;
+ }
+
+ if (!quiet_warnings)
+ {
+ if (!intel_syntax
+ && ((i.types[0] & JumpAbsolute)
+ != (t->operand_types[0] & JumpAbsolute)))
+ {
+ as_warn (_("indirect %s without `*'"), t->name);
+ }
+
+ if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
+ == (IsPrefix | IgnoreSize))
+ {
+ /* Warn them that a data or address size prefix doesn't
+ affect assembly of the next line of code. */
+ as_warn (_("stand-alone `%s' prefix"), t->name);
+ }
+ }
- for (op = i.operands; --op >= 0;)
- if (i.types[op] & Imm)
+ /* Copy the template we found. */
+ i.tm = *t;
+ if (found_reverse_match)
+ {
+ /* If we found a reverse match we must alter the opcode
+ direction bit. found_reverse_match holds bits to change
+ (different for int & float insns). */
+
+ i.tm.base_opcode ^= found_reverse_match;
+
+ i.tm.operand_types[0] = t->operand_types[1];
+ i.tm.operand_types[1] = t->operand_types[0];
+ }
+
+ return 1;
+}
+
+static int
+check_string ()
+{
+ int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
+ if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
+ {
+ if (i.seg[0] != NULL && i.seg[0] != &es)
+ {
+ as_bad (_("`%s' operand %d must use `%%es' segment"),
+ i.tm.name,
+ mem_op + 1);
+ return 0;
+ }
+ /* There's only ever one segment override allowed per instruction.
+ This instruction possibly has a legal segment override on the
+ second operand, so copy the segment to where non-string
+ instructions store it, allowing common code. */
+ i.seg[0] = i.seg[1];
+ }
+ else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
+ {
+ if (i.seg[1] != NULL && i.seg[1] != &es)
+ {
+ as_bad (_("`%s' operand %d must use `%%es' segment"),
+ i.tm.name,
+ mem_op + 2);
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int
+process_suffix (void)
+{
+ /* If matched instruction specifies an explicit instruction mnemonic
+ suffix, use it. */
+ if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
+ {
+ if (i.tm.opcode_modifier & Size16)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.tm.opcode_modifier & Size64)
+ i.suffix = QWORD_MNEM_SUFFIX;
+ else
+ i.suffix = LONG_MNEM_SUFFIX;
+ }
+ else if (i.reg_operands)
+ {
+ /* If there's no instruction mnemonic suffix we try to invent one
+ based on register operands. */
+ if (!i.suffix)
+ {
+ /* We take i.suffix from the last register operand specified,
+ Destination register type is more significant than source
+ register type. */
+ int op;
+
+ for (op = i.operands; --op >= 0;)
+ if ((i.types[op] & Reg)
+ && !(i.tm.operand_types[op] & InOutPortReg))
+ {
+ i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
+ (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
+ (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+ LONG_MNEM_SUFFIX);
+ break;
+ }
+ }
+ else if (i.suffix == BYTE_MNEM_SUFFIX)
+ {
+ if (!check_byte_reg ())
+ return 0;
+ }
+ else if (i.suffix == LONG_MNEM_SUFFIX)
+ {
+ if (!check_long_reg ())
+ return 0;
+ }
+ else if (i.suffix == QWORD_MNEM_SUFFIX)
+ {
+ if (!check_qword_reg ())
+ return 0;
+ }
+ else if (i.suffix == WORD_MNEM_SUFFIX)
+ {
+ if (!check_word_reg ())
+ return 0;
+ }
+ else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
+ /* Do nothing if the instruction is going to ignore the prefix. */
+ ;
+ else
+ abort ();
+ }
+ else if ((i.tm.opcode_modifier & DefaultSize)
+ && !i.suffix
+ /* exclude fldenv/frstor/fsave/fstenv */
+ && (i.tm.opcode_modifier & No_sSuf))
+ {
+ i.suffix = stackop_size;
+ }
+ else if (intel_syntax
+ && !i.suffix
+ && ((i.tm.operand_types[0] & JumpAbsolute)
+ || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
+ || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
+ && i.tm.extension_opcode <= 3)))
+ {
+ switch (flag_code)
+ {
+ case CODE_64BIT:
+ if (!(i.tm.opcode_modifier & No_qSuf))
{
- switch (i.op[op].imms->X_op)
- {
- case O_constant:
- /* If a suffix is given, this operand may be shortened. */
- switch (guess_suffix)
- {
- case LONG_MNEM_SUFFIX:
- i.types[op] |= Imm32 | Imm64;
- break;
- case WORD_MNEM_SUFFIX:
- i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
- break;
- case BYTE_MNEM_SUFFIX:
- i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
- break;
- }
+ i.suffix = QWORD_MNEM_SUFFIX;
+ break;
+ }
+ case CODE_32BIT:
+ if (!(i.tm.opcode_modifier & No_lSuf))
+ i.suffix = LONG_MNEM_SUFFIX;
+ break;
+ case CODE_16BIT:
+ if (!(i.tm.opcode_modifier & No_wSuf))
+ i.suffix = WORD_MNEM_SUFFIX;
+ break;
+ }
+ }
- /* If this operand is at most 16 bits, convert it
- to a signed 16 bit number before trying to see
- whether it will fit in an even smaller size.
- This allows a 16-bit operand such as $0xffe0 to
- be recognised as within Imm8S range. */
- if ((i.types[op] & Imm16)
- && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
- {
- i.op[op].imms->X_add_number =
- (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
- }
- if ((i.types[op] & Imm32)
- && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
- {
- i.op[op].imms->X_add_number =
- (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
- }
- i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
- /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
- if (guess_suffix == QWORD_MNEM_SUFFIX)
- i.types[op] &= ~Imm32;
- break;
- case O_absent:
- case O_register:
- abort ();
- /* Symbols and expressions. */
- default:
- /* Convert symbolic operand to proper sizes for matching. */
- switch (guess_suffix)
- {
- case QWORD_MNEM_SUFFIX:
- i.types[op] = Imm64 | Imm32S;
- break;
- case LONG_MNEM_SUFFIX:
- i.types[op] = Imm32 | Imm64;
- break;
- case WORD_MNEM_SUFFIX:
- i.types[op] = Imm16 | Imm32 | Imm64;
- break;
- break;
- case BYTE_MNEM_SUFFIX:
- i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
- break;
- break;
- }
- break;
- }
+ if (!i.suffix)
+ {
+ if (!intel_syntax)
+ {
+ if (i.tm.opcode_modifier & W)
+ {
+ as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
+ return 0;
}
- }
+ }
+ else
+ {
+ unsigned int suffixes = ~i.tm.opcode_modifier
+ & (No_bSuf
+ | No_wSuf
+ | No_lSuf
+ | No_sSuf
+ | No_xSuf
+ | No_qSuf);
+
+ if ((i.tm.opcode_modifier & W)
+ || ((suffixes & (suffixes - 1))
+ && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
+ {
+ as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+ return 0;
+ }
+ }
+ }
+
+ /* Change the opcode based on the operand size given by i.suffix;
+ We don't need to change things for byte insns. */
+
+ if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
+ {
+ /* It's not a byte, select word/dword operation. */
+ if (i.tm.opcode_modifier & W)
+ {
+ if (i.tm.opcode_modifier & ShortForm)
+ i.tm.base_opcode |= 8;
+ else
+ i.tm.base_opcode |= 1;
+ }
+
+ /* Now select between word & dword operations via the operand
+ size prefix, except for instructions that will ignore this
+ prefix anyway. */
+ if (i.suffix != QWORD_MNEM_SUFFIX
+ && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
+ && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
+ && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
+ || (flag_code == CODE_64BIT
+ && (i.tm.opcode_modifier & JumpByte))))
+ {
+ unsigned int prefix = DATA_PREFIX_OPCODE;
+
+ if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
+ prefix = ADDR_PREFIX_OPCODE;
+
+ if (!add_prefix (prefix))
+ return 0;
+ }
- if (i.disp_operands)
- {
- /* Try to use the smallest displacement type too. */
- int op;
+ /* Set mode64 for an operand. */
+ if (i.suffix == QWORD_MNEM_SUFFIX
+ && flag_code == CODE_64BIT
+ && (i.tm.opcode_modifier & NoRex64) == 0)
+ i.rex |= REX_MODE64;
- for (op = i.operands; --op >= 0;)
- if ((i.types[op] & Disp)
- && i.op[op].imms->X_op == O_constant)
- {
- offsetT disp = i.op[op].disps->X_add_number;
+ /* Size floating point instruction. */
+ if (i.suffix == LONG_MNEM_SUFFIX)
+ if (i.tm.opcode_modifier & FloatMF)
+ i.tm.base_opcode ^= 4;
+ }
- if (i.types[op] & Disp16)
- {
- /* We know this operand is at most 16 bits, so
- convert to a signed 16 bit number before trying
- to see whether it will fit in an even smaller
- size. */
+ return 1;
+}
- disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
- }
- else if (i.types[op] & Disp32)
- {
- /* We know this operand is at most 32 bits, so convert to a
- signed 32 bit number before trying to see whether it will
- fit in an even smaller size. */
- disp &= (((offsetT) 2 << 31) - 1);
- disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
- }
- if (flag_code == CODE_64BIT)
- {
- if (fits_in_signed_long (disp))
- i.types[op] |= Disp32S;
- if (fits_in_unsigned_long (disp))
- i.types[op] |= Disp32;
- }
- if ((i.types[op] & (Disp32 | Disp32S | Disp16))
- && fits_in_signed_byte (disp))
- i.types[op] |= Disp8;
- }
- }
+static int
+check_byte_reg (void)
+{
+ int op;
- overlap0 = 0;
- overlap1 = 0;
- overlap2 = 0;
- found_reverse_match = 0;
- suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
- ? No_bSuf
- : (i.suffix == WORD_MNEM_SUFFIX
- ? No_wSuf
- : (i.suffix == SHORT_MNEM_SUFFIX
- ? No_sSuf
- : (i.suffix == LONG_MNEM_SUFFIX
- ? No_lSuf
- : (i.suffix == QWORD_MNEM_SUFFIX
- ? No_qSuf
- : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
-
- for (t = current_templates->start;
- t < current_templates->end;
- t++)
- {
- /* Must have right number of operands. */
- if (i.operands != t->operands)
+ for (op = i.operands; --op >= 0;)
+ {
+ /* If this is an eight bit register, it's OK. If it's the 16 or
+ 32 bit version of an eight bit register, we will just use the
+ low portion, and that's OK too. */
+ if (i.types[op] & Reg8)
+ continue;
+
+ /* movzx and movsx should not generate this warning. */
+ if (intel_syntax
+ && (i.tm.base_opcode == 0xfb7
+ || i.tm.base_opcode == 0xfb6
+ || i.tm.base_opcode == 0x63
+ || i.tm.base_opcode == 0xfbe
+ || i.tm.base_opcode == 0xfbf))
+ continue;
+
+ if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
+ {
+ /* Prohibit these changes in the 64bit mode, since the
+ lowering is more complicated. */
+ if (flag_code == CODE_64BIT
+ && (i.tm.operand_types[op] & InOutPortReg) == 0)
+ {
+ as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
+ }
+#if REGISTER_WARNINGS
+ if (!quiet_warnings
+ && (i.tm.operand_types[op] & InOutPortReg) == 0)
+ as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+ (i.op[op].regs + (i.types[op] & Reg16
+ ? REGNAM_AL - REGNAM_AX
+ : REGNAM_AL - REGNAM_EAX))->reg_name,
+ i.op[op].regs->reg_name,
+ i.suffix);
+#endif
continue;
+ }
+ /* Any other register is bad. */
+ if (i.types[op] & (Reg | RegMMX | RegXMM
+ | SReg2 | SReg3
+ | Control | Debug | Test
+ | FloatReg | FloatAcc))
+ {
+ as_bad (_("`%%%s' not allowed with `%s%c'"),
+ i.op[op].regs->reg_name,
+ i.tm.name,
+ i.suffix);
+ return 0;
+ }
+ }
+ return 1;
+}
- /* Check the suffix, except for some instructions in intel mode. */
- if ((t->opcode_modifier & suffix_check)
- && !(intel_syntax
- && (t->opcode_modifier & IgnoreSize))
- && !(intel_syntax
- && t->base_opcode == 0xd9
- && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
- || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
- continue;
+static int
+check_long_reg ()
+{
+ int op;
- /* Do not verify operands when there are none. */
- else if (!t->operands)
+ for (op = i.operands; --op >= 0;)
+ /* Reject eight bit registers, except where the template requires
+ them. (eg. movzb) */
+ if ((i.types[op] & Reg8) != 0
+ && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
+ {
+ as_bad (_("`%%%s' not allowed with `%s%c'"),
+ i.op[op].regs->reg_name,
+ i.tm.name,
+ i.suffix);
+ return 0;
+ }
+ /* Warn if the e prefix on a general reg is missing. */
+ else if ((!quiet_warnings || flag_code == CODE_64BIT)
+ && (i.types[op] & Reg16) != 0
+ && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
+ {
+ /* Prohibit these changes in the 64bit mode, since the
+ lowering is more complicated. */
+ if (flag_code == CODE_64BIT)
{
- if (t->cpu_flags & ~cpu_arch_flags)
- continue;
- /* We've found a match; break out of loop. */
- break;
+ as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
}
+#if REGISTER_WARNINGS
+ else
+ as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+ (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
+ i.op[op].regs->reg_name,
+ i.suffix);
+#endif
+ }
+ /* Warn if the r prefix on a general reg is missing. */
+ else if ((i.types[op] & Reg64) != 0
+ && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
+ {
+ as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
+ }
+ return 1;
+}
- overlap0 = i.types[0] & t->operand_types[0];
- switch (t->operands)
- {
- case 1:
- if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
- continue;
- break;
- case 2:
- case 3:
- overlap1 = i.types[1] & t->operand_types[1];
- if (!MATCH (overlap0, i.types[0], t->operand_types[0])
- || !MATCH (overlap1, i.types[1], t->operand_types[1])
- || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
- t->operand_types[0],
- overlap1, i.types[1],
- t->operand_types[1]))
- {
- /* Check if other direction is valid ... */
- if ((t->opcode_modifier & (D|FloatD)) == 0)
- continue;
-
- /* Try reversing direction of operands. */
- overlap0 = i.types[0] & t->operand_types[1];
- overlap1 = i.types[1] & t->operand_types[0];
- if (!MATCH (overlap0, i.types[0], t->operand_types[1])
- || !MATCH (overlap1, i.types[1], t->operand_types[0])
- || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
- t->operand_types[1],
- overlap1, i.types[1],
- t->operand_types[0]))
- {
- /* Does not match either direction. */
- continue;
- }
- /* found_reverse_match holds which of D or FloatDR
- we've found. */
- found_reverse_match = t->opcode_modifier & (D|FloatDR);
- }
- /* Found a forward 2 operand match here. */
- else if (t->operands == 3)
- {
- /* Here we make use of the fact that there are no
- reverse match 3 operand instructions, and all 3
- operand instructions only need to be checked for
- register consistency between operands 2 and 3. */
- overlap2 = i.types[2] & t->operand_types[2];
- if (!MATCH (overlap2, i.types[2], t->operand_types[2])
- || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
- t->operand_types[1],
- overlap2, i.types[2],
- t->operand_types[2]))
+static int
+check_qword_reg ()
+{
+ int op;
- continue;
- }
- /* Found either forward/reverse 2 or 3 operand match here:
- slip through to break. */
- }
- if (t->cpu_flags & ~cpu_arch_flags)
- {
- found_reverse_match = 0;
- continue;
- }
- /* We've found a match; break out of loop. */
- break;
+ for (op = i.operands; --op >= 0; )
+ /* Reject eight bit registers, except where the template requires
+ them. (eg. movzb) */
+ if ((i.types[op] & Reg8) != 0
+ && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
+ {
+ as_bad (_("`%%%s' not allowed with `%s%c'"),
+ i.op[op].regs->reg_name,
+ i.tm.name,
+ i.suffix);
+ return 0;
}
- if (t == current_templates->end)
+ /* Warn if the e prefix on a general reg is missing. */
+ else if (((i.types[op] & Reg16) != 0
+ || (i.types[op] & Reg32) != 0)
+ && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
{
- /* We found no match. */
- as_bad (_("suffix or operands invalid for `%s'"),
- current_templates->start->name);
- return;
+ /* Prohibit these changes in the 64bit mode, since the
+ lowering is more complicated. */
+ as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
}
+ return 1;
+}
- if (!quiet_warnings)
+static int
+check_word_reg ()
+{
+ int op;
+ for (op = i.operands; --op >= 0;)
+ /* Reject eight bit registers, except where the template requires
+ them. (eg. movzb) */
+ if ((i.types[op] & Reg8) != 0
+ && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
{
- if (!intel_syntax
- && ((i.types[0] & JumpAbsolute)
- != (t->operand_types[0] & JumpAbsolute)))
- {
- as_warn (_("indirect %s without `*'"), t->name);
- }
-
- if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
- == (IsPrefix|IgnoreSize))
+ as_bad (_("`%%%s' not allowed with `%s%c'"),
+ i.op[op].regs->reg_name,
+ i.tm.name,
+ i.suffix);
+ return 0;
+ }
+ /* Warn if the e prefix on a general reg is present. */
+ else if ((!quiet_warnings || flag_code == CODE_64BIT)
+ && (i.types[op] & Reg32) != 0
+ && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
+ {
+ /* Prohibit these changes in the 64bit mode, since the
+ lowering is more complicated. */
+ if (flag_code == CODE_64BIT)
{
- /* Warn them that a data or address size prefix doesn't
- affect assembly of the next line of code. */
- as_warn (_("stand-alone `%s' prefix"), t->name);
+ as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
}
+ else
+#if REGISTER_WARNINGS
+ as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+ (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
+ i.op[op].regs->reg_name,
+ i.suffix);
+#endif
}
+ return 1;
+}
- /* Copy the template we found. */
- i.tm = *t;
- if (found_reverse_match)
- {
- /* If we found a reverse match we must alter the opcode
- direction bit. found_reverse_match holds bits to change
- (different for int & float insns). */
+static int
+finalize_imm ()
+{
+ unsigned int overlap0, overlap1, overlap2;
- i.tm.base_opcode ^= found_reverse_match;
+ overlap0 = i.types[0] & i.tm.operand_types[0];
+ if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
+ && overlap0 != Imm8 && overlap0 != Imm8S
+ && overlap0 != Imm16 && overlap0 != Imm32S
+ && overlap0 != Imm32 && overlap0 != Imm64)
+ {
+ if (i.suffix)
+ {
+ overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
+ ? Imm8 | Imm8S
+ : (i.suffix == WORD_MNEM_SUFFIX
+ ? Imm16
+ : (i.suffix == QWORD_MNEM_SUFFIX
+ ? Imm64 | Imm32S
+ : Imm32)));
+ }
+ else if (overlap0 == (Imm16 | Imm32S | Imm32)
+ || overlap0 == (Imm16 | Imm32)
+ || overlap0 == (Imm16 | Imm32S))
+ {
+ overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
+ ? Imm16 : Imm32S);
+ }
+ if (overlap0 != Imm8 && overlap0 != Imm8S
+ && overlap0 != Imm16 && overlap0 != Imm32S
+ && overlap0 != Imm32 && overlap0 != Imm64)
+ {
+ as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
+ return 0;
+ }
+ }
+ i.types[0] = overlap0;
- i.tm.operand_types[0] = t->operand_types[1];
- i.tm.operand_types[1] = t->operand_types[0];
- }
+ overlap1 = i.types[1] & i.tm.operand_types[1];
+ if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
+ && overlap1 != Imm8 && overlap1 != Imm8S
+ && overlap1 != Imm16 && overlap1 != Imm32S
+ && overlap1 != Imm32 && overlap1 != Imm64)
+ {
+ if (i.suffix)
+ {
+ overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
+ ? Imm8 | Imm8S
+ : (i.suffix == WORD_MNEM_SUFFIX
+ ? Imm16
+ : (i.suffix == QWORD_MNEM_SUFFIX
+ ? Imm64 | Imm32S
+ : Imm32)));
+ }
+ else if (overlap1 == (Imm16 | Imm32 | Imm32S)
+ || overlap1 == (Imm16 | Imm32)
+ || overlap1 == (Imm16 | Imm32S))
+ {
+ overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
+ ? Imm16 : Imm32S);
+ }
+ if (overlap1 != Imm8 && overlap1 != Imm8S
+ && overlap1 != Imm16 && overlap1 != Imm32S
+ && overlap1 != Imm32 && overlap1 != Imm64)
+ {
+ as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
+ return 0;
+ }
+ }
+ i.types[1] = overlap1;
- /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
- if (SYSV386_COMPAT
- && intel_syntax
- && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
- i.tm.base_opcode ^= FloatR;
+ overlap2 = i.types[2] & i.tm.operand_types[2];
+ assert ((overlap2 & Imm) == 0);
+ i.types[2] = overlap2;
- if (i.tm.opcode_modifier & FWait)
- if (! add_prefix (FWAIT_OPCODE))
- return;
+ return 1;
+}
- /* Check string instruction segment overrides. */
- if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
- {
- int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
- if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
- {
- if (i.seg[0] != NULL && i.seg[0] != &es)
- {
- as_bad (_("`%s' operand %d must use `%%es' segment"),
- i.tm.name,
- mem_op + 1);
- return;
- }
- /* There's only ever one segment override allowed per instruction.
- This instruction possibly has a legal segment override on the
- second operand, so copy the segment to where non-string
- instructions store it, allowing common code. */
- i.seg[0] = i.seg[1];
- }
- else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
- {
- if (i.seg[1] != NULL && i.seg[1] != &es)
- {
- as_bad (_("`%s' operand %d must use `%%es' segment"),
- i.tm.name,
- mem_op + 2);
- return;
- }
- }
- }
+static int
+process_operands ()
+{
+ /* Default segment register this instruction will use for memory
+ accesses. 0 means unknown. This is only for optimizing out
+ unnecessary segment overrides. */
+ const seg_entry *default_seg = 0;
+
+ /* The imul $imm, %reg instruction is converted into
+ imul $imm, %reg, %reg, and the clr %reg instruction
+ is converted into xor %reg, %reg. */
+ if (i.tm.opcode_modifier & regKludge)
+ {
+ unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
+ /* Pretend we saw the extra register operand. */
+ assert (i.op[first_reg_op + 1].regs == 0);
+ i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
+ i.types[first_reg_op + 1] = i.types[first_reg_op];
+ i.reg_operands = 2;
+ }
- if (i.reg_operands && flag_code < CODE_64BIT)
- {
- int op;
- for (op = i.operands; --op >= 0;)
- if ((i.types[op] & Reg)
- && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
+ if (i.tm.opcode_modifier & ShortForm)
+ {
+ /* The register or float register operand is in operand 0 or 1. */
+ unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
+ /* Register goes in low 3 bits of opcode. */
+ i.tm.base_opcode |= i.op[op].regs->reg_num;
+ if ((i.op[op].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
+ {
+ /* Warn about some common errors, but press on regardless.
+ The first case can be generated by gcc (<= 2.8.1). */
+ if (i.operands == 2)
{
- as_bad (_("Extended register `%%%s' available only in 64bit mode."),
- i.op[op].regs->reg_name);
- return;
+ /* Reversed arguments on faddp, fsubp, etc. */
+ as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
+ i.op[1].regs->reg_name,
+ i.op[0].regs->reg_name);
}
- }
+ else
+ {
+ /* Extraneous `l' suffix on fp insn. */
+ as_warn (_("translating to `%s %%%s'"), i.tm.name,
+ i.op[0].regs->reg_name);
+ }
+ }
+ }
+ else if (i.tm.opcode_modifier & Modrm)
+ {
+ /* The opcode is completed (modulo i.tm.extension_opcode which
+ must be put into the modrm byte). Now, we make the modrm and
+ index base bytes based on all the info we've collected. */
- /* If matched instruction specifies an explicit instruction mnemonic
- suffix, use it. */
- if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
- {
- if (i.tm.opcode_modifier & Size16)
- i.suffix = WORD_MNEM_SUFFIX;
- else if (i.tm.opcode_modifier & Size64)
- i.suffix = QWORD_MNEM_SUFFIX;
- else
- i.suffix = LONG_MNEM_SUFFIX;
- }
- else if (i.reg_operands)
- {
- /* If there's no instruction mnemonic suffix we try to invent one
- based on register operands. */
- if (!i.suffix)
- {
- /* We take i.suffix from the last register operand specified,
- Destination register type is more significant than source
- register type. */
- int op;
- for (op = i.operands; --op >= 0;)
- if ((i.types[op] & Reg)
- && !(i.tm.operand_types[op] & InOutPortReg))
- {
- i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
- (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
- (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
- LONG_MNEM_SUFFIX);
- break;
- }
- }
- else if (i.suffix == BYTE_MNEM_SUFFIX)
- {
- int op;
- for (op = i.operands; --op >= 0;)
- {
- /* If this is an eight bit register, it's OK. If it's
- the 16 or 32 bit version of an eight bit register,
- we will just use the low portion, and that's OK too. */
- if (i.types[op] & Reg8)
- continue;
+ default_seg = build_modrm_byte ();
+ }
+ else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
+ {
+ if (i.tm.base_opcode == POP_SEG_SHORT
+ && i.op[0].regs->reg_num == 1)
+ {
+ as_bad (_("you can't `pop %%cs'"));
+ return 0;
+ }
+ i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
+ if ((i.op[0].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ }
+ else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
+ {
+ default_seg = &ds;
+ }
+ else if ((i.tm.opcode_modifier & IsString) != 0)
+ {
+ /* For the string instructions that allow a segment override
+ on one of their operands, the default segment is ds. */
+ default_seg = &ds;
+ }
- /* movzx and movsx should not generate this warning. */
- if (intel_syntax
- && (i.tm.base_opcode == 0xfb7
- || i.tm.base_opcode == 0xfb6
- || i.tm.base_opcode == 0x63
- || i.tm.base_opcode == 0xfbe
- || i.tm.base_opcode == 0xfbf))
- continue;
+ if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
+ as_warn (_("segment override on `lea' is ineffectual"));
- if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
-#if 0
- /* Check that the template allows eight bit regs
- This kills insns such as `orb $1,%edx', which
- maybe should be allowed. */
- && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
-#endif
- )
- {
- /* Prohibit these changes in the 64bit mode, since
- the lowering is more complicated. */
- if (flag_code == CODE_64BIT
- && (i.tm.operand_types[op] & InOutPortReg) == 0)
- as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
- i.op[op].regs->reg_name,
- i.suffix);
-#if REGISTER_WARNINGS
- if (!quiet_warnings
- && (i.tm.operand_types[op] & InOutPortReg) == 0)
- as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
- (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
- i.op[op].regs->reg_name,
- i.suffix);
-#endif
- continue;
- }
- /* Any other register is bad. */
- if (i.types[op] & (Reg | RegMMX | RegXMM
- | SReg2 | SReg3
- | Control | Debug | Test
- | FloatReg | FloatAcc))
- {
- as_bad (_("`%%%s' not allowed with `%s%c'"),
- i.op[op].regs->reg_name,
- i.tm.name,
- i.suffix);
- return;
- }
- }
- }
- else if (i.suffix == LONG_MNEM_SUFFIX)
- {
- int op;
+ /* If a segment was explicitly specified, and the specified segment
+ is not the default, use an opcode prefix to select it. If we
+ never figured out what the default segment is, then default_seg
+ will be zero at this point, and the specified segment prefix will
+ always be used. */
+ if ((i.seg[0]) && (i.seg[0] != default_seg))
+ {
+ if (!add_prefix (i.seg[0]->seg_prefix))
+ return 0;
+ }
+ return 1;
+}
- for (op = i.operands; --op >= 0;)
- /* Reject eight bit registers, except where the template
- requires them. (eg. movzb) */
- if ((i.types[op] & Reg8) != 0
- && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
- {
- as_bad (_("`%%%s' not allowed with `%s%c'"),
- i.op[op].regs->reg_name,
- i.tm.name,
- i.suffix);
- return;
- }
- /* Warn if the e prefix on a general reg is missing. */
- else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && (i.types[op] & Reg16) != 0
- && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
+static const seg_entry *
+build_modrm_byte ()
+{
+ const seg_entry *default_seg = 0;
+
+ /* i.reg_operands MUST be the number of real register operands;
+ implicit registers do not count. */
+ if (i.reg_operands == 2)
+ {
+ unsigned int source, dest;
+ source = ((i.types[0]
+ & (Reg | RegMMX | RegXMM
+ | SReg2 | SReg3
+ | Control | Debug | Test))
+ ? 0 : 1);
+ dest = source + 1;
+
+ i.rm.mode = 3;
+ /* One of the register operands will be encoded in the i.tm.reg
+ field, the other in the combined i.tm.mode and i.tm.regmem
+ fields. If no form of this instruction supports a memory
+ destination operand, then we assume the source operand may
+ sometimes be a memory operand and so we need to store the
+ destination in the i.rm.reg field. */
+ if ((i.tm.operand_types[dest] & AnyMem) == 0)
+ {
+ i.rm.reg = i.op[dest].regs->reg_num;
+ i.rm.regmem = i.op[source].regs->reg_num;
+ if ((i.op[dest].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTX;
+ if ((i.op[source].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ }
+ else
+ {
+ i.rm.reg = i.op[source].regs->reg_num;
+ i.rm.regmem = i.op[dest].regs->reg_num;
+ if ((i.op[dest].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ if ((i.op[source].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTX;
+ }
+ if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
+ {
+ if (!((i.types[0] | i.types[1]) & Control))
+ abort ();
+ i.rex &= ~(REX_EXTX | REX_EXTZ);
+ add_prefix (LOCK_PREFIX_OPCODE);
+ }
+ }
+ else
+ { /* If it's not 2 reg operands... */
+ if (i.mem_operands)
+ {
+ unsigned int fake_zero_displacement = 0;
+ unsigned int op = ((i.types[0] & AnyMem)
+ ? 0
+ : (i.types[1] & AnyMem) ? 1 : 2);
+
+ default_seg = &ds;
+
+ if (i.base_reg == 0)
+ {
+ i.rm.mode = 0;
+ if (!i.disp_operands)
+ fake_zero_displacement = 1;
+ if (i.index_reg == 0)
{
- /* Prohibit these changes in the 64bit mode, since
- the lowering is more complicated. */
+ /* Operand is just <disp> */
if (flag_code == CODE_64BIT)
- as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
- i.op[op].regs->reg_name,
- i.suffix);
-#if REGISTER_WARNINGS
+ {
+ /* 64bit mode overwrites the 32bit absolute
+ addressing by RIP relative addressing and
+ absolute addressing is encoded by one of the
+ redundant SIB forms. */
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.sib.base = NO_BASE_REGISTER;
+ i.sib.index = NO_INDEX_REGISTER;
+ i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
+ }
+ else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
+ {
+ i.rm.regmem = NO_BASE_REGISTER_16;
+ i.types[op] = Disp16;
+ }
else
- as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
- (i.op[op].regs + 8)->reg_name,
- i.op[op].regs->reg_name,
- i.suffix);
-#endif
- }
- /* Warn if the r prefix on a general reg is missing. */
- else if ((i.types[op] & Reg64) != 0
- && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
- {
- as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
- i.op[op].regs->reg_name,
- i.suffix);
- }
- }
- else if (i.suffix == QWORD_MNEM_SUFFIX)
- {
- int op;
-
- for (op = i.operands; --op >= 0; )
- /* Reject eight bit registers, except where the template
- requires them. (eg. movzb) */
- if ((i.types[op] & Reg8) != 0
- && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
- {
- as_bad (_("`%%%s' not allowed with `%s%c'"),
- i.op[op].regs->reg_name,
- i.tm.name,
- i.suffix);
- return;
- }
- /* Warn if the e prefix on a general reg is missing. */
- else if (((i.types[op] & Reg16) != 0
- || (i.types[op] & Reg32) != 0)
- && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
- {
- /* Prohibit these changes in the 64bit mode, since
- the lowering is more complicated. */
- as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
- i.op[op].regs->reg_name,
- i.suffix);
- }
- }
- else if (i.suffix == WORD_MNEM_SUFFIX)
- {
- int op;
- for (op = i.operands; --op >= 0;)
- /* Reject eight bit registers, except where the template
- requires them. (eg. movzb) */
- if ((i.types[op] & Reg8) != 0
- && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
- {
- as_bad (_("`%%%s' not allowed with `%s%c'"),
- i.op[op].regs->reg_name,
- i.tm.name,
- i.suffix);
- return;
+ {
+ i.rm.regmem = NO_BASE_REGISTER;
+ i.types[op] = Disp32;
+ }
}
- /* Warn if the e prefix on a general reg is present. */
- else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && (i.types[op] & Reg32) != 0
- && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
+ else /* !i.base_reg && i.index_reg */
{
- /* Prohibit these changes in the 64bit mode, since
- the lowering is more complicated. */
- if (flag_code == CODE_64BIT)
- as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
- i.op[op].regs->reg_name,
- i.suffix);
+ i.sib.index = i.index_reg->reg_num;
+ i.sib.base = NO_BASE_REGISTER;
+ i.sib.scale = i.log2_scale_factor;
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.types[op] &= ~Disp;
+ if (flag_code != CODE_64BIT)
+ i.types[op] |= Disp32; /* Must be 32 bit */
else
-#if REGISTER_WARNINGS
- as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
- (i.op[op].regs - 8)->reg_name,
- i.op[op].regs->reg_name,
- i.suffix);
-#endif
+ i.types[op] |= Disp32S;
+ if ((i.index_reg->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTY;
}
- }
- else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
- /* Do nothing if the instruction is going to ignore the prefix. */
- ;
- else
- abort ();
- }
- else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
- {
- i.suffix = stackop_size;
- }
- /* Make still unresolved immediate matches conform to size of immediate
- given in i.suffix. Note: overlap2 cannot be an immediate! */
- if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
- && overlap0 != Imm8 && overlap0 != Imm8S
- && overlap0 != Imm16 && overlap0 != Imm32S
- && overlap0 != Imm32 && overlap0 != Imm64)
- {
- if (i.suffix)
- {
- overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
- (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
- (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
- }
- else if (overlap0 == (Imm16 | Imm32S | Imm32)
- || overlap0 == (Imm16 | Imm32)
- || overlap0 == (Imm16 | Imm32S))
- {
- overlap0 =
- ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
- }
- if (overlap0 != Imm8 && overlap0 != Imm8S
- && overlap0 != Imm16 && overlap0 != Imm32S
- && overlap0 != Imm32 && overlap0 != Imm64)
- {
- as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
- return;
- }
- }
- if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
- && overlap1 != Imm8 && overlap1 != Imm8S
- && overlap1 != Imm16 && overlap1 != Imm32S
- && overlap1 != Imm32 && overlap1 != Imm64)
- {
- if (i.suffix)
- {
- overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
- (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
- (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
- }
- else if (overlap1 == (Imm16 | Imm32 | Imm32S)
- || overlap1 == (Imm16 | Imm32)
- || overlap1 == (Imm16 | Imm32S))
- {
- overlap1 =
- ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
- }
- if (overlap1 != Imm8 && overlap1 != Imm8S
- && overlap1 != Imm16 && overlap1 != Imm32S
- && overlap1 != Imm32 && overlap1 != Imm64)
- {
- as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
- return;
- }
- }
- assert ((overlap2 & Imm) == 0);
-
- i.types[0] = overlap0;
- if (overlap0 & ImplicitRegister)
- i.reg_operands--;
- if (overlap0 & Imm1)
- i.imm_operands = 0; /* kludge for shift insns. */
-
- i.types[1] = overlap1;
- if (overlap1 & ImplicitRegister)
- i.reg_operands--;
-
- i.types[2] = overlap2;
- if (overlap2 & ImplicitRegister)
- i.reg_operands--;
-
- /* Finalize opcode. First, we change the opcode based on the operand
- size given by i.suffix: We need not change things for byte insns. */
+ }
+ /* RIP addressing for 64bit mode. */
+ else if (i.base_reg->reg_type == BaseIndex)
+ {
+ i.rm.regmem = NO_BASE_REGISTER;
+ i.types[op] &= ~ Disp;
+ i.types[op] |= Disp32S;
+ i.flags[op] = Operand_PCrel;
+ if (! i.disp_operands)
+ fake_zero_displacement = 1;
+ }
+ else if (i.base_reg->reg_type & Reg16)
+ {
+ switch (i.base_reg->reg_num)
+ {
+ case 3: /* (%bx) */
+ if (i.index_reg == 0)
+ i.rm.regmem = 7;
+ else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
+ i.rm.regmem = i.index_reg->reg_num - 6;
+ break;
+ case 5: /* (%bp) */
+ default_seg = &ss;
+ if (i.index_reg == 0)
+ {
+ i.rm.regmem = 6;
+ if ((i.types[op] & Disp) == 0)
+ {
+ /* fake (%bp) into 0(%bp) */
+ i.types[op] |= Disp8;
+ fake_zero_displacement = 1;
+ }
+ }
+ else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
+ i.rm.regmem = i.index_reg->reg_num - 6 + 2;
+ break;
+ default: /* (%si) -> 4 or (%di) -> 5 */
+ i.rm.regmem = i.base_reg->reg_num - 6 + 4;
+ }
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ }
+ else /* i.base_reg and 32/64 bit mode */
+ {
+ if (flag_code == CODE_64BIT
+ && (i.types[op] & Disp))
+ i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
+
+ i.rm.regmem = i.base_reg->reg_num;
+ if ((i.base_reg->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ i.sib.base = i.base_reg->reg_num;
+ /* x86-64 ignores REX prefix bit here to avoid decoder
+ complications. */
+ if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
+ {
+ default_seg = &ss;
+ if (i.disp_operands == 0)
+ {
+ fake_zero_displacement = 1;
+ i.types[op] |= Disp8;
+ }
+ }
+ else if (i.base_reg->reg_num == ESP_REG_NUM)
+ {
+ default_seg = &ss;
+ }
+ i.sib.scale = i.log2_scale_factor;
+ if (i.index_reg == 0)
+ {
+ /* <disp>(%esp) becomes two byte modrm with no index
+ register. We've already stored the code for esp
+ in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
+ Any base register besides %esp will not use the
+ extra modrm byte. */
+ i.sib.index = NO_INDEX_REGISTER;
+#if !SCALE1_WHEN_NO_INDEX
+ /* Another case where we force the second modrm byte. */
+ if (i.log2_scale_factor)
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+#endif
+ }
+ else
+ {
+ i.sib.index = i.index_reg->reg_num;
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ if ((i.index_reg->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTY;
+ }
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ }
- if (!i.suffix && (i.tm.opcode_modifier & W))
- {
- as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
- return;
- }
+ if (fake_zero_displacement)
+ {
+ /* Fakes a zero displacement assuming that i.types[op]
+ holds the correct displacement size. */
+ expressionS *exp;
+
+ assert (i.op[op].disps == 0);
+ exp = &disp_expressions[i.disp_operands++];
+ i.op[op].disps = exp;
+ exp->X_op = O_constant;
+ exp->X_add_number = 0;
+ exp->X_add_symbol = (symbolS *) 0;
+ exp->X_op_symbol = (symbolS *) 0;
+ }
+ }
- /* For movzx and movsx, need to check the register type. */
- if (intel_syntax
- && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
- if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
+ /* Fill in i.rm.reg or i.rm.regmem field with register operand
+ (if any) based on i.tm.extension_opcode. Again, we must be
+ careful to make sure that segment/control/debug/test/MMX
+ registers are coded into the i.rm.reg field. */
+ if (i.reg_operands)
{
- unsigned int prefix = DATA_PREFIX_OPCODE;
+ unsigned int op =
+ ((i.types[0]
+ & (Reg | RegMMX | RegXMM
+ | SReg2 | SReg3
+ | Control | Debug | Test))
+ ? 0
+ : ((i.types[1]
+ & (Reg | RegMMX | RegXMM
+ | SReg2 | SReg3
+ | Control | Debug | Test))
+ ? 1
+ : 2));
+ /* If there is an extension opcode to put here, the register
+ number must be put into the regmem field. */
+ if (i.tm.extension_opcode != None)
+ {
+ i.rm.regmem = i.op[op].regs->reg_num;
+ if ((i.op[op].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTZ;
+ }
+ else
+ {
+ i.rm.reg = i.op[op].regs->reg_num;
+ if ((i.op[op].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_EXTX;
+ }
- if ((i.op[1].regs->reg_type & Reg16) != 0)
- if (!add_prefix (prefix))
- return;
+ /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
+ must set it to 3 to indicate this is a register operand
+ in the regmem field. */
+ if (!i.mem_operands)
+ i.rm.mode = 3;
}
- if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
- {
- /* It's not a byte, select word/dword operation. */
- if (i.tm.opcode_modifier & W)
- {
- if (i.tm.opcode_modifier & ShortForm)
- i.tm.base_opcode |= 8;
- else
- i.tm.base_opcode |= 1;
- }
- /* Now select between word & dword operations via the operand
- size prefix, except for instructions that will ignore this
- prefix anyway. */
- if (i.suffix != QWORD_MNEM_SUFFIX
- && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
- && !(i.tm.opcode_modifier & IgnoreSize))
- {
- unsigned int prefix = DATA_PREFIX_OPCODE;
- if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
- prefix = ADDR_PREFIX_OPCODE;
+ /* Fill in i.rm.reg field with extension opcode (if any). */
+ if (i.tm.extension_opcode != None)
+ i.rm.reg = i.tm.extension_opcode;
+ }
+ return default_seg;
+}
- if (! add_prefix (prefix))
- return;
- }
+static void
+output_branch ()
+{
+ char *p;
+ int code16;
+ int prefix;
+ relax_substateT subtype;
+ symbolS *sym;
+ offsetT off;
+
+ code16 = 0;
+ if (flag_code == CODE_16BIT)
+ code16 = CODE16;
+
+ prefix = 0;
+ if (i.prefix[DATA_PREFIX] != 0)
+ {
+ prefix = 1;
+ i.prefixes -= 1;
+ code16 ^= CODE16;
+ }
+ /* Pentium4 branch hints. */
+ if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
+ || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
+ {
+ prefix++;
+ i.prefixes--;
+ }
+ if (i.prefix[REX_PREFIX] != 0)
+ {
+ prefix++;
+ i.prefixes--;
+ }
- /* Set mode64 for an operand. */
- if (i.suffix == QWORD_MNEM_SUFFIX
- && !(i.tm.opcode_modifier & NoRex64))
- {
- i.rex.mode64 = 1;
- if (flag_code < CODE_64BIT)
- {
- as_bad (_("64bit operations available only in 64bit modes."));
- return;
- }
- }
+ if (i.prefixes != 0 && !intel_syntax)
+ as_warn (_("skipping prefixes on this instruction"));
+
+ /* It's always a symbol; End frag & setup for relax.
+ Make sure there is enough room in this frag for the largest
+ instruction we may generate in md_convert_frag. This is 2
+ bytes for the opcode and room for the prefix and largest
+ displacement. */
+ frag_grow (prefix + 2 + 4);
+ /* Prefix and 1 opcode byte go in fr_fix. */
+ p = frag_more (prefix + 1);
+ if (i.prefix[DATA_PREFIX] != 0)
+ *p++ = DATA_PREFIX_OPCODE;
+ if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
+ || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
+ *p++ = i.prefix[SEG_PREFIX];
+ if (i.prefix[REX_PREFIX] != 0)
+ *p++ = i.prefix[REX_PREFIX];
+ *p = i.tm.base_opcode;
+
+ if ((unsigned char) *p == JUMP_PC_RELATIVE)
+ subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
+ else if ((cpu_arch_flags & Cpu386) != 0)
+ subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
+ else
+ subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
+ subtype |= code16;
- /* Size floating point instruction. */
- if (i.suffix == LONG_MNEM_SUFFIX)
- {
- if (i.tm.opcode_modifier & FloatMF)
- i.tm.base_opcode ^= 4;
- }
- }
+ sym = i.op[0].disps->X_add_symbol;
+ off = i.op[0].disps->X_add_number;
- if (i.tm.opcode_modifier & ImmExt)
- {
- /* These AMD 3DNow! and Intel Katmai New Instructions have an
- opcode suffix which is coded in the same place as an 8-bit
- immediate field would be. Here we fake an 8-bit immediate
- operand from the opcode suffix stored in tm.extension_opcode. */
+ if (i.op[0].disps->X_op != O_constant
+ && i.op[0].disps->X_op != O_symbol)
+ {
+ /* Handle complex expressions. */
+ sym = make_expr_symbol (i.op[0].disps);
+ off = 0;
+ }
- expressionS *exp;
+ /* 1 possible extra opcode + 4 byte displacement go in var part.
+ Pass reloc in fr_var. */
+ frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
+}
- assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
+static void
+output_jump ()
+{
+ char *p;
+ int size;
+ fixS *fixP;
- exp = &im_expressions[i.imm_operands++];
- i.op[i.operands].imms = exp;
- i.types[i.operands++] = Imm8;
- exp->X_op = O_constant;
- exp->X_add_number = i.tm.extension_opcode;
- i.tm.extension_opcode = None;
- }
+ if (i.tm.opcode_modifier & JumpByte)
+ {
+ /* This is a loop or jecxz type instruction. */
+ size = 1;
+ if (i.prefix[ADDR_PREFIX] != 0)
+ {
+ FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
+ i.prefixes -= 1;
+ }
+ /* Pentium4 branch hints. */
+ if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
+ || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
+ {
+ FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
+ i.prefixes--;
+ }
+ }
+ else
+ {
+ int code16;
- /* For insns with operands there are more diddles to do to the opcode. */
- if (i.operands)
- {
- /* Default segment register this instruction will use
- for memory accesses. 0 means unknown.
- This is only for optimizing out unnecessary segment overrides. */
- const seg_entry *default_seg = 0;
-
- /* The imul $imm, %reg instruction is converted into
- imul $imm, %reg, %reg, and the clr %reg instruction
- is converted into xor %reg, %reg. */
- if (i.tm.opcode_modifier & regKludge)
- {
- unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
- /* Pretend we saw the extra register operand. */
- assert (i.op[first_reg_op + 1].regs == 0);
- i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
- i.types[first_reg_op + 1] = i.types[first_reg_op];
- i.reg_operands = 2;
- }
+ code16 = 0;
+ if (flag_code == CODE_16BIT)
+ code16 = CODE16;
- if (i.tm.opcode_modifier & ShortForm)
- {
- /* The register or float register operand is in operand 0 or 1. */
- unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
- /* Register goes in low 3 bits of opcode. */
- i.tm.base_opcode |= i.op[op].regs->reg_num;
- if (i.op[op].regs->reg_flags & RegRex)
- i.rex.extZ = 1;
- if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
- {
- /* Warn about some common errors, but press on regardless.
- The first case can be generated by gcc (<= 2.8.1). */
- if (i.operands == 2)
- {
- /* Reversed arguments on faddp, fsubp, etc. */
- as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
- i.op[1].regs->reg_name,
- i.op[0].regs->reg_name);
- }
- else
- {
- /* Extraneous `l' suffix on fp insn. */
- as_warn (_("translating to `%s %%%s'"), i.tm.name,
- i.op[0].regs->reg_name);
- }
- }
- }
- else if (i.tm.opcode_modifier & Modrm)
- {
- /* The opcode is completed (modulo i.tm.extension_opcode which
- must be put into the modrm byte).
- Now, we make the modrm & index base bytes based on all the
- info we've collected. */
-
- /* i.reg_operands MUST be the number of real register operands;
- implicit registers do not count. */
- if (i.reg_operands == 2)
- {
- unsigned int source, dest;
- source = ((i.types[0]
- & (Reg | RegMMX | RegXMM
- | SReg2 | SReg3
- | Control | Debug | Test))
- ? 0 : 1);
- dest = source + 1;
-
- i.rm.mode = 3;
- /* One of the register operands will be encoded in the
- i.tm.reg field, the other in the combined i.tm.mode
- and i.tm.regmem fields. If no form of this
- instruction supports a memory destination operand,
- then we assume the source operand may sometimes be
- a memory operand and so we need to store the
- destination in the i.rm.reg field. */
- if ((i.tm.operand_types[dest] & AnyMem) == 0)
- {
- i.rm.reg = i.op[dest].regs->reg_num;
- i.rm.regmem = i.op[source].regs->reg_num;
- if (i.op[dest].regs->reg_flags & RegRex)
- i.rex.extX = 1;
- if (i.op[source].regs->reg_flags & RegRex)
- i.rex.extZ = 1;
- }
- else
- {
- i.rm.reg = i.op[source].regs->reg_num;
- i.rm.regmem = i.op[dest].regs->reg_num;
- if (i.op[dest].regs->reg_flags & RegRex)
- i.rex.extZ = 1;
- if (i.op[source].regs->reg_flags & RegRex)
- i.rex.extX = 1;
- }
- }
- else
- { /* If it's not 2 reg operands... */
- if (i.mem_operands)
- {
- unsigned int fake_zero_displacement = 0;
- unsigned int op = ((i.types[0] & AnyMem)
- ? 0
- : (i.types[1] & AnyMem) ? 1 : 2);
+ if (i.prefix[DATA_PREFIX] != 0)
+ {
+ FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
+ i.prefixes -= 1;
+ code16 ^= CODE16;
+ }
- default_seg = &ds;
+ size = 4;
+ if (code16)
+ size = 2;
+ }
- if (! i.base_reg)
- {
- i.rm.mode = 0;
- if (! i.disp_operands)
- fake_zero_displacement = 1;
- if (! i.index_reg)
- {
- /* Operand is just <disp> */
- if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
- {
- i.rm.regmem = NO_BASE_REGISTER_16;
- i.types[op] &= ~Disp;
- i.types[op] |= Disp16;
- }
- else if (flag_code != CODE_64BIT)
- {
- i.rm.regmem = NO_BASE_REGISTER;
- i.types[op] &= ~Disp;
- i.types[op] |= Disp32;
- }
- else
- {
- /* 64bit mode overwrites the 32bit
- absolute addressing by RIP relative
- addressing and absolute addressing
- is encoded by one of the redundant
- SIB forms. */
-
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.sib.base = NO_BASE_REGISTER;
- i.sib.index = NO_INDEX_REGISTER;
- i.types[op] &= ~Disp;
- i.types[op] |= Disp32S;
- }
- }
- else /* ! i.base_reg && i.index_reg */
- {
- i.sib.index = i.index_reg->reg_num;
- i.sib.base = NO_BASE_REGISTER;
- i.sib.scale = i.log2_scale_factor;
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.types[op] &= ~Disp;
- if (flag_code != CODE_64BIT)
- i.types[op] |= Disp32; /* Must be 32 bit */
- else
- i.types[op] |= Disp32S;
- if (i.index_reg->reg_flags & RegRex)
- i.rex.extY = 1;
- }
- }
- /* RIP addressing for 64bit mode. */
- else if (i.base_reg->reg_type == BaseIndex)
- {
- i.rm.regmem = NO_BASE_REGISTER;
- i.types[op] &= ~Disp;
- i.types[op] |= Disp32S;
- i.flags[op] = Operand_PCrel;
- }
- else if (i.base_reg->reg_type & Reg16)
- {
- switch (i.base_reg->reg_num)
- {
- case 3: /* (%bx) */
- if (! i.index_reg)
- i.rm.regmem = 7;
- else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
- i.rm.regmem = i.index_reg->reg_num - 6;
- break;
- case 5: /* (%bp) */
- default_seg = &ss;
- if (! i.index_reg)
- {
- i.rm.regmem = 6;
- if ((i.types[op] & Disp) == 0)
- {
- /* fake (%bp) into 0(%bp) */
- i.types[op] |= Disp8;
- fake_zero_displacement = 1;
- }
- }
- else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
- i.rm.regmem = i.index_reg->reg_num - 6 + 2;
- break;
- default: /* (%si) -> 4 or (%di) -> 5 */
- i.rm.regmem = i.base_reg->reg_num - 6 + 4;
- }
- i.rm.mode = mode_from_disp_size (i.types[op]);
- }
- else /* i.base_reg and 32/64 bit mode */
- {
- if (flag_code == CODE_64BIT
- && (i.types[op] & Disp))
- {
- if (i.types[op] & Disp8)
- i.types[op] = Disp8 | Disp32S;
- else
- i.types[op] = Disp32S;
- }
- i.rm.regmem = i.base_reg->reg_num;
- if (i.base_reg->reg_flags & RegRex)
- i.rex.extZ = 1;
- i.sib.base = i.base_reg->reg_num;
- /* x86-64 ignores REX prefix bit here to avoid
- decoder complications. */
- if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
- {
- default_seg = &ss;
- if (i.disp_operands == 0)
- {
- fake_zero_displacement = 1;
- i.types[op] |= Disp8;
- }
- }
- else if (i.base_reg->reg_num == ESP_REG_NUM)
- {
- default_seg = &ss;
- }
- i.sib.scale = i.log2_scale_factor;
- if (! i.index_reg)
- {
- /* <disp>(%esp) becomes two byte modrm
- with no index register. We've already
- stored the code for esp in i.rm.regmem
- ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
- base register besides %esp will not use
- the extra modrm byte. */
- i.sib.index = NO_INDEX_REGISTER;
-#if ! SCALE1_WHEN_NO_INDEX
- /* Another case where we force the second
- modrm byte. */
- if (i.log2_scale_factor)
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
-#endif
- }
- else
- {
- i.sib.index = i.index_reg->reg_num;
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- if (i.index_reg->reg_flags & RegRex)
- i.rex.extY = 1;
- }
- i.rm.mode = mode_from_disp_size (i.types[op]);
- }
+ if (i.prefix[REX_PREFIX] != 0)
+ {
+ FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
+ i.prefixes -= 1;
+ }
- if (fake_zero_displacement)
- {
- /* Fakes a zero displacement assuming that i.types[op]
- holds the correct displacement size. */
- expressionS *exp;
-
- assert (i.op[op].disps == 0);
- exp = &disp_expressions[i.disp_operands++];
- i.op[op].disps = exp;
- exp->X_op = O_constant;
- exp->X_add_number = 0;
- exp->X_add_symbol = (symbolS *) 0;
- exp->X_op_symbol = (symbolS *) 0;
- }
- }
+ if (i.prefixes != 0 && !intel_syntax)
+ as_warn (_("skipping prefixes on this instruction"));
- /* Fill in i.rm.reg or i.rm.regmem field with register
- operand (if any) based on i.tm.extension_opcode.
- Again, we must be careful to make sure that
- segment/control/debug/test/MMX registers are coded
- into the i.rm.reg field. */
- if (i.reg_operands)
- {
- unsigned int op =
- ((i.types[0]
- & (Reg | RegMMX | RegXMM
- | SReg2 | SReg3
- | Control | Debug | Test))
- ? 0
- : ((i.types[1]
- & (Reg | RegMMX | RegXMM
- | SReg2 | SReg3
- | Control | Debug | Test))
- ? 1
- : 2));
- /* If there is an extension opcode to put here, the
- register number must be put into the regmem field. */
- if (i.tm.extension_opcode != None)
- {
- i.rm.regmem = i.op[op].regs->reg_num;
- if (i.op[op].regs->reg_flags & RegRex)
- i.rex.extZ = 1;
- }
- else
- {
- i.rm.reg = i.op[op].regs->reg_num;
- if (i.op[op].regs->reg_flags & RegRex)
- i.rex.extX = 1;
- }
+ p = frag_more (1 + size);
+ *p++ = i.tm.base_opcode;
- /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
- we must set it to 3 to indicate this is a register
- operand in the regmem field. */
- if (!i.mem_operands)
- i.rm.mode = 3;
- }
+ fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
+ i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
- /* Fill in i.rm.reg field with extension opcode (if any). */
- if (i.tm.extension_opcode != None)
- i.rm.reg = i.tm.extension_opcode;
- }
- }
- else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
- {
- if (i.tm.base_opcode == POP_SEG_SHORT
- && i.op[0].regs->reg_num == 1)
- {
- as_bad (_("you can't `pop %%cs'"));
- return;
- }
- i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
- if (i.op[0].regs->reg_flags & RegRex)
- i.rex.extZ = 1;
- }
- else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
- {
- default_seg = &ds;
- }
- else if ((i.tm.opcode_modifier & IsString) != 0)
- {
- /* For the string instructions that allow a segment override
- on one of their operands, the default segment is ds. */
- default_seg = &ds;
- }
+ /* All jumps handled here are signed, but don't use a signed limit
+ check for 32 and 16 bit jumps as we want to allow wrap around at
+ 4G and 64k respectively. */
+ if (size == 1)
+ fixP->fx_signed = 1;
+}
- /* If a segment was explicitly specified,
- and the specified segment is not the default,
- use an opcode prefix to select it.
- If we never figured out what the default segment is,
- then default_seg will be zero at this point,
- and the specified segment prefix will always be used. */
- if ((i.seg[0]) && (i.seg[0] != default_seg))
- {
- if (! add_prefix (i.seg[0]->seg_prefix))
- return;
- }
- }
- else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
- {
- /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
- as_warn (_("translating to `%sp'"), i.tm.name);
- }
- }
+static void
+output_interseg_jump ()
+{
+ char *p;
+ int size;
+ int prefix;
+ int code16;
- /* Handle conversion of 'int $3' --> special int3 insn. */
- if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
+ code16 = 0;
+ if (flag_code == CODE_16BIT)
+ code16 = CODE16;
+
+ prefix = 0;
+ if (i.prefix[DATA_PREFIX] != 0)
{
- i.tm.base_opcode = INT3_OPCODE;
- i.imm_operands = 0;
+ prefix = 1;
+ i.prefixes -= 1;
+ code16 ^= CODE16;
}
-
- if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
- && i.op[0].disps->X_op == O_constant)
+ if (i.prefix[REX_PREFIX] != 0)
{
- /* Convert "jmp constant" (and "call constant") to a jump (call) to
- the absolute address given by the constant. Since ix86 jumps and
- calls are pc relative, we need to generate a reloc. */
- i.op[0].disps->X_add_symbol = &abs_symbol;
- i.op[0].disps->X_op = O_symbol;
+ prefix++;
+ i.prefixes -= 1;
}
- if (i.tm.opcode_modifier & Rex64)
- i.rex.mode64 = 1;
+ size = 4;
+ if (code16)
+ size = 2;
- /* For 8bit registers we would need an empty rex prefix.
- Also in the case instruction is already having prefix,
- we need to convert old registers to new ones. */
+ if (i.prefixes != 0 && !intel_syntax)
+ as_warn (_("skipping prefixes on this instruction"));
- if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
- || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
- || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
- && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
+ /* 1 opcode; 2 segment; offset */
+ p = frag_more (prefix + 1 + 2 + size);
+
+ if (i.prefix[DATA_PREFIX] != 0)
+ *p++ = DATA_PREFIX_OPCODE;
+
+ if (i.prefix[REX_PREFIX] != 0)
+ *p++ = i.prefix[REX_PREFIX];
+
+ *p++ = i.tm.base_opcode;
+ if (i.op[1].imms->X_op == O_constant)
{
- int x;
- i.rex.empty = 1;
- for (x = 0; x < 2; x++)
+ offsetT n = i.op[1].imms->X_add_number;
+
+ if (size == 2
+ && !fits_in_unsigned_word (n)
+ && !fits_in_signed_word (n))
+ {
+ as_bad (_("16-bit jump out of range"));
+ return;
+ }
+ md_number_to_chars (p, n, size);
+ }
+ else
+ fix_new_exp (frag_now, p - frag_now->fr_literal, size,
+ i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
+ if (i.op[0].imms->X_op != O_constant)
+ as_bad (_("can't handle non absolute segment in `%s'"),
+ i.tm.name);
+ md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
+}
+
+static void
+output_insn ()
+{
+ fragS *insn_start_frag;
+ offsetT insn_start_off;
+
+ /* Tie dwarf2 debug info to the address at the start of the insn.
+ We can't do this after the insn has been output as the current
+ frag may have been closed off. eg. by frag_var. */
+ dwarf2_emit_insn (0);
+
+ insn_start_frag = frag_now;
+ insn_start_off = frag_now_fix ();
+
+ /* Output jumps. */
+ if (i.tm.opcode_modifier & Jump)
+ output_branch ();
+ else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
+ output_jump ();
+ else if (i.tm.opcode_modifier & JumpInterSegment)
+ output_interseg_jump ();
+ else
+ {
+ /* Output normal instructions here. */
+ char *p;
+ unsigned char *q;
+
+ /* All opcodes on i386 have either 1 or 2 bytes. We may use one
+ more higher byte to specify a prefix the instruction
+ requires. */
+ if ((i.tm.base_opcode & 0xff0000) != 0)
{
- /* Look for 8bit operand that does use old registers. */
- if (i.types[x] & Reg8
- && !(i.op[x].regs->reg_flags & RegRex64))
+ if ((i.tm.cpu_flags & CpuPadLock) != 0)
{
- /* In case it is "hi" register, give up. */
- if (i.op[x].regs->reg_num > 3)
- as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
- i.op[x].regs->reg_name);
+ unsigned int prefix;
+ prefix = (i.tm.base_opcode >> 16) & 0xff;
- /* Otherwise it is equivalent to the extended register.
- Since the encoding don't change this is merely cosmetical
- cleanup for debug output. */
+ if (prefix != REPE_PREFIX_OPCODE
+ || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
+ add_prefix (prefix);
+ }
+ else
+ add_prefix ((i.tm.base_opcode >> 16) & 0xff);
+ }
- i.op[x].regs = i.op[x].regs + 8;
+ /* The prefix bytes. */
+ for (q = i.prefix;
+ q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
+ q++)
+ {
+ if (*q)
+ {
+ p = frag_more (1);
+ md_number_to_chars (p, (valueT) *q, 1);
+ }
+ }
+
+ /* Now the opcode; be careful about word order here! */
+ if (fits_in_unsigned_byte (i.tm.base_opcode))
+ {
+ FRAG_APPEND_1_CHAR (i.tm.base_opcode);
+ }
+ else
+ {
+ p = frag_more (2);
+
+ /* Put out high byte first: can't use md_number_to_chars! */
+ *p++ = (i.tm.base_opcode >> 8) & 0xff;
+ *p = i.tm.base_opcode & 0xff;
+ }
+
+ /* Now the modrm byte and sib byte (if present). */
+ if (i.tm.opcode_modifier & Modrm)
+ {
+ p = frag_more (1);
+ md_number_to_chars (p,
+ (valueT) (i.rm.regmem << 0
+ | i.rm.reg << 3
+ | i.rm.mode << 6),
+ 1);
+ /* If i.rm.regmem == ESP (4)
+ && i.rm.mode != (Register mode)
+ && not 16 bit
+ ==> need second modrm byte. */
+ if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
+ && i.rm.mode != 3
+ && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
+ {
+ p = frag_more (1);
+ md_number_to_chars (p,
+ (valueT) (i.sib.base << 0
+ | i.sib.index << 3
+ | i.sib.scale << 6),
+ 1);
}
}
+
+ if (i.disp_operands)
+ output_disp (insn_start_frag, insn_start_off);
+
+ if (i.imm_operands)
+ output_imm (insn_start_frag, insn_start_off);
}
- if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
- add_prefix (0x40
- | (i.rex.mode64 ? 8 : 0)
- | (i.rex.extX ? 4 : 0)
- | (i.rex.extY ? 2 : 0)
- | (i.rex.extZ ? 1 : 0));
+#ifdef DEBUG386
+ if (flag_debug)
+ {
+ pi (line, &i);
+ }
+#endif /* DEBUG386 */
+}
- /* We are ready to output the insn. */
- {
- register char *p;
+static void
+output_disp (insn_start_frag, insn_start_off)
+ fragS *insn_start_frag;
+ offsetT insn_start_off;
+{
+ char *p;
+ unsigned int n;
- /* Output jumps. */
- if (i.tm.opcode_modifier & Jump)
- {
- int code16;
- int prefix;
+ for (n = 0; n < i.operands; n++)
+ {
+ if (i.types[n] & Disp)
+ {
+ if (i.op[n].disps->X_op == O_constant)
+ {
+ int size;
+ offsetT val;
+
+ size = 4;
+ if (i.types[n] & (Disp8 | Disp16 | Disp64))
+ {
+ size = 2;
+ if (i.types[n] & Disp8)
+ size = 1;
+ if (i.types[n] & Disp64)
+ size = 8;
+ }
+ val = offset_in_range (i.op[n].disps->X_add_number,
+ size);
+ p = frag_more (size);
+ md_number_to_chars (p, val, size);
+ }
+ else
+ {
+ enum bfd_reloc_code_real reloc_type;
+ int size = 4;
+ int sign = 0;
+ int pcrel = (i.flags[n] & Operand_PCrel) != 0;
+
+ /* The PC relative address is computed relative
+ to the instruction boundary, so in case immediate
+ fields follows, we need to adjust the value. */
+ if (pcrel && i.imm_operands)
+ {
+ int imm_size = 4;
+ unsigned int n1;
- code16 = 0;
- if (flag_code == CODE_16BIT)
- code16 = CODE16;
+ for (n1 = 0; n1 < i.operands; n1++)
+ if (i.types[n1] & Imm)
+ {
+ if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
+ {
+ imm_size = 2;
+ if (i.types[n1] & (Imm8 | Imm8S))
+ imm_size = 1;
+ if (i.types[n1] & Imm64)
+ imm_size = 8;
+ }
+ break;
+ }
+ /* We should find the immediate. */
+ if (n1 == i.operands)
+ abort ();
+ i.op[n].disps->X_add_number -= imm_size;
+ }
- prefix = 0;
- if (i.prefix[DATA_PREFIX])
- {
- prefix = 1;
- i.prefixes -= 1;
- code16 ^= CODE16;
- }
- if (i.prefix[REX_PREFIX])
- {
- prefix++;
- i.prefixes--;
- }
+ if (i.types[n] & Disp32S)
+ sign = 1;
- if (i.prefixes != 0 && !intel_syntax)
- as_warn (_("skipping prefixes on this instruction"));
-
- /* It's always a symbol; End frag & setup for relax.
- Make sure there is enough room in this frag for the largest
- instruction we may generate in md_convert_frag. This is 2
- bytes for the opcode and room for the prefix and largest
- displacement. */
- frag_grow (prefix + 2 + 4);
- insn_size += prefix + 1;
- /* Prefix and 1 opcode byte go in fr_fix. */
- p = frag_more (prefix + 1);
- if (i.prefix[DATA_PREFIX])
- *p++ = DATA_PREFIX_OPCODE;
- if (i.prefix[REX_PREFIX])
- *p++ = i.prefix[REX_PREFIX];
- *p = i.tm.base_opcode;
- /* 1 possible extra opcode + displacement go in var part.
- Pass reloc in fr_var. */
- frag_var (rs_machine_dependent,
- 1 + 4,
- i.disp_reloc[0],
- ((unsigned char) *p == JUMP_PC_RELATIVE
- ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
- : ((cpu_arch_flags & Cpu386) != 0
- ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
- : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
- i.op[0].disps->X_add_symbol,
- i.op[0].disps->X_add_number,
- p);
- }
- else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
- {
- int size;
+ if (i.types[n] & (Disp16 | Disp64))
+ {
+ size = 2;
+ if (i.types[n] & Disp64)
+ size = 8;
+ }
- if (i.tm.opcode_modifier & JumpByte)
- {
- /* This is a loop or jecxz type instruction. */
- size = 1;
- if (i.prefix[ADDR_PREFIX])
- {
- insn_size += 1;
- FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
- i.prefixes -= 1;
- }
- }
- else
- {
- int code16;
+ p = frag_more (size);
+ reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
+ if (reloc_type == BFD_RELOC_32
+ && GOT_symbol
+ && GOT_symbol == i.op[n].disps->X_add_symbol
+ && (i.op[n].disps->X_op == O_symbol
+ || (i.op[n].disps->X_op == O_add
+ && ((symbol_get_value_expression
+ (i.op[n].disps->X_op_symbol)->X_op)
+ == O_subtract))))
+ {
+ offsetT add;
+
+ if (insn_start_frag == frag_now)
+ add = (p - frag_now->fr_literal) - insn_start_off;
+ else
+ {
+ fragS *fr;
+
+ add = insn_start_frag->fr_fix - insn_start_off;
+ for (fr = insn_start_frag->fr_next;
+ fr && fr != frag_now; fr = fr->fr_next)
+ add += fr->fr_fix;
+ add += p - frag_now->fr_literal;
+ }
- code16 = 0;
- if (flag_code == CODE_16BIT)
- code16 = CODE16;
+ /* We don't support dynamic linking on x86-64 yet. */
+ if (flag_code == CODE_64BIT)
+ abort ();
+ reloc_type = BFD_RELOC_386_GOTPC;
+ i.op[n].disps->X_add_number += add;
+ }
+ fix_new_exp (frag_now, p - frag_now->fr_literal, size,
+ i.op[n].disps, pcrel, reloc_type);
+ }
+ }
+ }
+}
- if (i.prefix[DATA_PREFIX])
- {
- insn_size += 1;
- FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
- i.prefixes -= 1;
- code16 ^= CODE16;
- }
+static void
+output_imm (insn_start_frag, insn_start_off)
+ fragS *insn_start_frag;
+ offsetT insn_start_off;
+{
+ char *p;
+ unsigned int n;
- size = 4;
- if (code16)
- size = 2;
- }
+ for (n = 0; n < i.operands; n++)
+ {
+ if (i.types[n] & Imm)
+ {
+ if (i.op[n].imms->X_op == O_constant)
+ {
+ int size;
+ offsetT val;
- if (i.prefix[REX_PREFIX])
- {
- FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
- insn_size++;
- i.prefixes -= 1;
- }
+ size = 4;
+ if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
+ {
+ size = 2;
+ if (i.types[n] & (Imm8 | Imm8S))
+ size = 1;
+ else if (i.types[n] & Imm64)
+ size = 8;
+ }
+ val = offset_in_range (i.op[n].imms->X_add_number,
+ size);
+ p = frag_more (size);
+ md_number_to_chars (p, val, size);
+ }
+ else
+ {
+ /* Not absolute_section.
+ Need a 32-bit fixup (don't support 8bit
+ non-absolute imms). Try to support other
+ sizes ... */
+ enum bfd_reloc_code_real reloc_type;
+ int size = 4;
+ int sign = 0;
+
+ if ((i.types[n] & (Imm32S))
+ && (i.suffix == QWORD_MNEM_SUFFIX
+ || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
+ sign = 1;
+ if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
+ {
+ size = 2;
+ if (i.types[n] & (Imm8 | Imm8S))
+ size = 1;
+ if (i.types[n] & Imm64)
+ size = 8;
+ }
- if (i.prefixes != 0 && !intel_syntax)
- as_warn (_("skipping prefixes on this instruction"));
+ p = frag_more (size);
+ reloc_type = reloc (size, 0, sign, i.reloc[n]);
+
+ /* This is tough to explain. We end up with this one if we
+ * have operands that look like
+ * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
+ * obtain the absolute address of the GOT, and it is strongly
+ * preferable from a performance point of view to avoid using
+ * a runtime relocation for this. The actual sequence of
+ * instructions often look something like:
+ *
+ * call .L66
+ * .L66:
+ * popl %ebx
+ * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
+ *
+ * The call and pop essentially return the absolute address
+ * of the label .L66 and store it in %ebx. The linker itself
+ * will ultimately change the first operand of the addl so
+ * that %ebx points to the GOT, but to keep things simple, the
+ * .o file must have this operand set so that it generates not
+ * the absolute address of .L66, but the absolute address of
+ * itself. This allows the linker itself simply treat a GOTPC
+ * relocation as asking for a pcrel offset to the GOT to be
+ * added in, and the addend of the relocation is stored in the
+ * operand field for the instruction itself.
+ *
+ * Our job here is to fix the operand so that it would add
+ * the correct offset so that %ebx would point to itself. The
+ * thing that is tricky is that .-.L66 will point to the
+ * beginning of the instruction, so we need to further modify
+ * the operand so that it will point to itself. There are
+ * other cases where you have something like:
+ *
+ * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
+ *
+ * and here no correction would be required. Internally in
+ * the assembler we treat operands of this form as not being
+ * pcrel since the '.' is explicitly mentioned, and I wonder
+ * whether it would simplify matters to do it this way. Who
+ * knows. In earlier versions of the PIC patches, the
+ * pcrel_adjust field was used to store the correction, but
+ * since the expression is not pcrel, I felt it would be
+ * confusing to do it this way. */
+
+ if (reloc_type == BFD_RELOC_32
+ && GOT_symbol
+ && GOT_symbol == i.op[n].imms->X_add_symbol
+ && (i.op[n].imms->X_op == O_symbol
+ || (i.op[n].imms->X_op == O_add
+ && ((symbol_get_value_expression
+ (i.op[n].imms->X_op_symbol)->X_op)
+ == O_subtract))))
+ {
+ offsetT add;
- if (fits_in_unsigned_byte (i.tm.base_opcode))
- {
- insn_size += 1 + size;
- p = frag_more (1 + size);
- }
- else
- {
- /* Opcode can be at most two bytes. */
- insn_size += 2 + size;
- p = frag_more (2 + size);
- *p++ = (i.tm.base_opcode >> 8) & 0xff;
- }
- *p++ = i.tm.base_opcode & 0xff;
+ if (insn_start_frag == frag_now)
+ add = (p - frag_now->fr_literal) - insn_start_off;
+ else
+ {
+ fragS *fr;
- fix_new_exp (frag_now, p - frag_now->fr_literal, size,
- i.op[0].disps, 1, reloc (size, 1, 1, i.disp_reloc[0]));
- }
- else if (i.tm.opcode_modifier & JumpInterSegment)
- {
- int size;
- int prefix;
- int code16;
+ add = insn_start_frag->fr_fix - insn_start_off;
+ for (fr = insn_start_frag->fr_next;
+ fr && fr != frag_now; fr = fr->fr_next)
+ add += fr->fr_fix;
+ add += p - frag_now->fr_literal;
+ }
- code16 = 0;
- if (flag_code == CODE_16BIT)
- code16 = CODE16;
+ /* We don't support dynamic linking on x86-64 yet. */
+ if (flag_code == CODE_64BIT)
+ abort ();
+ reloc_type = BFD_RELOC_386_GOTPC;
+ i.op[n].imms->X_add_number += add;
+ }
+ fix_new_exp (frag_now, p - frag_now->fr_literal, size,
+ i.op[n].imms, 0, reloc_type);
+ }
+ }
+ }
+}
+\f
+#ifndef LEX_AT
+static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
- prefix = 0;
- if (i.prefix[DATA_PREFIX])
- {
- prefix = 1;
- i.prefixes -= 1;
- code16 ^= CODE16;
- }
- if (i.prefix[REX_PREFIX])
- {
- prefix++;
- i.prefixes -= 1;
- }
+/* Parse operands of the form
+ <symbol>@GOTOFF+<nnn>
+ and similar .plt or .got references.
- size = 4;
- if (code16)
- size = 2;
+ If we find one, set up the correct relocation in RELOC and copy the
+ input string, minus the `@GOTOFF' into a malloc'd buffer for
+ parsing by the calling routine. Return this buffer, and if ADJUST
+ is non-null set it to the length of the string we removed from the
+ input line. Otherwise return NULL. */
+static char *
+lex_got (reloc, adjust)
+ enum bfd_reloc_code_real *reloc;
+ int *adjust;
+{
+ static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
+ static const struct {
+ const char *str;
+ const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
+ } gotrel[] = {
+ { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
+ { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
+ { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
+ { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
+ { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
+ { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
+ { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
+ { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
+ { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
+ { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
+ { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
+ { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
+ { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
+ };
+ char *cp;
+ unsigned int j;
- if (i.prefixes != 0 && !intel_syntax)
- as_warn (_("skipping prefixes on this instruction"));
+ for (cp = input_line_pointer; *cp != '@'; cp++)
+ if (is_end_of_line[(unsigned char) *cp])
+ return NULL;
- /* 1 opcode; 2 segment; offset */
- insn_size += prefix + 1 + 2 + size;
- p = frag_more (prefix + 1 + 2 + size);
+ for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
+ {
+ int len;
- if (i.prefix[DATA_PREFIX])
- *p++ = DATA_PREFIX_OPCODE;
+ len = strlen (gotrel[j].str);
+ if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
+ {
+ if (gotrel[j].rel[(unsigned int) flag_code] != 0)
+ {
+ int first, second;
+ char *tmpbuf, *past_reloc;
+
+ *reloc = gotrel[j].rel[(unsigned int) flag_code];
+ if (adjust)
+ *adjust = len;
+
+ if (GOT_symbol == NULL)
+ GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
+
+ /* Replace the relocation token with ' ', so that
+ errors like foo@GOTOFF1 will be detected. */
+
+ /* The length of the first part of our input line. */
+ first = cp - input_line_pointer;
+
+ /* The second part goes from after the reloc token until
+ (and including) an end_of_line char. Don't use strlen
+ here as the end_of_line char may not be a NUL. */
+ past_reloc = cp + 1 + len;
+ for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
+ ;
+ second = cp - past_reloc;
+
+ /* Allocate and copy string. The trailing NUL shouldn't
+ be necessary, but be safe. */
+ tmpbuf = xmalloc (first + second + 2);
+ memcpy (tmpbuf, input_line_pointer, first);
+ tmpbuf[first] = ' ';
+ memcpy (tmpbuf + first + 1, past_reloc, second);
+ tmpbuf[first + second + 1] = '\0';
+ return tmpbuf;
+ }
- if (i.prefix[REX_PREFIX])
- *p++ = i.prefix[REX_PREFIX];
+ as_bad (_("@%s reloc is not supported in %s bit mode"),
+ gotrel[j].str, mode_name[(unsigned int) flag_code]);
+ return NULL;
+ }
+ }
- *p++ = i.tm.base_opcode;
- if (i.op[1].imms->X_op == O_constant)
- {
- offsetT n = i.op[1].imms->X_add_number;
+ /* Might be a symbol version string. Don't as_bad here. */
+ return NULL;
+}
- if (size == 2
- && !fits_in_unsigned_word (n)
- && !fits_in_signed_word (n))
- {
- as_bad (_("16-bit jump out of range"));
- return;
- }
- md_number_to_chars (p, n, size);
- }
- else
- fix_new_exp (frag_now, p - frag_now->fr_literal, size,
- i.op[1].imms, 0, reloc (size, 0, 0, i.disp_reloc[0]));
- if (i.op[0].imms->X_op != O_constant)
- as_bad (_("can't handle non absolute segment in `%s'"),
- i.tm.name);
- md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
- }
- else
- {
- /* Output normal instructions here. */
- unsigned char *q;
-
- /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
- byte for the SSE instructions to specify prefix they require. */
- if (i.tm.base_opcode & 0xff0000)
- add_prefix ((i.tm.base_opcode >> 16) & 0xff);
-
- /* The prefix bytes. */
- for (q = i.prefix;
- q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
- q++)
- {
- if (*q)
- {
- insn_size += 1;
- p = frag_more (1);
- md_number_to_chars (p, (valueT) *q, 1);
- }
- }
+/* x86_cons_fix_new is called via the expression parsing code when a
+ reloc is needed. We use this hook to get the correct .got reloc. */
+static enum bfd_reloc_code_real got_reloc = NO_RELOC;
- /* Now the opcode; be careful about word order here! */
- if (fits_in_unsigned_byte (i.tm.base_opcode))
- {
- insn_size += 1;
- FRAG_APPEND_1_CHAR (i.tm.base_opcode);
- }
- else
- {
- insn_size += 2;
- p = frag_more (2);
- /* Put out high byte first: can't use md_number_to_chars! */
- *p++ = (i.tm.base_opcode >> 8) & 0xff;
- *p = i.tm.base_opcode & 0xff;
- }
+void
+x86_cons_fix_new (frag, off, len, exp)
+ fragS *frag;
+ unsigned int off;
+ unsigned int len;
+ expressionS *exp;
+{
+ enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
+ got_reloc = NO_RELOC;
+ fix_new_exp (frag, off, len, exp, 0, r);
+}
- /* Now the modrm byte and sib byte (if present). */
- if (i.tm.opcode_modifier & Modrm)
- {
- insn_size += 1;
- p = frag_more (1);
- md_number_to_chars (p,
- (valueT) (i.rm.regmem << 0
- | i.rm.reg << 3
- | i.rm.mode << 6),
- 1);
- /* If i.rm.regmem == ESP (4)
- && i.rm.mode != (Register mode)
- && not 16 bit
- ==> need second modrm byte. */
- if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
- && i.rm.mode != 3
- && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
- {
- insn_size += 1;
- p = frag_more (1);
- md_number_to_chars (p,
- (valueT) (i.sib.base << 0
- | i.sib.index << 3
- | i.sib.scale << 6),
- 1);
- }
- }
+void
+x86_cons (exp, size)
+ expressionS *exp;
+ int size;
+{
+ if (size == 4)
+ {
+ /* Handle @GOTOFF and the like in an expression. */
+ char *save;
+ char *gotfree_input_line;
+ int adjust;
- if (i.disp_operands)
- {
- register unsigned int n;
+ save = input_line_pointer;
+ gotfree_input_line = lex_got (&got_reloc, &adjust);
+ if (gotfree_input_line)
+ input_line_pointer = gotfree_input_line;
- for (n = 0; n < i.operands; n++)
- {
- if (i.types[n] & Disp)
- {
- if (i.op[n].disps->X_op == O_constant)
- {
- int size;
- offsetT val;
+ expression (exp);
- size = 4;
- if (i.types[n] & (Disp8 | Disp16 | Disp64))
- {
- size = 2;
- if (i.types[n] & Disp8)
- size = 1;
- if (i.types[n] & Disp64)
- size = 8;
- }
- val = offset_in_range (i.op[n].disps->X_add_number,
- size);
- insn_size += size;
- p = frag_more (size);
- md_number_to_chars (p, val, size);
- }
- else
- {
- int size = 4;
- int sign = 0;
- int pcrel = (i.flags[n] & Operand_PCrel) != 0;
-
- /* The PC relative address is computed relative
- to the instruction boundary, so in case immediate
- fields follows, we need to adjust the value. */
- if (pcrel && i.imm_operands)
- {
- int imm_size = 4;
- register unsigned int n1;
-
- for (n1 = 0; n1 < i.operands; n1++)
- if (i.types[n1] & Imm)
- {
- if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
- {
- imm_size = 2;
- if (i.types[n1] & (Imm8 | Imm8S))
- imm_size = 1;
- if (i.types[n1] & Imm64)
- imm_size = 8;
- }
- break;
- }
- /* We should find the immediate. */
- if (n1 == i.operands)
- abort ();
- i.op[n].disps->X_add_number -= imm_size;
- }
+ if (gotfree_input_line)
+ {
+ /* expression () has merrily parsed up to the end of line,
+ or a comma - in the wrong buffer. Transfer how far
+ input_line_pointer has moved to the right buffer. */
+ input_line_pointer = (save
+ + (input_line_pointer - gotfree_input_line)
+ + adjust);
+ free (gotfree_input_line);
+ }
+ }
+ else
+ expression (exp);
+}
+#endif
- if (i.types[n] & Disp32S)
- sign = 1;
+#ifdef TE_PE
- if (i.types[n] & (Disp16 | Disp64))
- {
- size = 2;
- if (i.types[n] & Disp64)
- size = 8;
- }
+void
+x86_pe_cons_fix_new (frag, off, len, exp)
+ fragS *frag;
+ unsigned int off;
+ unsigned int len;
+ expressionS *exp;
+{
+ enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
- insn_size += size;
- p = frag_more (size);
- fix_new_exp (frag_now, p - frag_now->fr_literal, size,
- i.op[n].disps, pcrel,
- reloc (size, pcrel, sign, i.disp_reloc[n]));
- }
- }
- }
- }
+ if (exp->X_op == O_secrel)
+ {
+ exp->X_op = O_symbol;
+ r = BFD_RELOC_32_SECREL;
+ }
- /* Output immediate. */
- if (i.imm_operands)
- {
- register unsigned int n;
+ fix_new_exp (frag, off, len, exp, 0, r);
+}
- for (n = 0; n < i.operands; n++)
- {
- if (i.types[n] & Imm)
- {
- if (i.op[n].imms->X_op == O_constant)
- {
- int size;
- offsetT val;
+static void
+pe_directive_secrel (dummy)
+ int dummy ATTRIBUTE_UNUSED;
+{
+ expressionS exp;
- size = 4;
- if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
- {
- size = 2;
- if (i.types[n] & (Imm8 | Imm8S))
- size = 1;
- else if (i.types[n] & Imm64)
- size = 8;
- }
- val = offset_in_range (i.op[n].imms->X_add_number,
- size);
- insn_size += size;
- p = frag_more (size);
- md_number_to_chars (p, val, size);
- }
- else
- {
- /* Not absolute_section.
- Need a 32-bit fixup (don't support 8bit
- non-absolute imms). Try to support other
- sizes ... */
-#ifdef BFD_ASSEMBLER
- enum bfd_reloc_code_real reloc_type;
-#else
- int reloc_type;
-#endif
- int size = 4;
- int sign = 0;
+ do
+ {
+ expression (&exp);
+ if (exp.X_op == O_symbol)
+ exp.X_op = O_secrel;
- if ((i.types[n] & (Imm32S))
- && i.suffix == QWORD_MNEM_SUFFIX)
- sign = 1;
- if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
- {
- size = 2;
- if (i.types[n] & (Imm8 | Imm8S))
- size = 1;
- if (i.types[n] & Imm64)
- size = 8;
- }
+ emit_expr (&exp, 4);
+ }
+ while (*input_line_pointer++ == ',');
- insn_size += size;
- p = frag_more (size);
- reloc_type = reloc (size, 0, sign, i.disp_reloc[0]);
-#ifdef BFD_ASSEMBLER
- if (reloc_type == BFD_RELOC_32
- && GOT_symbol
- && GOT_symbol == i.op[n].imms->X_add_symbol
- && (i.op[n].imms->X_op == O_symbol
- || (i.op[n].imms->X_op == O_add
- && ((symbol_get_value_expression
- (i.op[n].imms->X_op_symbol)->X_op)
- == O_subtract))))
- {
- /* We don't support dynamic linking on x86-64 yet. */
- if (flag_code == CODE_64BIT)
- abort ();
- reloc_type = BFD_RELOC_386_GOTPC;
- i.op[n].imms->X_add_number += 3;
- }
-#endif
- fix_new_exp (frag_now, p - frag_now->fr_literal, size,
- i.op[n].imms, 0, reloc_type);
- }
- }
- }
- }
- }
+ input_line_pointer--;
+ demand_empty_rest_of_line ();
+}
- dwarf2_emit_insn (insn_size);
+#endif
-#ifdef DEBUG386
- if (flag_debug)
- {
- pi (line, &i);
- }
-#endif /* DEBUG386 */
- }
-}
-\f
static int i386_immediate PARAMS ((char *));
static int
char *imm_start;
{
char *save_input_line_pointer;
+#ifndef LEX_AT
+ char *gotfree_input_line;
+#endif
segT exp_seg = 0;
expressionS *exp;
input_line_pointer = imm_start;
#ifndef LEX_AT
- {
- /* We can have operands of the form
- <symbol>@GOTOFF+<nnn>
- Take the easy way out here and copy everything
- into a temporary buffer... */
- register char *cp;
-
- cp = strchr (input_line_pointer, '@');
- if (cp != NULL)
- {
- char *tmpbuf;
- int len = 0;
- int first;
-
- /* GOT relocations are not supported in 16 bit mode. */
- if (flag_code == CODE_16BIT)
- as_bad (_("GOT relocations not supported in 16 bit mode"));
-
- if (GOT_symbol == NULL)
- GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
-
- if (strncmp (cp + 1, "PLT", 3) == 0)
- {
- if (flag_code == CODE_64BIT)
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
- else
- i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
- len = 3;
- }
- else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
- {
- if (flag_code == CODE_64BIT)
- as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
- i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
- len = 6;
- }
- else if (strncmp (cp + 1, "GOTPCREL", 8) == 0)
- {
- if (flag_code == CODE_64BIT)
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
- else
- as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
- len = 8;
- }
- else if (strncmp (cp + 1, "GOT", 3) == 0)
- {
- if (flag_code == CODE_64BIT)
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
- else
- i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
- len = 3;
- }
- else
- as_bad (_("bad reloc specifier in expression"));
-
- /* Replace the relocation token with ' ', so that errors like
- foo@GOTOFF1 will be detected. */
- first = cp - input_line_pointer;
- tmpbuf = (char *) alloca (strlen (input_line_pointer));
- memcpy (tmpbuf, input_line_pointer, first);
- tmpbuf[first] = ' ';
- strcpy (tmpbuf + first + 1, cp + 1 + len);
- input_line_pointer = tmpbuf;
- }
- }
+ gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
+ if (gotfree_input_line)
+ input_line_pointer = gotfree_input_line;
#endif
exp_seg = expression (exp);
SKIP_WHITESPACE ();
if (*input_line_pointer)
- as_bad (_("ignoring junk `%s' after expression"), input_line_pointer);
+ as_bad (_("junk `%s' after expression"), input_line_pointer);
input_line_pointer = save_input_line_pointer;
+#ifndef LEX_AT
+ if (gotfree_input_line)
+ free (gotfree_input_line);
+#endif
if (exp->X_op == O_absent || exp->X_op == O_big)
{
exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
}
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
- else if (1
-#ifdef BFD_ASSEMBLER
- && OUTPUT_FLAVOR == bfd_target_aout_flavour
-#endif
+ else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
+ && exp_seg != absolute_section
&& exp_seg != text_section
&& exp_seg != data_section
&& exp_seg != bss_section
&& exp_seg != undefined_section
-#ifdef BFD_ASSEMBLER
- && !bfd_is_com_section (exp_seg)
-#endif
- )
+ && !bfd_is_com_section (exp_seg))
{
-#ifdef BFD_ASSEMBLER
as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
-#else
- as_bad (_("unimplemented segment type %d in operand"), exp_seg);
-#endif
return 0;
}
#endif
return 1;
}
-static int i386_scale PARAMS ((char *));
+static char *i386_scale PARAMS ((char *));
-static int
+static char *
i386_scale (scale)
char *scale;
{
- if (!isdigit (*scale))
- goto bad_scale;
+ offsetT val;
+ char *save = input_line_pointer;
- switch (*scale)
+ input_line_pointer = scale;
+ val = get_absolute_expression ();
+
+ switch (val)
{
- case '0':
- case '1':
+ case 1:
i.log2_scale_factor = 0;
break;
- case '2':
+ case 2:
i.log2_scale_factor = 1;
break;
- case '4':
+ case 4:
i.log2_scale_factor = 2;
break;
- case '8':
+ case 8:
i.log2_scale_factor = 3;
break;
default:
- bad_scale:
- as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
- scale);
- return 0;
+ {
+ char sep = *input_line_pointer;
+
+ *input_line_pointer = '\0';
+ as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
+ scale);
+ *input_line_pointer = sep;
+ input_line_pointer = save;
+ return NULL;
+ }
}
- if (i.log2_scale_factor != 0 && ! i.index_reg)
+ if (i.log2_scale_factor != 0 && i.index_reg == 0)
{
as_warn (_("scale factor of %d without an index register"),
1 << i.log2_scale_factor);
i.log2_scale_factor = 0;
#endif
}
- return 1;
+ scale = input_line_pointer;
+ input_line_pointer = save;
+ return scale;
}
static int i386_displacement PARAMS ((char *, char *));
char *disp_start;
char *disp_end;
{
- register expressionS *exp;
+ expressionS *exp;
segT exp_seg = 0;
char *save_input_line_pointer;
+#ifndef LEX_AT
+ char *gotfree_input_line;
+#endif
int bigdisp = Disp32;
- if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
- bigdisp = Disp16;
if (flag_code == CODE_64BIT)
- bigdisp = Disp64;
+ {
+ if (i.prefix[ADDR_PREFIX] == 0)
+ bigdisp = Disp64;
+ }
+ else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
+ bigdisp = Disp16;
i.types[this_operand] |= bigdisp;
exp = &disp_expressions[i.disp_operands];
}
#endif
#ifndef LEX_AT
- {
- /* We can have operands of the form
- <symbol>@GOTOFF+<nnn>
- Take the easy way out here and copy everything
- into a temporary buffer... */
- register char *cp;
-
- cp = strchr (input_line_pointer, '@');
- if (cp != NULL)
- {
- char *tmpbuf;
- int len = 0;
- int first;
-
- /* GOT relocations are not supported in 16 bit mode. */
- if (flag_code == CODE_16BIT)
- as_bad (_("GOT relocations not supported in 16 bit mode"));
-
- if (GOT_symbol == NULL)
- GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
-
- if (strncmp (cp + 1, "PLT", 3) == 0)
- {
- if (flag_code == CODE_64BIT)
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
- else
- i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
- len = 3;
- }
- else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
- {
- if (flag_code == CODE_64BIT)
- as_bad ("GOTOFF relocation is not supported in 64bit mode.");
- i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
- len = 6;
- }
- else if (strncmp (cp + 1, "GOTPCREL", 8) == 0)
- {
- if (flag_code != CODE_64BIT)
- as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
- len = 8;
- }
- else if (strncmp (cp + 1, "GOT", 3) == 0)
- {
- if (flag_code == CODE_64BIT)
- i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
- else
- i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
- len = 3;
- }
- else
- as_bad (_("bad reloc specifier in expression"));
-
- /* Replace the relocation token with ' ', so that errors like
- foo@GOTOFF1 will be detected. */
- first = cp - input_line_pointer;
- tmpbuf = (char *) alloca (strlen (input_line_pointer));
- memcpy (tmpbuf, input_line_pointer, first);
- tmpbuf[first] = ' ';
- strcpy (tmpbuf + first + 1, cp + 1 + len);
- input_line_pointer = tmpbuf;
- }
- }
+ gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
+ if (gotfree_input_line)
+ input_line_pointer = gotfree_input_line;
#endif
exp_seg = expression (exp);
-#ifdef BFD_ASSEMBLER
+ SKIP_WHITESPACE ();
+ if (*input_line_pointer)
+ as_bad (_("junk `%s' after expression"), input_line_pointer);
+#if GCC_ASM_O_HACK
+ RESTORE_END_STRING (disp_end + 1);
+#endif
+ RESTORE_END_STRING (disp_end);
+ input_line_pointer = save_input_line_pointer;
+#ifndef LEX_AT
+ if (gotfree_input_line)
+ free (gotfree_input_line);
+#endif
+
/* We do this to make sure that the section symbol is in
the symbol table. We will ultimately change the relocation
to be relative to the beginning of the section. */
- if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF
- || i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
+ if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
+ || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
{
+ if (exp->X_op != O_symbol)
+ {
+ as_bad (_("bad expression used with @%s"),
+ (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
+ ? "GOTPCREL"
+ : "GOTOFF"));
+ return 0;
+ }
+
if (S_IS_LOCAL (exp->X_add_symbol)
&& S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
- assert (exp->X_op == O_symbol);
exp->X_op = O_subtract;
exp->X_op_symbol = GOT_symbol;
- if (i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
- i.disp_reloc[this_operand] = BFD_RELOC_32_PCREL;
+ if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
+ i.reloc[this_operand] = BFD_RELOC_32_PCREL;
else
- i.disp_reloc[this_operand] = BFD_RELOC_32;
+ i.reloc[this_operand] = BFD_RELOC_32;
}
-#endif
-
- SKIP_WHITESPACE ();
- if (*input_line_pointer)
- as_bad (_("ignoring junk `%s' after expression"),
- input_line_pointer);
-#if GCC_ASM_O_HACK
- RESTORE_END_STRING (disp_end + 1);
-#endif
- RESTORE_END_STRING (disp_end);
- input_line_pointer = save_input_line_pointer;
if (exp->X_op == O_absent || exp->X_op == O_big)
{
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
if (exp->X_op != O_constant
-#ifdef BFD_ASSEMBLER
&& OUTPUT_FLAVOR == bfd_target_aout_flavour
-#endif
+ && exp_seg != absolute_section
&& exp_seg != text_section
&& exp_seg != data_section
&& exp_seg != bss_section
- && exp_seg != undefined_section)
+ && exp_seg != undefined_section
+ && !bfd_is_com_section (exp_seg))
{
-#ifdef BFD_ASSEMBLER
as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
-#else
- as_bad (_("unimplemented segment type %d in operand"), exp_seg);
-#endif
return 0;
}
#endif
tryprefix:
#endif
ok = 1;
- if (flag_code == CODE_64BIT)
- {
- /* 64bit checks. */
- if ((i.base_reg
- && ((i.base_reg->reg_type & Reg64) == 0)
- && (i.base_reg->reg_type != BaseIndex
- || i.index_reg))
- || (i.index_reg
- && ((i.index_reg->reg_type & (Reg64|BaseIndex))
- != (Reg64|BaseIndex))))
- ok = 0;
+ if (flag_code == CODE_64BIT)
+ {
+ unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
+
+ if ((i.base_reg
+ && ((i.base_reg->reg_type & RegXX) == 0)
+ && (i.base_reg->reg_type != BaseIndex
+ || i.index_reg))
+ || (i.index_reg
+ && ((i.index_reg->reg_type & (RegXX | BaseIndex))
+ != (RegXX | BaseIndex))))
+ ok = 0;
}
else
{
{
/* 16bit checks. */
if ((i.base_reg
- && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
- != (Reg16|BaseIndex)))
+ && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
+ != (Reg16 | BaseIndex)))
|| (i.index_reg
- && (((i.index_reg->reg_type & (Reg16|BaseIndex))
- != (Reg16|BaseIndex))
- || ! (i.base_reg
- && i.base_reg->reg_num < 6
- && i.index_reg->reg_num >= 6
- && i.log2_scale_factor == 0))))
+ && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
+ != (Reg16 | BaseIndex))
+ || !(i.base_reg
+ && i.base_reg->reg_num < 6
+ && i.index_reg->reg_num >= 6
+ && i.log2_scale_factor == 0))))
ok = 0;
}
else
if ((i.base_reg
&& (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
|| (i.index_reg
- && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
- != (Reg32|BaseIndex))))
+ && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
+ != (Reg32 | BaseIndex))))
ok = 0;
}
}
if (!ok)
{
#if INFER_ADDR_PREFIX
- if (flag_code != CODE_64BIT
- && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
+ if (i.prefix[ADDR_PREFIX] == 0)
{
i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
i.prefixes += 1;
FIXME. There doesn't seem to be any real need for separate
Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
Removing them would probably clean up the code quite a lot. */
- if (i.types[this_operand] & (Disp16|Disp32))
- i.types[this_operand] ^= (Disp16|Disp32);
+ if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
+ i.types[this_operand] ^= (Disp16 | Disp32);
fudged = 1;
goto tryprefix;
}
as_bad (_("`%s' is not a valid %s bit base/index expression"),
operand_string,
flag_code_names[flag_code]);
- return 0;
}
- return 1;
+ return ok;
}
/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
}
/* Check for scale factor. */
- if (isdigit ((unsigned char) *base_string))
+ if (*base_string != ')')
{
- if (!i386_scale (base_string))
+ char *end_scale = i386_scale (base_string);
+
+ if (!end_scale)
return 0;
- ++base_string;
+ base_string = end_scale;
if (is_space_char (*base_string))
++base_string;
if (*base_string != ')')
int
md_estimate_size_before_relax (fragP, segment)
- register fragS *fragP;
- register segT segment;
+ fragS *fragP;
+ segT segment;
{
/* We've already got fragP->fr_subtype right; all we have to do is
check for un-relaxable symbols. On an ELF system, we can't relax
shared library. */
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
- || S_IS_EXTERNAL (fragP->fr_symbol)
- || S_IS_WEAK (fragP->fr_symbol)
+ || (OUTPUT_FLAVOR == bfd_target_elf_flavour
+ && (S_IS_EXTERNAL (fragP->fr_symbol)
+ || S_IS_WEAK (fragP->fr_symbol)))
#endif
)
{
/* Symbol is undefined in this segment, or we need to keep a
reloc so that weak symbols can be overridden. */
int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
-#ifdef BFD_ASSEMBLER
enum bfd_reloc_code_real reloc_type;
-#else
- int reloc_type;
-#endif
unsigned char *opcode;
int old_fr_fix;
break;
case COND_JUMP86:
- if (no_cond_jump_promotion)
- return 1;
- if (size == 2)
+ if (size == 2
+ && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
{
/* Negate the condition, and branch past an
unconditional jump. */
/* Fall through. */
case COND_JUMP:
- if (no_cond_jump_promotion)
- return 1;
+ if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
+ {
+ fixS *fixP;
+
+ fragP->fr_fix += 1;
+ fixP = fix_new (fragP, old_fr_fix, 1,
+ fragP->fr_symbol,
+ fragP->fr_offset, 1,
+ BFD_RELOC_8_PCREL);
+ fixP->fx_signed = 1;
+ break;
+ }
+
/* This changes the byte-displacement jump 0x7N
to the (d)word-displacement jump 0x0f,0x8N. */
opcode[1] = opcode[0] + 0x10;
frag_wane (fragP);
return fragP->fr_fix - old_fr_fix;
}
- /* Guess a short jump. */
- return 1;
+
+ /* Guess size depending on current relax state. Initially the relax
+ state will correspond to a short jump and we return 1, because
+ the variable part of the frag (the branch offset) is one byte
+ long. However, we can relax a section more than once and in that
+ case we must either set fr_subtype back to the unrelaxed state,
+ or return the value for the appropriate branch. */
+ return md_relax_table[fragP->fr_subtype].rlx_length;
}
/* Called after relax() is finished.
Out: Any fixSs and constants are set up.
Caller will turn frag into a ".space 0". */
-
-#ifndef BFD_ASSEMBLER
-void
-md_convert_frag (headers, sec, fragP)
- object_headers *headers ATTRIBUTE_UNUSED;
- segT sec ATTRIBUTE_UNUSED;
- register fragS *fragP;
-#else
+
void
md_convert_frag (abfd, sec, fragP)
bfd *abfd ATTRIBUTE_UNUSED;
segT sec ATTRIBUTE_UNUSED;
- register fragS *fragP;
-#endif
+ fragS *fragP;
{
- register unsigned char *opcode;
+ unsigned char *opcode;
unsigned char *where_to_put_displacement = NULL;
offsetT target_address;
offsetT opcode_address;
/* Address we want to reach in file space. */
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
-#ifdef BFD_ASSEMBLER
- /* Not needed otherwise? */
- target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
-#endif
/* Address opcode resides at in file space. */
opcode_address = fragP->fr_address + fragP->fr_fix;
the same (little-endian) format, so we don't need to care about which
we are handling. */
-int
-md_apply_fix3 (fixP, valp, seg)
+void
+md_apply_fix3 (fixP, valP, seg)
/* The fix we're to put in. */
fixS *fixP;
-
/* Pointer to the value of the bits. */
- valueT *valp;
-
+ valueT *valP;
/* Segment fix is from. */
segT seg ATTRIBUTE_UNUSED;
{
- register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
- valueT value = *valp;
+ char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
+ valueT value = *valP;
-#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
+#if !defined (TE_Mach)
if (fixP->fx_pcrel)
{
switch (fixP->fx_r_type)
break;
case BFD_RELOC_32:
+ case BFD_RELOC_X86_64_32S:
fixP->fx_r_type = BFD_RELOC_32_PCREL;
break;
case BFD_RELOC_16:
}
}
- /* This is a hack. There should be a better way to handle this.
- This covers for the fact that bfd_install_relocation will
- subtract the current location (for partial_inplace, PC relative
- relocations); see more below. */
- if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
- || fixP->fx_r_type == BFD_RELOC_16_PCREL
- || fixP->fx_r_type == BFD_RELOC_8_PCREL)
- && fixP->fx_addsy)
+ if (fixP->fx_addsy != NULL
+ && (fixP->fx_r_type == BFD_RELOC_32_PCREL
+ || fixP->fx_r_type == BFD_RELOC_16_PCREL
+ || fixP->fx_r_type == BFD_RELOC_8_PCREL)
+ && !use_rela_relocations)
{
+ /* This is a hack. There should be a better way to handle this.
+ This covers for the fact that bfd_install_relocation will
+ subtract the current location (for partial_inplace, PC relative
+ relocations); see more below. */
#ifndef OBJ_AOUT
if (OUTPUT_FLAVOR == bfd_target_elf_flavour
#ifdef TE_PE
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
{
- segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
+ segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
- if ((fseg == seg
+ if ((sym_seg == seg
|| (symbol_section_p (fixP->fx_addsy)
- && fseg != absolute_section))
- && ! S_IS_EXTERNAL (fixP->fx_addsy)
- && ! S_IS_WEAK (fixP->fx_addsy)
- && S_IS_DEFINED (fixP->fx_addsy)
- && ! S_IS_COMMON (fixP->fx_addsy))
+ && sym_seg != absolute_section))
+ && !generic_force_reloc (fixP))
{
/* Yes, we add the values in twice. This is because
- bfd_perform_relocation subtracts them out again. I think
- bfd_perform_relocation is broken, but I don't dare change
+ bfd_install_relocation subtracts them out again. I think
+ bfd_install_relocation is broken, but I don't dare change
it. FIXME. */
value += fixP->fx_where + fixP->fx_frag->fr_address;
}
}
#endif
#if defined (OBJ_COFF) && defined (TE_PE)
- /* For some reason, the PE format does not store a section
- address offset for a PC relative symbol. */
- if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
+ /* For some reason, the PE format does not store a
+ section address offset for a PC relative symbol. */
+ if (S_GET_SEGMENT (fixP->fx_addsy) != seg
+#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
+ || S_IS_WEAK (fixP->fx_addsy)
+#endif
+ )
value += md_pcrel_from (fixP);
#endif
}
/* Fix a few things - the dynamic linker expects certain values here,
- and we must not dissappoint it. */
+ and we must not disappoint it. */
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
if (OUTPUT_FLAVOR == bfd_target_elf_flavour
&& fixP->fx_addsy)
runtime we merely add the offset to the actual PLT entry. */
value = -4;
break;
- case BFD_RELOC_386_GOTPC:
-
-/* This is tough to explain. We end up with this one if we have
- * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
- * here is to obtain the absolute address of the GOT, and it is strongly
- * preferable from a performance point of view to avoid using a runtime
- * relocation for this. The actual sequence of instructions often look
- * something like:
- *
- * call .L66
- * .L66:
- * popl %ebx
- * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
- *
- * The call and pop essentially return the absolute address of
- * the label .L66 and store it in %ebx. The linker itself will
- * ultimately change the first operand of the addl so that %ebx points to
- * the GOT, but to keep things simple, the .o file must have this operand
- * set so that it generates not the absolute address of .L66, but the
- * absolute address of itself. This allows the linker itself simply
- * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
- * added in, and the addend of the relocation is stored in the operand
- * field for the instruction itself.
- *
- * Our job here is to fix the operand so that it would add the correct
- * offset so that %ebx would point to itself. The thing that is tricky is
- * that .-.L66 will point to the beginning of the instruction, so we need
- * to further modify the operand so that it will point to itself.
- * There are other cases where you have something like:
- *
- * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
- *
- * and here no correction would be required. Internally in the assembler
- * we treat operands of this form as not being pcrel since the '.' is
- * explicitly mentioned, and I wonder whether it would simplify matters
- * to do it this way. Who knows. In earlier versions of the PIC patches,
- * the pcrel_adjust field was used to store the correction, but since the
- * expression is not pcrel, I felt it would be confusing to do it this
- * way. */
-
- value -= 1;
+
+ case BFD_RELOC_386_TLS_GD:
+ case BFD_RELOC_386_TLS_LDM:
+ case BFD_RELOC_386_TLS_IE_32:
+ case BFD_RELOC_386_TLS_IE:
+ case BFD_RELOC_386_TLS_GOTIE:
+ case BFD_RELOC_X86_64_TLSGD:
+ case BFD_RELOC_X86_64_TLSLD:
+ case BFD_RELOC_X86_64_GOTTPOFF:
+ value = 0; /* Fully resolved at runtime. No addend. */
+ /* Fallthrough */
+ case BFD_RELOC_386_TLS_LE:
+ case BFD_RELOC_386_TLS_LDO_32:
+ case BFD_RELOC_386_TLS_LE_32:
+ case BFD_RELOC_X86_64_DTPOFF32:
+ case BFD_RELOC_X86_64_TPOFF32:
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
break;
+
case BFD_RELOC_386_GOT32:
case BFD_RELOC_X86_64_GOT32:
value = 0; /* Fully resolved at runtime. No addend. */
break;
- case BFD_RELOC_386_GOTOFF:
- case BFD_RELOC_X86_64_GOTPCREL:
- break;
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = 0;
- return 1;
+ return;
default:
break;
}
#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
- *valp = value;
-#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
+ *valP = value;
+#endif /* !defined (TE_Mach) */
-#ifndef BFD_ASSEMBLER
- md_number_to_chars (p, value, fixP->fx_size);
-#else
/* Are we finished with this relocation now? */
- if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
+ if (fixP->fx_addsy == NULL)
fixP->fx_done = 1;
else if (use_rela_relocations)
{
fixP->fx_no_overflow = 1;
+ /* Remember value for tc_gen_reloc. */
+ fixP->fx_addnumber = value;
value = 0;
}
- md_number_to_chars (p, value, fixP->fx_size);
-#endif
- return 1;
+ md_number_to_chars (p, value, fixP->fx_size);
}
\f
#define MAX_LITTLENUMS 6
return 0;
}
\f
-char output_invalid_buf[8];
+static char output_invalid_buf[8];
static char *
output_invalid (c)
int c;
{
- if (isprint (c))
+ if (ISPRINT (c))
sprintf (output_invalid_buf, "'%c'", c);
else
sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
}
}
+ if (r != NULL
+ && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
+ && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
+ && flag_code != CODE_64BIT)
+ return (const reg_entry *) NULL;
+
return r;
}
\f
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-const char *md_shortopts = "kVQ:sq";
+const char *md_shortopts = "kVQ:sqn";
#else
-const char *md_shortopts = "q";
+const char *md_shortopts = "qn";
#endif
struct option md_longopts[] = {
{
switch (c)
{
+ case 'n':
+ optimize_align_code = 0;
+ break;
+
case 'q':
quiet_warnings = 1;
break;
case 's':
/* -s: On i386 Solaris, this tells the native assembler to use
- .stab instead of .stab.excl. We always use .stab anyhow. */
+ .stab instead of .stab.excl. We always use .stab anyhow. */
break;
case OPTION_64:
-Q ignored\n\
-V print assembler version number\n\
-k ignored\n\
+ -n Do not optimize code alignment\n\
-q quieten some warnings\n\
-s ignored\n"));
#else
fprintf (stream, _("\
+ -n Do not optimize code alignment\n\
-q quieten some warnings\n"));
#endif
}
-#ifdef BFD_ASSEMBLER
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
{
if (flag_code == CODE_64BIT)
use_rela_relocations = 1;
- return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
+ return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
}
#endif
default:
}
#endif /* OBJ_MAYBE_ more than one */
-#endif /* BFD_ASSEMBLER */
+
+#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
+void i386_elf_emit_arch_note ()
+{
+ if (OUTPUT_FLAVOR == bfd_target_elf_flavour
+ && cpu_arch_name != NULL)
+ {
+ char *p;
+ asection *seg = now_seg;
+ subsegT subseg = now_subseg;
+ Elf_Internal_Note i_note;
+ Elf_External_Note e_note;
+ asection *note_secp;
+ int len;
+
+ /* Create the .note section. */
+ note_secp = subseg_new (".note", 0);
+ bfd_set_section_flags (stdoutput,
+ note_secp,
+ SEC_HAS_CONTENTS | SEC_READONLY);
+
+ /* Process the arch string. */
+ len = strlen (cpu_arch_name);
+
+ i_note.namesz = len + 1;
+ i_note.descsz = 0;
+ i_note.type = NT_ARCH;
+ p = frag_more (sizeof (e_note.namesz));
+ md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
+ p = frag_more (sizeof (e_note.descsz));
+ md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
+ p = frag_more (sizeof (e_note.type));
+ md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
+ p = frag_more (len + 1);
+ strcpy (p, cpu_arch_name);
+
+ frag_align (2, 0, 0);
+
+ subseg_set (seg, subseg);
+ }
+}
+#endif
\f
symbolS *
md_undefined_symbol (name)
segT segment ATTRIBUTE_UNUSED;
valueT size;
{
-#ifdef BFD_ASSEMBLER
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
{
align = bfd_get_section_alignment (stdoutput, segment);
size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
}
-#endif
#endif
return size;
s_bss (ignore)
int ignore ATTRIBUTE_UNUSED;
{
- register int temp;
+ int temp;
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+ if (IS_ELF)
+ obj_elf_section_change_hook ();
+#endif
temp = get_absolute_expression ();
subseg_set (bss_section, (subsegT) temp);
demand_empty_rest_of_line ();
#endif
-#ifdef BFD_ASSEMBLER
-
void
i386_validate_fix (fixp)
fixS *fixp;
case BFD_RELOC_386_GOT32:
case BFD_RELOC_386_GOTOFF:
case BFD_RELOC_386_GOTPC:
- case BFD_RELOC_X86_64_32S:
+ case BFD_RELOC_386_TLS_GD:
+ case BFD_RELOC_386_TLS_LDM:
+ case BFD_RELOC_386_TLS_LDO_32:
+ case BFD_RELOC_386_TLS_IE_32:
+ case BFD_RELOC_386_TLS_IE:
+ case BFD_RELOC_386_TLS_GOTIE:
+ case BFD_RELOC_386_TLS_LE_32:
+ case BFD_RELOC_386_TLS_LE:
+ case BFD_RELOC_X86_64_TLSGD:
+ case BFD_RELOC_X86_64_TLSLD:
+ case BFD_RELOC_X86_64_DTPOFF32:
+ case BFD_RELOC_X86_64_GOTTPOFF:
+ case BFD_RELOC_X86_64_TPOFF32:
case BFD_RELOC_RVA:
case BFD_RELOC_VTABLE_ENTRY:
case BFD_RELOC_VTABLE_INHERIT:
+#ifdef TE_PE
+ case BFD_RELOC_32_SECREL:
+#endif
code = fixp->fx_r_type;
break;
+ case BFD_RELOC_X86_64_32S:
+ if (!fixp->fx_pcrel)
+ {
+ /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
+ code = fixp->fx_r_type;
+ break;
+ }
default:
if (fixp->fx_pcrel)
{
switch (fixp->fx_size)
{
default:
- as_bad (_("can not do %d byte pc-relative relocation"),
- fixp->fx_size);
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("can not do %d byte pc-relative relocation"),
+ fixp->fx_size);
code = BFD_RELOC_32_PCREL;
break;
case 1: code = BFD_RELOC_8_PCREL; break;
switch (fixp->fx_size)
{
default:
- as_bad (_("can not do %d byte relocation"), fixp->fx_size);
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("can not do %d byte relocation"),
+ fixp->fx_size);
code = BFD_RELOC_32;
break;
case 1: code = BFD_RELOC_8; break;
case 2: code = BFD_RELOC_16; break;
case 4: code = BFD_RELOC_32; break;
+#ifdef BFD64
case 8: code = BFD_RELOC_64; break;
+#endif
}
}
break;
*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
if (!use_rela_relocations)
{
/* HACK: Since i386 ELF uses Rel instead of Rela, encode the
if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
rel->address = fixp->fx_offset;
- if (fixp->fx_pcrel)
- rel->addend = fixp->fx_addnumber;
- else
- rel->addend = 0;
+ rel->addend = 0;
}
/* Use the rela in 64bit mode. */
else
{
- rel->addend = fixp->fx_offset;
-#ifdef OBJ_ELF
- /* Ohhh, this is ugly. The problem is that if this is a local global
- symbol, the relocation will entirely be performed at link time, not
- at assembly time. bfd_perform_reloc doesn't know about this sort
- of thing, and as a result we need to fake it out here. */
- if ((S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))
- && !S_IS_COMMON (fixp->fx_addsy))
- rel->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value;
-#endif
- if (fixp->fx_pcrel)
- rel->addend -= fixp->fx_size;
+ if (!fixp->fx_pcrel)
+ rel->addend = fixp->fx_offset;
+ else
+ switch (code)
+ {
+ case BFD_RELOC_X86_64_PLT32:
+ case BFD_RELOC_X86_64_GOT32:
+ case BFD_RELOC_X86_64_GOTPCREL:
+ case BFD_RELOC_X86_64_TLSGD:
+ case BFD_RELOC_X86_64_TLSLD:
+ case BFD_RELOC_X86_64_GOTTPOFF:
+ rel->addend = fixp->fx_offset - fixp->fx_size;
+ break;
+ default:
+ rel->addend = (section->vma
+ - fixp->fx_size
+ + fixp->fx_addnumber
+ + md_pcrel_from (fixp));
+ break;
+ }
}
rel->howto = bfd_reloc_type_lookup (stdoutput, code);
return rel;
}
-#else /* ! BFD_ASSEMBLER */
-
-#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
-void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
- char *where;
- fixS *fixP;
- relax_addressT segment_address_in_file;
-{
- /* In: length of relocation (or of address) in chars: 1, 2 or 4.
- Out: GNU LD relocation length code: 0, 1, or 2. */
-
- static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
- long r_symbolnum;
-
- know (fixP->fx_addsy != NULL);
-
- md_number_to_chars (where,
- (valueT) (fixP->fx_frag->fr_address
- + fixP->fx_where - segment_address_in_file),
- 4);
-
- r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
- ? S_GET_TYPE (fixP->fx_addsy)
- : fixP->fx_addsy->sy_number);
-
- where[6] = (r_symbolnum >> 16) & 0x0ff;
- where[5] = (r_symbolnum >> 8) & 0x0ff;
- where[4] = r_symbolnum & 0x0ff;
- where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
- | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
- | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
-}
-
-#endif /* OBJ_AOUT or OBJ_BOUT. */
-
-#if defined (I386COFF)
-
-short
-tc_coff_fix2rtype (fixP)
- fixS *fixP;
-{
- if (fixP->fx_r_type == R_IMAGEBASE)
- return R_IMAGEBASE;
-
- return (fixP->fx_pcrel ?
- (fixP->fx_size == 1 ? R_PCRBYTE :
- fixP->fx_size == 2 ? R_PCRWORD :
- R_PCRLONG) :
- (fixP->fx_size == 1 ? R_RELBYTE :
- fixP->fx_size == 2 ? R_RELWORD :
- R_DIR32));
-}
-
-int
-tc_coff_sizemachdep (frag)
- fragS *frag;
-{
- if (frag->fr_next)
- return (frag->fr_next->fr_address - frag->fr_address);
- else
- return 0;
-}
-
-#endif /* I386COFF */
-
-#endif /* ! BFD_ASSEMBLER */
\f
/* Parse operands using Intel syntax. This implements a recursive descent
parser based on the BNF grammar published in Appendix B of the MASM 6.1
alpha [a-zA-Z]
+ binOp & | AND | \| | OR | ^ | XOR
+
byteRegister AL | AH | BL | BH | CL | CH | DL | DH
constant digits [[ radixOverride ]]
- dataType BYTE | WORD | DWORD | QWORD | XWORD
+ dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
digits decdigit
| digits decdigit
decdigit [0-9]
- e05 e05 addOp e06
+ e04 e04 addOp e05
+ | e05
+
+ e05 e05 binOp e06
| e06
e06 e06 mulOp e09
| e09
e09 OFFSET e10
+ | SHORT e10
+ | + e10
+ | - e10
+ | ~ e10
+ | NOT e10
| e09 PTR e10
| e09 : e10
| e10
| $
| register
- => expr SHORT e05
- | e05
+ => expr expr cmpOp e04
+ | e04
gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
| BP | EBP | SP | ESP | DI | EDI | SI | ESI
| id alpha
| id decdigit
- mulOp * | / | MOD
+ mulOp * | / | % | MOD | << | SHL | >> | SHR
quote " | '
segmentRegister CS | DS | ES | FS | GS | SS
- specialRegister CR0 | CR2 | CR3
+ specialRegister CR0 | CR2 | CR3 | CR4
| DR0 | DR1 | DR2 | DR3 | DR6 | DR7
| TR3 | TR4 | TR5 | TR6 | TR7
done by calling parse_register) and eliminate immediate left recursion
to implement a recursive-descent parser.
- expr SHORT e05
- | e05
+ expr e04 expr'
+
+ expr' cmpOp e04 expr'
+ | Empty
+
+ e04 e05 e04'
+
+ e04' addOp e05 e04'
+ | Empty
e05 e06 e05'
- e05' addOp e06 e05'
+ e05' binOp e06 e05'
| Empty
e06 e09 e06'
| Empty
e09 OFFSET e10 e09'
+ | SHORT e10'
+ | + e10'
+ | - e10'
+ | ~ e10'
+ | NOT e10'
| e10 e09'
e09' PTR e10 e09'
| BYTE
| WORD
| DWORD
+ | FWORD
| QWORD
- | XWORD
+ | TBYTE
+ | OWORD
+ | XMMWORD
| .
| $
| register
int got_a_float; /* Whether the operand is a float. */
int op_modifier; /* Operand modifier. */
int is_mem; /* 1 if operand is memory reference. */
+ int in_offset; /* >=1 if parsing operand of offset. */
+ int in_bracket; /* >=1 if parsing operand in brackets. */
const reg_entry *reg; /* Last register reference found. */
char *disp; /* Displacement string being built. */
+ char *next_operand; /* Resume point when splitting operands. */
};
static struct intel_parser_s intel_parser;
#define T_REG 2
#define T_BYTE 3
#define T_WORD 4
-#define T_DWORD 5
-#define T_QWORD 6
-#define T_XWORD 7
+#define T_DWORD 5
+#define T_FWORD 6
+#define T_QWORD 7
+#define T_TBYTE 8
+#define T_XMMWORD 9
#undef T_SHORT
-#define T_SHORT 8
-#define T_OFFSET 9
-#define T_PTR 10
-#define T_ID 11
+#define T_SHORT 10
+#define T_OFFSET 11
+#define T_PTR 12
+#define T_ID 13
+#define T_SHL 14
+#define T_SHR 15
/* Prototypes for intel parser functions. */
static int intel_match_token PARAMS ((int code));
static void intel_get_token PARAMS ((void));
static void intel_putback_token PARAMS ((void));
static int intel_expr PARAMS ((void));
+static int intel_e04 PARAMS ((void));
static int intel_e05 PARAMS ((void));
-static int intel_e05_1 PARAMS ((void));
static int intel_e06 PARAMS ((void));
-static int intel_e06_1 PARAMS ((void));
static int intel_e09 PARAMS ((void));
-static int intel_e09_1 PARAMS ((void));
+static int intel_bracket_expr PARAMS ((void));
static int intel_e10 PARAMS ((void));
-static int intel_e10_1 PARAMS ((void));
static int intel_e11 PARAMS ((void));
static int
int ret;
char *p;
- /* Initialize token holders. */
- cur_token.code = prev_token.code = T_NIL;
- cur_token.reg = prev_token.reg = NULL;
- cur_token.str = prev_token.str = NULL;
-
- /* Initialize parser structure. */
- p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
- if (p == NULL)
- abort ();
- strcpy (intel_parser.op_string, operand_string);
- intel_parser.got_a_float = got_a_float;
- intel_parser.op_modifier = -1;
- intel_parser.is_mem = 0;
- intel_parser.reg = NULL;
- intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
- if (intel_parser.disp == NULL)
- abort ();
- intel_parser.disp[0] = '\0';
-
- /* Read the first token and start the parser. */
- intel_get_token ();
- ret = intel_expr ();
-
- if (ret)
+ p = intel_parser.op_string = xstrdup (operand_string);
+ intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
+
+ for (;;)
{
+ /* Initialize token holders. */
+ cur_token.code = prev_token.code = T_NIL;
+ cur_token.reg = prev_token.reg = NULL;
+ cur_token.str = prev_token.str = NULL;
+
+ /* Initialize parser structure. */
+ intel_parser.got_a_float = got_a_float;
+ intel_parser.op_modifier = 0;
+ intel_parser.is_mem = 0;
+ intel_parser.in_offset = 0;
+ intel_parser.in_bracket = 0;
+ intel_parser.reg = NULL;
+ intel_parser.disp[0] = '\0';
+ intel_parser.next_operand = NULL;
+
+ /* Read the first token and start the parser. */
+ intel_get_token ();
+ ret = intel_expr ();
+
+ if (!ret)
+ break;
+
+ if (cur_token.code != T_NIL)
+ {
+ as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
+ current_templates->start->name, cur_token.str);
+ ret = 0;
+ }
/* If we found a memory reference, hand it over to i386_displacement
to fill in the rest of the operand fields. */
- if (intel_parser.is_mem)
+ else if (intel_parser.is_mem)
{
if ((i.mem_operands == 1
&& (current_templates->start->opcode_modifier & IsString) == 0)
char *s = intel_parser.disp;
i.mem_operands++;
+ if (!quiet_warnings && intel_parser.is_mem < 0)
+ /* See the comments in intel_bracket_expr. */
+ as_warn (_("Treating `%s' as memory reference"), operand_string);
+
/* Add the displacement expression. */
if (*s != '\0')
- ret = i386_displacement (s, s + strlen (s))
- && i386_index_check (s);
+ ret = i386_displacement (s, s + strlen (s));
+ if (ret)
+ {
+ /* Swap base and index in 16-bit memory operands like
+ [si+bx]. Since i386_index_check is also used in AT&T
+ mode we have to do that here. */
+ if (i.base_reg
+ && i.index_reg
+ && (i.base_reg->reg_type & Reg16)
+ && (i.index_reg->reg_type & Reg16)
+ && i.base_reg->reg_num >= 6
+ && i.index_reg->reg_num < 6)
+ {
+ const reg_entry *base = i.index_reg;
+
+ i.index_reg = i.base_reg;
+ i.base_reg = base;
+ }
+ ret = i386_index_check (operand_string);
+ }
}
}
/* Constant and OFFSET expressions are handled by i386_immediate. */
- else if (intel_parser.op_modifier == OFFSET_FLAT
+ else if ((intel_parser.op_modifier & (1 << T_OFFSET))
|| intel_parser.reg == NULL)
ret = i386_immediate (intel_parser.disp);
+
+ if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
+ ret = 0;
+ if (!ret || !intel_parser.next_operand)
+ break;
+ intel_parser.op_string = intel_parser.next_operand;
+ this_operand = i.operands++;
}
free (p);
return ret;
}
-/* expr SHORT e05
- | e05 */
+#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
+
+/* expr e04 expr'
+
+ expr' cmpOp e04 expr'
+ | Empty */
static int
intel_expr ()
{
- /* expr SHORT e05 */
- if (cur_token.code == T_SHORT)
+ /* XXX Implement the comparison operators. */
+ return intel_e04 ();
+}
+
+/* e04 e05 e04'
+
+ e04' addOp e05 e04'
+ | Empty */
+static int
+intel_e04 ()
+{
+ int nregs = -1;
+
+ for (;;)
{
- intel_parser.op_modifier = SHORT;
- intel_match_token (T_SHORT);
+ if (!intel_e05())
+ return 0;
- return (intel_e05 ());
- }
+ if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+ i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
- /* expr e05 */
- else
- return intel_e05 ();
+ if (cur_token.code == '+')
+ nregs = -1;
+ else if (cur_token.code == '-')
+ nregs = NUM_ADDRESS_REGS;
+ else
+ return 1;
+
+ strcat (intel_parser.disp, cur_token.str);
+ intel_match_token (cur_token.code);
+ }
}
/* e05 e06 e05'
- e05' addOp e06 e05'
+ e05' binOp e06 e05'
| Empty */
static int
intel_e05 ()
{
- return (intel_e06 () && intel_e05_1 ());
-}
+ int nregs = ~NUM_ADDRESS_REGS;
-static int
-intel_e05_1 ()
-{
- /* e05' addOp e06 e05' */
- if (cur_token.code == '+' || cur_token.code == '-')
+ for (;;)
{
- strcat (intel_parser.disp, cur_token.str);
+ if (!intel_e06())
+ return 0;
+
+ if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
+ {
+ char str[2];
+
+ str[0] = cur_token.code;
+ str[1] = 0;
+ strcat (intel_parser.disp, str);
+ }
+ else
+ break;
+
intel_match_token (cur_token.code);
- return (intel_e06 () && intel_e05_1 ());
+ if (nregs < 0)
+ nregs = ~nregs;
}
-
- /* e05' Empty */
- else
- return 1;
+ if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+ i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
+ return 1;
}
/* e06 e09 e06'
static int
intel_e06 ()
{
- return (intel_e09 () && intel_e06_1 ());
-}
+ int nregs = ~NUM_ADDRESS_REGS;
-static int
-intel_e06_1 ()
-{
- /* e06' mulOp e09 e06' */
- if (cur_token.code == '*' || cur_token.code == '/')
+ for (;;)
{
- strcat (intel_parser.disp, cur_token.str);
- intel_match_token (cur_token.code);
+ if (!intel_e09())
+ return 0;
- return (intel_e09 () && intel_e06_1 ());
- }
+ if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
+ {
+ char str[2];
- /* e06' Empty */
- else
- return 1;
+ str[0] = cur_token.code;
+ str[1] = 0;
+ strcat (intel_parser.disp, str);
+ }
+ else if (cur_token.code == T_SHL)
+ strcat (intel_parser.disp, "<<");
+ else if (cur_token.code == T_SHR)
+ strcat (intel_parser.disp, ">>");
+ else
+ break;
+
+ intel_match_token (cur_token.code);
+
+ if (nregs < 0)
+ nregs = ~nregs;
+ }
+ if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+ i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
+ return 1;
}
-/* e09 OFFSET e10 e09'
+/* e09 OFFSET e09
+ | SHORT e09
+ | + e09
+ | - e09
+ | ~ e09
+ | NOT e09
| e10 e09'
e09' PTR e10 e09'
static int
intel_e09 ()
{
- /* e09 OFFSET e10 e09' */
- if (cur_token.code == T_OFFSET)
+ int nregs = ~NUM_ADDRESS_REGS;
+ int in_offset = 0;
+
+ for (;;)
{
- intel_parser.is_mem = 0;
- intel_parser.op_modifier = OFFSET_FLAT;
- intel_match_token (T_OFFSET);
+ /* Don't consume constants here. */
+ if (cur_token.code == '+' || cur_token.code == '-')
+ {
+ /* Need to look one token ahead - if the next token
+ is a constant, the current token is its sign. */
+ int next_code;
- return (intel_e10 () && intel_e09_1 ());
- }
+ intel_match_token (cur_token.code);
+ next_code = cur_token.code;
+ intel_putback_token ();
+ if (next_code == T_CONST)
+ break;
+ }
- /* e09 e10 e09' */
- else
- return (intel_e10 () && intel_e09_1 ());
-}
+ /* e09 OFFSET e09 */
+ if (cur_token.code == T_OFFSET)
+ {
+ if (!in_offset++)
+ ++intel_parser.in_offset;
+ }
-static int
-intel_e09_1 ()
-{
- /* e09' PTR e10 e09' */
- if (cur_token.code == T_PTR)
- {
- if (prev_token.code == T_BYTE)
- i.suffix = BYTE_MNEM_SUFFIX;
+ /* e09 SHORT e09 */
+ else if (cur_token.code == T_SHORT)
+ intel_parser.op_modifier |= 1 << T_SHORT;
+
+ /* e09 + e09 */
+ else if (cur_token.code == '+')
+ strcat (intel_parser.disp, "+");
- else if (prev_token.code == T_WORD)
+ /* e09 - e09
+ | ~ e09
+ | NOT e09 */
+ else if (cur_token.code == '-' || cur_token.code == '~')
{
- if (intel_parser.got_a_float == 2) /* "fi..." */
- i.suffix = SHORT_MNEM_SUFFIX;
- else
- i.suffix = WORD_MNEM_SUFFIX;
+ char str[2];
+
+ if (nregs < 0)
+ nregs = ~nregs;
+ str[0] = cur_token.code;
+ str[1] = 0;
+ strcat (intel_parser.disp, str);
}
- else if (prev_token.code == T_DWORD)
+ /* e09 e10 e09' */
+ else
+ break;
+
+ intel_match_token (cur_token.code);
+ }
+
+ for (;;)
+ {
+ if (!intel_e10 ())
+ return 0;
+
+ /* e09' PTR e10 e09' */
+ if (cur_token.code == T_PTR)
{
- if (intel_parser.got_a_float == 1) /* "f..." */
- i.suffix = SHORT_MNEM_SUFFIX;
+ char suffix;
+
+ if (prev_token.code == T_BYTE)
+ suffix = BYTE_MNEM_SUFFIX;
+
+ else if (prev_token.code == T_WORD)
+ {
+ if (current_templates->start->name[0] == 'l'
+ && current_templates->start->name[2] == 's'
+ && current_templates->start->name[3] == 0)
+ suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+ else if (intel_parser.got_a_float == 2) /* "fi..." */
+ suffix = SHORT_MNEM_SUFFIX;
+ else
+ suffix = WORD_MNEM_SUFFIX;
+ }
+
+ else if (prev_token.code == T_DWORD)
+ {
+ if (current_templates->start->name[0] == 'l'
+ && current_templates->start->name[2] == 's'
+ && current_templates->start->name[3] == 0)
+ suffix = WORD_MNEM_SUFFIX;
+ else if (flag_code == CODE_16BIT
+ && (current_templates->start->opcode_modifier
+ & (Jump|JumpDword|JumpInterSegment)))
+ suffix = LONG_DOUBLE_MNEM_SUFFIX;
+ else if (intel_parser.got_a_float == 1) /* "f..." */
+ suffix = SHORT_MNEM_SUFFIX;
+ else
+ suffix = LONG_MNEM_SUFFIX;
+ }
+
+ else if (prev_token.code == T_FWORD)
+ {
+ if (current_templates->start->name[0] == 'l'
+ && current_templates->start->name[2] == 's'
+ && current_templates->start->name[3] == 0)
+ suffix = LONG_MNEM_SUFFIX;
+ else if (!intel_parser.got_a_float)
+ {
+ if (flag_code == CODE_16BIT)
+ add_prefix (DATA_PREFIX_OPCODE);
+ suffix = LONG_DOUBLE_MNEM_SUFFIX;
+ }
+ else
+ suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+ }
+
+ else if (prev_token.code == T_QWORD)
+ {
+ if (intel_parser.got_a_float == 1) /* "f..." */
+ suffix = LONG_MNEM_SUFFIX;
+ else
+ suffix = QWORD_MNEM_SUFFIX;
+ }
+
+ else if (prev_token.code == T_TBYTE)
+ {
+ if (intel_parser.got_a_float == 1)
+ suffix = LONG_DOUBLE_MNEM_SUFFIX;
+ else
+ suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+ }
+
+ else if (prev_token.code == T_XMMWORD)
+ {
+ /* XXX ignored for now, but accepted since gcc uses it */
+ suffix = 0;
+ }
+
else
- i.suffix = LONG_MNEM_SUFFIX;
+ {
+ as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
+ return 0;
+ }
+
+ if (current_templates->start->base_opcode == 0x8d /* lea */)
+ ;
+ else if (!i.suffix)
+ i.suffix = suffix;
+ else if (i.suffix != suffix)
+ {
+ as_bad (_("Conflicting operand modifiers"));
+ return 0;
+ }
+
}
- else if (prev_token.code == T_QWORD)
+ /* e09' : e10 e09' */
+ else if (cur_token.code == ':')
{
- if (intel_parser.got_a_float == 1) /* "f..." */
- i.suffix = LONG_MNEM_SUFFIX;
- else
- i.suffix = QWORD_MNEM_SUFFIX;
+ if (prev_token.code != T_REG)
+ {
+ /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
+ segment/group identifier (which we don't have), using comma
+ as the operand separator there is even less consistent, since
+ there all branches only have a single operand. */
+ if (this_operand != 0
+ || intel_parser.in_offset
+ || intel_parser.in_bracket
+ || (!(current_templates->start->opcode_modifier
+ & (Jump|JumpDword|JumpInterSegment))
+ && !(current_templates->start->operand_types[0]
+ & JumpAbsolute)))
+ return intel_match_token (T_NIL);
+ /* Remember the start of the 2nd operand and terminate 1st
+ operand here.
+ XXX This isn't right, yet (when SSSS:OOOO is right operand of
+ another expression), but it gets at least the simplest case
+ (a plain number or symbol on the left side) right. */
+ intel_parser.next_operand = intel_parser.op_string;
+ *--intel_parser.op_string = '\0';
+ return intel_match_token (':');
+ }
}
- else if (prev_token.code == T_XWORD)
- i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
-
+ /* e09' Empty */
else
+ break;
+
+ intel_match_token (cur_token.code);
+
+ }
+
+ if (in_offset)
+ {
+ --intel_parser.in_offset;
+ if (nregs < 0)
+ nregs = ~nregs;
+ if (NUM_ADDRESS_REGS > nregs)
{
- as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
+ as_bad (_("Invalid operand to `OFFSET'"));
return 0;
}
+ intel_parser.op_modifier |= 1 << T_OFFSET;
+ }
+
+ if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+ i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
+ return 1;
+}
+
+static int
+intel_bracket_expr ()
+{
+ int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
+ const char *start = intel_parser.op_string;
+ int len;
+
+ if (i.op[this_operand].regs)
+ return intel_match_token (T_NIL);
- intel_match_token (T_PTR);
+ intel_match_token ('[');
- return (intel_e10 () && intel_e09_1 ());
+ /* Mark as a memory operand only if it's not already known to be an
+ offset expression. If it's an offset expression, we need to keep
+ the brace in. */
+ if (!intel_parser.in_offset)
+ {
+ ++intel_parser.in_bracket;
+ /* Unfortunately gas always diverged from MASM in a respect that can't
+ be easily fixed without risking to break code sequences likely to be
+ encountered (the testsuite even check for this): MASM doesn't consider
+ an expression inside brackets unconditionally as a memory reference.
+ When that is e.g. a constant, an offset expression, or the sum of the
+ two, this is still taken as a constant load. gas, however, always
+ treated these as memory references. As a compromise, we'll try to make
+ offset expressions inside brackets work the MASM way (since that's
+ less likely to be found in real world code), but make constants alone
+ continue to work the traditional gas way. In either case, issue a
+ warning. */
+ intel_parser.op_modifier &= ~was_offset;
}
+ else
+ strcat (intel_parser.disp, "[");
- /* e09 : e10 e09' */
- else if (cur_token.code == ':')
+ /* Add a '+' to the displacement string if necessary. */
+ if (*intel_parser.disp != '\0'
+ && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
+ strcat (intel_parser.disp, "+");
+
+ if (intel_expr ()
+ && (len = intel_parser.op_string - start - 1,
+ intel_match_token (']')))
{
- /* Mark as a memory operand only if it's not already known to be an
- offset expression. */
- if (intel_parser.op_modifier != OFFSET_FLAT)
- intel_parser.is_mem = 1;
+ /* Preserve brackets when the operand is an offset expression. */
+ if (intel_parser.in_offset)
+ strcat (intel_parser.disp, "]");
+ else
+ {
+ --intel_parser.in_bracket;
+ if (i.base_reg || i.index_reg)
+ intel_parser.is_mem = 1;
+ if (!intel_parser.is_mem)
+ {
+ if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
+ /* Defer the warning until all of the operand was parsed. */
+ intel_parser.is_mem = -1;
+ else if (!quiet_warnings)
+ as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
+ }
+ }
+ intel_parser.op_modifier |= was_offset;
- return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
+ return 1;
}
-
- /* e09' Empty */
- else
- return 1;
+ return 0;
}
/* e10 e11 e10'
static int
intel_e10 ()
{
- return (intel_e11 () && intel_e10_1 ());
-}
+ if (!intel_e11 ())
+ return 0;
-static int
-intel_e10_1 ()
-{
- /* e10' [ expr ] e10' */
- if (cur_token.code == '[')
+ while (cur_token.code == '[')
{
- intel_match_token ('[');
-
- /* Mark as a memory operand only if it's not already known to be an
- offset expression. If it's an offset expression, we need to keep
- the brace in. */
- if (intel_parser.op_modifier != OFFSET_FLAT)
- intel_parser.is_mem = 1;
- else
- strcat (intel_parser.disp, "[");
-
- /* Add a '+' to the displacement string if necessary. */
- if (*intel_parser.disp != '\0'
- && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
- strcat (intel_parser.disp, "+");
-
- if (intel_expr () && intel_match_token (']'))
- {
- /* Preserve brackets when the operand is an offset expression. */
- if (intel_parser.op_modifier == OFFSET_FLAT)
- strcat (intel_parser.disp, "]");
-
- return intel_e10_1 ();
- }
- else
+ if (!intel_bracket_expr ())
return 0;
}
- /* e10' Empty */
- else
- return 1;
+ return 1;
}
/* e11 ( expr )
| BYTE
| WORD
| DWORD
+ | FWORD
| QWORD
- | XWORD
+ | TBYTE
+ | OWORD
+ | XMMWORD
| $
| .
| register
static int
intel_e11 ()
{
- /* e11 ( expr ) */
- if (cur_token.code == '(')
+ switch (cur_token.code)
{
+ /* e11 ( expr ) */
+ case '(':
intel_match_token ('(');
strcat (intel_parser.disp, "(");
strcat (intel_parser.disp, ")");
return 1;
}
- else
- return 0;
- }
-
- /* e11 [ expr ] */
- else if (cur_token.code == '[')
- {
- intel_match_token ('[');
-
- /* Mark as a memory operand only if it's not already known to be an
- offset expression. If it's an offset expression, we need to keep
- the brace in. */
- if (intel_parser.op_modifier != OFFSET_FLAT)
- intel_parser.is_mem = 1;
- else
- strcat (intel_parser.disp, "[");
+ return 0;
- /* Operands for jump/call inside brackets denote absolute addresses. */
- if (current_templates->start->opcode_modifier & Jump
- || current_templates->start->opcode_modifier & JumpDword
- || current_templates->start->opcode_modifier & JumpByte
- || current_templates->start->opcode_modifier & JumpInterSegment)
+ /* e11 [ expr ] */
+ case '[':
+ /* Operands for jump/call inside brackets denote absolute addresses.
+ XXX This shouldn't be needed anymore (or if it should rather live
+ in intel_bracket_expr). */
+ if (current_templates->start->opcode_modifier
+ & (Jump|JumpDword|JumpByte|JumpInterSegment))
i.types[this_operand] |= JumpAbsolute;
- /* Add a '+' to the displacement string if necessary. */
- if (*intel_parser.disp != '\0'
- && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
- strcat (intel_parser.disp, "+");
-
- if (intel_expr () && intel_match_token (']'))
- {
- /* Preserve brackets when the operand is an offset expression. */
- if (intel_parser.op_modifier == OFFSET_FLAT)
- strcat (intel_parser.disp, "]");
-
- return 1;
- }
- else
- return 0;
- }
-
- /* e11 BYTE
- | WORD
- | DWORD
- | QWORD
- | XWORD */
- else if (cur_token.code == T_BYTE
- || cur_token.code == T_WORD
- || cur_token.code == T_DWORD
- || cur_token.code == T_QWORD
- || cur_token.code == T_XWORD)
- {
- intel_match_token (cur_token.code);
-
- return 1;
- }
+ return intel_bracket_expr ();
- /* e11 $
- | . */
- else if (cur_token.code == '$' || cur_token.code == '.')
- {
+ /* e11 $
+ | . */
+ case '.':
strcat (intel_parser.disp, cur_token.str);
intel_match_token (cur_token.code);
/* Mark as a memory operand only if it's not already known to be an
offset expression. */
- if (intel_parser.op_modifier != OFFSET_FLAT)
+ if (!intel_parser.in_offset)
intel_parser.is_mem = 1;
return 1;
- }
- /* e11 register */
- else if (cur_token.code == T_REG)
- {
- const reg_entry *reg = intel_parser.reg = cur_token.reg;
+ /* e11 register */
+ case T_REG:
+ {
+ const reg_entry *reg = intel_parser.reg = cur_token.reg;
- intel_match_token (T_REG);
+ intel_match_token (T_REG);
- /* Check for segment change. */
- if (cur_token.code == ':')
- {
- if (reg->reg_type & (SReg2 | SReg3))
- {
- switch (reg->reg_num)
- {
- case 0:
- i.seg[i.mem_operands] = &es;
- break;
- case 1:
- i.seg[i.mem_operands] = &cs;
- break;
- case 2:
- i.seg[i.mem_operands] = &ss;
- break;
- case 3:
- i.seg[i.mem_operands] = &ds;
- break;
- case 4:
- i.seg[i.mem_operands] = &fs;
- break;
- case 5:
- i.seg[i.mem_operands] = &gs;
- break;
- }
- }
- else
- {
- as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
- return 0;
- }
- }
+ /* Check for segment change. */
+ if (cur_token.code == ':')
+ {
+ if (!(reg->reg_type & (SReg2 | SReg3)))
+ {
+ as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
+ return 0;
+ }
+ else if (i.seg[i.mem_operands])
+ as_warn (_("Extra segment override ignored"));
+ else
+ {
+ if (!intel_parser.in_offset)
+ intel_parser.is_mem = 1;
+ switch (reg->reg_num)
+ {
+ case 0:
+ i.seg[i.mem_operands] = &es;
+ break;
+ case 1:
+ i.seg[i.mem_operands] = &cs;
+ break;
+ case 2:
+ i.seg[i.mem_operands] = &ss;
+ break;
+ case 3:
+ i.seg[i.mem_operands] = &ds;
+ break;
+ case 4:
+ i.seg[i.mem_operands] = &fs;
+ break;
+ case 5:
+ i.seg[i.mem_operands] = &gs;
+ break;
+ }
+ }
+ }
- /* Not a segment register. Check for register scaling. */
- else if (cur_token.code == '*')
- {
- if (!intel_parser.is_mem)
- {
- as_bad (_("Register scaling only allowed in memory operands."));
+ /* Not a segment register. Check for register scaling. */
+ else if (cur_token.code == '*')
+ {
+ if (!intel_parser.in_bracket)
+ {
+ as_bad (_("Register scaling only allowed in memory operands"));
+ return 0;
+ }
+
+ if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
+ reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+ else if (i.index_reg)
+ reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
+
+ /* What follows must be a valid scale. */
+ intel_match_token ('*');
+ i.index_reg = reg;
+ i.types[this_operand] |= BaseIndex;
+
+ /* Set the scale after setting the register (otherwise,
+ i386_scale will complain) */
+ if (cur_token.code == '+' || cur_token.code == '-')
+ {
+ char *str, sign = cur_token.code;
+ intel_match_token (cur_token.code);
+ if (cur_token.code != T_CONST)
+ {
+ as_bad (_("Syntax error: Expecting a constant, got `%s'"),
+ cur_token.str);
+ return 0;
+ }
+ str = (char *) xmalloc (strlen (cur_token.str) + 2);
+ strcpy (str + 1, cur_token.str);
+ *str = sign;
+ if (!i386_scale (str))
+ return 0;
+ free (str);
+ }
+ else if (!i386_scale (cur_token.str))
return 0;
- }
+ intel_match_token (cur_token.code);
+ }
- /* What follows must be a valid scale. */
- if (intel_match_token ('*')
- && strchr ("01248", *cur_token.str))
- {
+ /* No scaling. If this is a memory operand, the register is either a
+ base register (first occurrence) or an index register (second
+ occurrence). */
+ else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
+ {
+
+ if (!i.base_reg)
+ i.base_reg = reg;
+ else if (!i.index_reg)
i.index_reg = reg;
- i.types[this_operand] |= BaseIndex;
+ else
+ {
+ as_bad (_("Too many register references in memory operand"));
+ return 0;
+ }
- /* Set the scale after setting the register (otherwise,
- i386_scale will complain) */
- i386_scale (cur_token.str);
- intel_match_token (T_CONST);
- }
- else
- {
- as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
- cur_token.str);
- return 0;
- }
- }
+ i.types[this_operand] |= BaseIndex;
+ }
- /* No scaling. If this is a memory operand, the register is either a
- base register (first occurrence) or an index register (second
- occurrence). */
- else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
- {
- if (i.base_reg && i.index_reg)
- {
- as_bad (_("Too many register references in memory operand.\n"));
- return 0;
- }
+ /* Offset modifier. Add the register to the displacement string to be
+ parsed as an immediate expression after we're done. */
+ else if (intel_parser.in_offset)
+ {
+ as_warn (_("Using register names in OFFSET expressions is deprecated"));
+ strcat (intel_parser.disp, reg->reg_name);
+ }
- if (i.base_reg == NULL)
- i.base_reg = reg;
- else
- i.index_reg = reg;
+ /* It's neither base nor index nor offset. */
+ else if (!intel_parser.is_mem)
+ {
+ i.types[this_operand] |= reg->reg_type & ~BaseIndex;
+ i.op[this_operand].regs = reg;
+ i.reg_operands++;
+ }
+ else
+ {
+ as_bad (_("Invalid use of register"));
+ return 0;
+ }
- i.types[this_operand] |= BaseIndex;
- }
+ /* Since registers are not part of the displacement string (except
+ when we're parsing offset operands), we may need to remove any
+ preceding '+' from the displacement string. */
+ if (*intel_parser.disp != '\0'
+ && !intel_parser.in_offset)
+ {
+ char *s = intel_parser.disp;
+ s += strlen (s) - 1;
+ if (*s == '+')
+ *s = '\0';
+ }
- /* Offset modifier. Add the register to the displacement string to be
- parsed as an immediate expression after we're done. */
- else if (intel_parser.op_modifier == OFFSET_FLAT)
- strcat (intel_parser.disp, reg->reg_name);
+ return 1;
+ }
- /* It's neither base nor index nor offset. */
- else
- {
- i.types[this_operand] |= reg->reg_type & ~BaseIndex;
- i.op[this_operand].regs = reg;
- i.reg_operands++;
- }
+ /* e11 BYTE
+ | WORD
+ | DWORD
+ | FWORD
+ | QWORD
+ | TBYTE
+ | OWORD
+ | XMMWORD */
+ case T_BYTE:
+ case T_WORD:
+ case T_DWORD:
+ case T_FWORD:
+ case T_QWORD:
+ case T_TBYTE:
+ case T_XMMWORD:
+ intel_match_token (cur_token.code);
+
+ if (cur_token.code == T_PTR)
+ return 1;
- /* Since registers are not part of the displacement string (except
- when we're parsing offset operands), we may need to remove any
- preceding '+' from the displacement string. */
- if (*intel_parser.disp != '\0'
- && intel_parser.op_modifier != OFFSET_FLAT)
+ /* It must have been an identifier. */
+ intel_putback_token ();
+ cur_token.code = T_ID;
+ /* FALLTHRU */
+
+ /* e11 id
+ | constant */
+ case T_ID:
+ if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
{
- char *s = intel_parser.disp;
- s += strlen (s) - 1;
- if (*s == '+')
- *s = '\0';
+ symbolS *symbolP;
+
+ /* The identifier represents a memory reference only if it's not
+ preceded by an offset modifier and if it's not an equate. */
+ symbolP = symbol_find(cur_token.str);
+ if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
+ intel_parser.is_mem = 1;
}
+ /* FALLTHRU */
- return 1;
- }
+ case T_CONST:
+ case '-':
+ case '+':
+ {
+ char *save_str, sign = 0;
- /* e11 id */
- else if (cur_token.code == T_ID)
- {
- /* Add the identifier to the displacement string. */
- strcat (intel_parser.disp, cur_token.str);
- intel_match_token (T_ID);
+ /* Allow constants that start with `+' or `-'. */
+ if (cur_token.code == '-' || cur_token.code == '+')
+ {
+ sign = cur_token.code;
+ intel_match_token (cur_token.code);
+ if (cur_token.code != T_CONST)
+ {
+ as_bad (_("Syntax error: Expecting a constant, got `%s'"),
+ cur_token.str);
+ return 0;
+ }
+ }
- /* The identifier represents a memory reference only if it's not
- preceded by an offset modifier. */
- if (intel_parser.op_modifier != OFFSET_FLAT)
- intel_parser.is_mem = 1;
+ save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
+ strcpy (save_str + !!sign, cur_token.str);
+ if (sign)
+ *save_str = sign;
- return 1;
- }
+ /* Get the next token to check for register scaling. */
+ intel_match_token (cur_token.code);
- /* e11 constant */
- else if (cur_token.code == T_CONST
- || cur_token.code == '-'
- || cur_token.code == '+')
- {
- char *save_str;
+ /* Check if this constant is a scaling factor for an index register. */
+ if (cur_token.code == '*')
+ {
+ if (intel_match_token ('*') && cur_token.code == T_REG)
+ {
+ const reg_entry *reg = cur_token.reg;
- /* Allow constants that start with `+' or `-'. */
- if (cur_token.code == '-' || cur_token.code == '+')
- {
- strcat (intel_parser.disp, cur_token.str);
- intel_match_token (cur_token.code);
- if (cur_token.code != T_CONST)
- {
- as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
- cur_token.str);
- return 0;
- }
- }
+ if (!intel_parser.in_bracket)
+ {
+ as_bad (_("Register scaling only allowed in memory operands"));
+ return 0;
+ }
- save_str = (char *) malloc (strlen (cur_token.str) + 1);
- if (save_str == NULL)
- abort ();
- strcpy (save_str, cur_token.str);
+ if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
+ reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+ else if (i.index_reg)
+ reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
- /* Get the next token to check for register scaling. */
- intel_match_token (cur_token.code);
+ /* The constant is followed by `* reg', so it must be
+ a valid scale. */
+ i.index_reg = reg;
+ i.types[this_operand] |= BaseIndex;
- /* Check if this constant is a scaling factor for an index register. */
- if (cur_token.code == '*')
- {
- if (intel_match_token ('*') && cur_token.code == T_REG)
- {
- if (!intel_parser.is_mem)
- {
- as_bad (_("Register scaling only allowed in memory operands."));
+ /* Set the scale after setting the register (otherwise,
+ i386_scale will complain) */
+ if (!i386_scale (save_str))
return 0;
- }
+ intel_match_token (T_REG);
- /* The constant is followed by `* reg', so it must be
- a valid scale. */
- if (strchr ("01248", *save_str))
- {
- i.index_reg = cur_token.reg;
- i.types[this_operand] |= BaseIndex;
-
- /* Set the scale after setting the register (otherwise,
- i386_scale will complain) */
- i386_scale (save_str);
- intel_match_token (T_REG);
-
- /* Since registers are not part of the displacement
- string, we may need to remove any preceding '+' from
- the displacement string. */
- if (*intel_parser.disp != '\0')
- {
- char *s = intel_parser.disp;
- s += strlen (s) - 1;
- if (*s == '+')
- *s = '\0';
- }
+ /* Since registers are not part of the displacement
+ string, we may need to remove any preceding '+' from
+ the displacement string. */
+ if (*intel_parser.disp != '\0')
+ {
+ char *s = intel_parser.disp;
+ s += strlen (s) - 1;
+ if (*s == '+')
+ *s = '\0';
+ }
- free (save_str);
+ free (save_str);
- return 1;
- }
- else
- return 0;
- }
+ return 1;
+ }
- /* The constant was not used for register scaling. Since we have
- already consumed the token following `*' we now need to put it
- back in the stream. */
- else
+ /* The constant was not used for register scaling. Since we have
+ already consumed the token following `*' we now need to put it
+ back in the stream. */
intel_putback_token ();
- }
+ }
- /* Add the constant to the displacement string. */
- strcat (intel_parser.disp, save_str);
- free (save_str);
+ /* Add the constant to the displacement string. */
+ strcat (intel_parser.disp, save_str);
+ free (save_str);
- return 1;
+ return 1;
+ }
}
as_bad (_("Unrecognized token '%s'"), cur_token.str);
}
else
{
- as_bad (_("Unexpected token `%s'\n"), cur_token.str);
+ as_bad (_("Unexpected token `%s'"), cur_token.str);
return 0;
}
}
/* The new token cannot be larger than the remainder of the operand
string. */
- new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
- if (new_token.str == NULL)
- abort ();
+ new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
new_token.str[0] = '\0';
if (strchr ("0123456789", *intel_parser.op_string))
new_token.code = T_ID;
}
- else if (strchr ("+-/*:[]()", *intel_parser.op_string))
- {
- new_token.code = *intel_parser.op_string;
- new_token.str[0] = *intel_parser.op_string;
- new_token.str[1] = '\0';
- }
-
else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
&& ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
{
Otherwise, it's operator '.' followed by an expression. */
if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
{
- new_token.code = *q;
- new_token.str[0] = *q;
+ new_token.code = '.';
+ new_token.str[0] = '.';
new_token.str[1] = '\0';
}
else
*p++ = *q++;
*p = '\0';
- if (strcasecmp (new_token.str, "BYTE") == 0)
+ if (strcasecmp (new_token.str, "NOT") == 0)
+ new_token.code = '~';
+
+ else if (strcasecmp (new_token.str, "MOD") == 0)
+ new_token.code = '%';
+
+ else if (strcasecmp (new_token.str, "AND") == 0)
+ new_token.code = '&';
+
+ else if (strcasecmp (new_token.str, "OR") == 0)
+ new_token.code = '|';
+
+ else if (strcasecmp (new_token.str, "XOR") == 0)
+ new_token.code = '^';
+
+ else if (strcasecmp (new_token.str, "SHL") == 0)
+ new_token.code = T_SHL;
+
+ else if (strcasecmp (new_token.str, "SHR") == 0)
+ new_token.code = T_SHR;
+
+ else if (strcasecmp (new_token.str, "BYTE") == 0)
new_token.code = T_BYTE;
else if (strcasecmp (new_token.str, "WORD") == 0)
else if (strcasecmp (new_token.str, "DWORD") == 0)
new_token.code = T_DWORD;
+ else if (strcasecmp (new_token.str, "FWORD") == 0)
+ new_token.code = T_FWORD;
+
else if (strcasecmp (new_token.str, "QWORD") == 0)
new_token.code = T_QWORD;
- else if (strcasecmp (new_token.str, "XWORD") == 0)
- new_token.code = T_XWORD;
+ else if (strcasecmp (new_token.str, "TBYTE") == 0
+ /* XXX remove (gcc still uses it) */
+ || strcasecmp (new_token.str, "XWORD") == 0)
+ new_token.code = T_TBYTE;
+
+ else if (strcasecmp (new_token.str, "XMMWORD") == 0
+ || strcasecmp (new_token.str, "OWORD") == 0)
+ new_token.code = T_XMMWORD;
else if (strcasecmp (new_token.str, "PTR") == 0)
new_token.code = T_PTR;
/* ??? This is not mentioned in the MASM grammar. */
else if (strcasecmp (new_token.str, "FLAT") == 0)
- new_token.code = T_OFFSET;
+ {
+ new_token.code = T_OFFSET;
+ if (*q == ':')
+ strcat (new_token.str, ":");
+ else
+ as_bad (_("`:' expected"));
+ }
else
new_token.code = T_ID;
}
}
+ else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
+ {
+ new_token.code = *intel_parser.op_string;
+ new_token.str[0] = *intel_parser.op_string;
+ new_token.str[1] = '\0';
+ }
+
+ else if (strchr ("<>", *intel_parser.op_string)
+ && *intel_parser.op_string == *(intel_parser.op_string + 1))
+ {
+ new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
+ new_token.str[0] = *intel_parser.op_string;
+ new_token.str[1] = *intel_parser.op_string;
+ new_token.str[2] = '\0';
+ }
+
else
- as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
+ as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
intel_parser.op_string += strlen (new_token.str);
cur_token = new_token;
static void
intel_putback_token ()
{
- intel_parser.op_string -= strlen (cur_token.str);
- free (cur_token.str);
+ if (cur_token.code != T_NIL)
+ {
+ intel_parser.op_string -= strlen (cur_token.str);
+ free (cur_token.str);
+ }
cur_token = prev_token;
/* Forget prev_token. */
prev_token.reg = NULL;
prev_token.str = NULL;
}
+
+int
+tc_x86_regname_to_dw2regnum (const char *regname)
+{
+ unsigned int regnum;
+ unsigned int regnames_count;
+ char *regnames_32[] =
+ {
+ "eax", "ecx", "edx", "ebx",
+ "esp", "ebp", "esi", "edi",
+ "eip"
+ };
+ char *regnames_64[] =
+ {
+ "rax", "rbx", "rcx", "rdx",
+ "rdi", "rsi", "rbp", "rsp",
+ "r8", "r9", "r10", "r11",
+ "r12", "r13", "r14", "r15",
+ "rip"
+ };
+ char **regnames;
+
+ if (flag_code == CODE_64BIT)
+ {
+ regnames = regnames_64;
+ regnames_count = ARRAY_SIZE (regnames_64);
+ }
+ else
+ {
+ regnames = regnames_32;
+ regnames_count = ARRAY_SIZE (regnames_32);
+ }
+
+ for (regnum = 0; regnum < regnames_count; regnum++)
+ if (strcmp (regname, regnames[regnum]) == 0)
+ return regnum;
+
+ return -1;
+}
+
+void
+tc_x86_frame_initial_instructions (void)
+{
+ static unsigned int sp_regno;
+
+ if (!sp_regno)
+ sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
+ ? "rsp" : "esp");
+
+ cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
+ cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
+}
+
+int
+i386_elf_section_type (const char *str, size_t len)
+{
+ if (flag_code == CODE_64BIT
+ && len == sizeof ("unwind") - 1
+ && strncmp (str, "unwind", 6) == 0)
+ return SHT_X86_64_UNWIND;
+
+ return -1;
+}
+
+#ifdef TE_PE
+void
+tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
+{
+ expressionS expr;
+
+ expr.X_op = O_secrel;
+ expr.X_add_symbol = symbol;
+ expr.X_add_number = 0;
+ emit_expr (&expr, size);
+}
+#endif
projects / deliverable / binutils-gdb.git / blobdiff