* configure.in: Define DEFAULT_ARCH for i386.

[deliverable/binutils-gdb.git] / gas / config / tc-i386.c

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 98cd518c740839fe36995a7d37968b4be083e3b0..c14f60a854cf116408b3321e68f58900424ac73f 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -352,9 +352,10 @@ static const arch_entry cpu_arch[] = {
   {"i686",     Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
   {"pentium",  Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
   {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
+  {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
   {"k6",       Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
   {"athlon",   Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
-  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE },
+  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
   {NULL, 0 }
 };
 
@@ -1862,8 +1863,11 @@ md_assemble (line)
        for (op = i.operands; --op >= 0; )
          if ((i.types[op] & Reg)
              && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
-           as_bad (_("Extended register `%%%s' available only in 64bit mode."),
-                   i.op[op].regs->reg_name);
+           {
+             as_bad (_("Extended register `%%%s' available only in 64bit mode."),
+                     i.op[op].regs->reg_name);
+             return;
+           }
       }
 
     /* If matched instruction specifies an explicit instruction mnemonic
@@ -2005,8 +2009,6 @@ md_assemble (line)
        else if (i.suffix == QWORD_MNEM_SUFFIX)
          {
            int op;
-           if (flag_code < CODE_64BIT)
-             as_bad (_("64bit operations available only in 64bit modes."));
 
            for (op = i.operands; --op >= 0; )
              /* Reject eight bit registers, except where the template
@@ -2196,7 +2198,14 @@ md_assemble (line)
        /* Set mode64 for an operand.  */
        if (i.suffix == QWORD_MNEM_SUFFIX
            && !(i.tm.opcode_modifier & NoRex64))
+         {
            i.rex.mode64 = 1;
+           if (flag_code < CODE_64BIT)
+             {
+                as_bad (_("64bit operations available only in 64bit modes."));
+                return;
+             }
+         }
 
        /* Size floating point instruction.  */
        if (i.suffix == LONG_MNEM_SUFFIX)
@@ -2825,6 +2834,11 @@ md_assemble (line)
        /* Output normal instructions here.  */
        unsigned char *q;
 
+       /* All opcodes on i386 have eighter 1 or 2 bytes.  We may use third
+          byte for the SSE instructions to specify prefix they require.  */
+       if (i.tm.base_opcode & 0xff0000)
+         add_prefix ((i.tm.base_opcode >> 16) & 0xff);
+
        /* The prefix bytes.  */
        for (q = i.prefix;
             q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
@@ -2844,7 +2858,7 @@ md_assemble (line)
            insn_size += 1;
            FRAG_APPEND_1_CHAR (i.tm.base_opcode);
          }
-       else if (fits_in_unsigned_word (i.tm.base_opcode))
+       else
          {
            insn_size += 2;
            p = frag_more (2);
@@ -2852,23 +2866,6 @@ md_assemble (line)
            *p++ = (i.tm.base_opcode >> 8) & 0xff;
            *p = i.tm.base_opcode & 0xff;
          }
-       else
-         {                     /* Opcode is either 3 or 4 bytes.  */
-           if (i.tm.base_opcode & 0xff000000)
-             {
-               insn_size += 4;
-               p = frag_more (4);
-               *p++ = (i.tm.base_opcode >> 24) & 0xff;
-             }
-           else
-             {
-               insn_size += 3;
-               p = frag_more (3);
-             }
-           *p++ = (i.tm.base_opcode >> 16) & 0xff;
-           *p++ = (i.tm.base_opcode >> 8) & 0xff;
-           *p = (i.tm.base_opcode) & 0xff;
-         }
 
        /* Now the modrm byte and sib byte (if present).  */
        if (i.tm.opcode_modifier & Modrm)