#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX 'l'
#define QWORD_MNEM_SUFFIX 'q'
-#define XMMWORD_MNEM_SUFFIX 'x'
-#define YMMWORD_MNEM_SUFFIX 'y'
-#define ZMMWORD_MNEM_SUFFIX 'z'
/* Intel Syntax. Use a non-ascii letter since since it never appears
in instructions. */
#define LONG_DOUBLE_MNEM_SUFFIX '\1'
{
if (x.bitfield.cpuavx)
{
- /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
+ /* We need to check a few extra flags with AVX. */
if (cpu.bitfield.cpuavx
&& (!t->opcode_modifier.sse2avx || sse2avx)
&& (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
+ && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
&& (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
match |= CPU_FLAGS_ARCH_MATCH;
}
+ else if (x.bitfield.cpuavx512f)
+ {
+ /* We need to check a few extra flags with AVX512F. */
+ if (cpu.bitfield.cpuavx512f
+ && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
+ && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
+ && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
+ match |= CPU_FLAGS_ARCH_MATCH;
+ }
else
match |= CPU_FLAGS_ARCH_MATCH;
}
{
supported |= cpu_flags_match (t);
if (supported == CPU_FLAGS_PERFECT_MATCH)
- goto skip;
- }
+ {
+ if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
+ as_warn (_("use .code16 to ensure correct addressing mode"));
- if (!(supported & CPU_FLAGS_64BIT_MATCH))
- {
- as_bad (flag_code == CODE_64BIT
- ? _("`%s' is not supported in 64-bit mode")
- : _("`%s' is only supported in 64-bit mode"),
- current_templates->start->name);
- return NULL;
- }
- if (supported != CPU_FLAGS_PERFECT_MATCH)
- {
- as_bad (_("`%s' is not supported on `%s%s'"),
- current_templates->start->name,
- cpu_arch_name ? cpu_arch_name : default_arch,
- cpu_sub_arch_name ? cpu_sub_arch_name : "");
- return NULL;
+ return l;
+ }
}
-skip:
- if (!cpu_arch_flags.bitfield.cpui386
- && (flag_code != CODE_16BIT))
- {
- as_warn (_("use .code16 to ensure correct addressing mode"));
- }
+ if (!(supported & CPU_FLAGS_64BIT_MATCH))
+ as_bad (flag_code == CODE_64BIT
+ ? _("`%s' is not supported in 64-bit mode")
+ : _("`%s' is only supported in 64-bit mode"),
+ current_templates->start->name);
+ else
+ as_bad (_("`%s' is not supported on `%s%s'"),
+ current_templates->start->name,
+ cpu_arch_name ? cpu_arch_name : default_arch,
+ cpu_sub_arch_name ? cpu_sub_arch_name : "");
- return l;
+ return NULL;
}
static char *
/* Fall through. */
case 3:
/* Here we make use of the fact that there are no
- reverse match 3 operand instructions, and all 3
- operand instructions only need to be checked for
- register consistency between operands 2 and 3. */
+ reverse match 3 operand instructions. */
if (!operand_type_match (overlap2, i.types[2])
|| (check_register
- && !operand_type_register_match (i.types[1],
- operand_types[1],
- i.types[2],
- operand_types[2])))
+ && (!operand_type_register_match (i.types[0],
+ operand_types[0],
+ i.types[2],
+ operand_types[2])
+ || !operand_type_register_match (i.types[1],
+ operand_types[1],
+ i.types[2],
+ operand_types[2]))))
continue;
break;
}
if (!i.tm.operand_types[op].bitfield.inoutportreg
&& !i.tm.operand_types[op].bitfield.shiftcount)
{
- if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
- {
- i.suffix = BYTE_MNEM_SUFFIX;
- break;
- }
- if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
- {
- i.suffix = WORD_MNEM_SUFFIX;
- break;
- }
- if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
- {
- i.suffix = LONG_MNEM_SUFFIX;
- break;
- }
- if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
- {
- i.suffix = QWORD_MNEM_SUFFIX;
- break;
- }
+ if (!i.types[op].bitfield.reg)
+ continue;
+ if (i.types[op].bitfield.byte)
+ i.suffix = BYTE_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.word)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.dword)
+ i.suffix = LONG_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.qword)
+ i.suffix = QWORD_MNEM_SUFFIX;
+ else
+ continue;
+ break;
}
}
}
else if (!check_word_reg ())
return 0;
}
- else if (i.suffix == XMMWORD_MNEM_SUFFIX
- || i.suffix == YMMWORD_MNEM_SUFFIX
- || i.suffix == ZMMWORD_MNEM_SUFFIX)
- {
- /* Skip if the instruction has x/y/z suffix. match_template
- should check if it is a valid suffix. */
- }
else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
/* Do nothing if the instruction is going to ignore the prefix. */
;
}
}
- /* Change the opcode based on the operand size given by i.suffix;
- We don't need to change things for byte insns. */
-
- if (i.suffix
- && i.suffix != BYTE_MNEM_SUFFIX
- && i.suffix != XMMWORD_MNEM_SUFFIX
- && i.suffix != YMMWORD_MNEM_SUFFIX
- && i.suffix != ZMMWORD_MNEM_SUFFIX)
+ /* Change the opcode based on the operand size given by i.suffix. */
+ switch (i.suffix)
{
+ /* Size floating point instruction. */
+ case LONG_MNEM_SUFFIX:
+ if (i.tm.opcode_modifier.floatmf)
+ {
+ i.tm.base_opcode ^= 4;
+ break;
+ }
+ /* fall through */
+ case WORD_MNEM_SUFFIX:
+ case QWORD_MNEM_SUFFIX:
/* It's not a byte, select word/dword operation. */
if (i.tm.opcode_modifier.w)
{
else
i.tm.base_opcode |= 1;
}
-
+ /* fall through */
+ case SHORT_MNEM_SUFFIX:
/* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway. */
return 0;
}
else if (i.suffix != QWORD_MNEM_SUFFIX
- && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
&& !i.tm.opcode_modifier.ignoresize
&& !i.tm.opcode_modifier.floatmf
&& ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
/* Set mode64 for an operand. */
if (i.suffix == QWORD_MNEM_SUFFIX
&& flag_code == CODE_64BIT
- && !i.tm.opcode_modifier.norex64)
- {
+ && !i.tm.opcode_modifier.norex64
/* Special case for xchg %rax,%rax. It is NOP and doesn't
- need rex64. cmpxchg8b is also a special case. */
- if (! (i.operands == 2
- && i.tm.base_opcode == 0x90
- && i.tm.extension_opcode == None
- && operand_type_equal (&i.types [0], &acc64)
- && operand_type_equal (&i.types [1], &acc64))
- && ! (i.operands == 1
- && i.tm.base_opcode == 0xfc7
- && i.tm.extension_opcode == 1
- && !operand_type_check (i.types [0], reg)
- && operand_type_check (i.types [0], anymem)))
- i.rex |= REX_W;
- }
-
- /* Size floating point instruction. */
- if (i.suffix == LONG_MNEM_SUFFIX)
- if (i.tm.opcode_modifier.floatmf)
- i.tm.base_opcode ^= 4;
+ need rex64. */
+ && ! (i.operands == 2
+ && i.tm.base_opcode == 0x90
+ && i.tm.extension_opcode == None
+ && operand_type_equal (&i.types [0], &acc64)
+ && operand_type_equal (&i.types [1], &acc64)))
+ i.rex |= REX_W;
+
+ break;
}
return 1;
}
else
{
- /* There are only 2 operands. */
- gas_assert (op < 2 && i.operands == 2);
- vex_reg = 1;
+ /* There are only 2 non-immediate operands. */
+ gas_assert (op < i.imm_operands + 2
+ && i.operands == i.imm_operands + 2);
+ vex_reg = i.imm_operands + 1;
}
}
else
projects / deliverable / binutils-gdb.git / blobdiff