/* tc-i386.h -- Header file for tc-i386.c
- Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
- Free Software Foundation.
+ Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+ 2001
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
-/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
- * It comes up in complicated expressions such as
- * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
- * the regular expressions. The fixup specified here when used at runtime
- * implies that we should add the address of the GOT to the specified location,
- * and as a result we have simplified the expression into something we can use.
- */
-#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
+#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
+/* This arranges for gas/write.c to not apply a relocation if
+ tc_fix_adjustable() says it is not adjustable.
+ The "! symbol_used_in_reloc_p" test is there specifically to cover
+ the case of non-global symbols in linkonce sections. It's the
+ generally correct thing to do though; If a reloc is going to be
+ emitted against a symbol then we don't want to adjust the fixup by
+ applying the reloc during assembly. The reloc will be applied by
+ the linker during final link. */
+#define TC_FIX_ADJUSTABLE(fixP) \
+ (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
+#endif
/* This expression evaluates to false if the relocation is for a local object
for which we still want to do the relocation at runtime. True if we
are willing to perform this relocation while building the .o file.
This is only used for pcrel relocations, so GOTOFF does not need to be
checked here. I am not sure if some of the others are ever used with
- pcrel, but it is easier to be safe than sorry. */
+ pcrel, but it is easier to be safe than sorry. */
#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
&& ! S_IS_COMMON ((FIX)->fx_addsy))))
#define TARGET_ARCH bfd_arch_i386
+#define TARGET_MACH (i386_mach ())
+extern unsigned long i386_mach PARAMS ((void));
+#ifdef TE_FreeBSD
+#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
+#endif
#ifdef TE_NetBSD
#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
#endif
#define AOUT_TARGET_FORMAT "a.out-i386"
#endif
-#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
- || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
- || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
+#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
+ || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#else
#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
extern short tc_coff_fix2rtype PARAMS ((struct fix *));
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
+#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
#ifdef TE_GO32
/* Need this for PIC relocations */
#define NEED_FX_R_TYPE
-
#ifdef TE_386BSD
/* The BSDI linker apparently rejects objects with a machine type of
M_386 (100). */
#endif /* ! BFD_ASSEMBLER */
+#ifndef LEX_AT
+#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
+extern void x86_cons PARAMS ((expressionS *, int));
+
+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
+extern void x86_cons_fix_new
+ PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
+#endif
+
#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
extern int tc_i386_force_relocation PARAMS ((struct fix *));
/* Prefixes will be emitted in the order defined below.
WAIT_PREFIX must be the first prefix since FWAIT is really is an
- instruction, and so must come before any prefixes. */
+ instruction, and so must come before any prefixes. */
#define WAIT_PREFIX 0
#define LOCKREP_PREFIX 1
#define ADDR_PREFIX 2
#define DATA_PREFIX 3
#define SEG_PREFIX 4
-#define MAX_PREFIXES 5 /* max prefixes per opcode */
+#define REX_PREFIX 5 /* must come last. */
+#define MAX_PREFIXES 6 /* max prefixes per opcode */
/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define BYTE_MNEM_SUFFIX 'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX 'l'
+#define QWORD_MNEM_SUFFIX 'q'
/* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x'
-/* Intel Syntax */
-#define DWORD_MNEM_SUFFIX 'd'
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define FLAT 7
#define NONE_FOUND 8
-
typedef struct
{
/* instruction name sans width suffix ("mov" for movl insns) */
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None */
unsigned int extension_opcode;
-#define None 0xffff /* If no extension_opcode is possible. */
+#define None 0xffff /* If no extension_opcode is possible. */
/* cpu feature flags */
unsigned int cpu_flags;
#define Cpu486 0x10 /* i486 or better required */
#define Cpu586 0x20 /* i585 or better required */
#define Cpu686 0x40 /* i686 or better required */
-#define CpuMMX 0x80 /* MMX support required */
-#define CpuSSE 0x100 /* Streaming SIMD extensions required */
-#define Cpu3dnow 0x200 /* 3dnow! support required */
+#define CpuP4 0x80 /* Pentium4 or better required */
+#define CpuK6 0x100 /* AMD K6 or better required*/
+#define CpuAthlon 0x200 /* AMD Athlon or better required*/
+#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
+#define CpuMMX 0x800 /* MMX support required */
+#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
+#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
+#define Cpu3dnow 0x4000 /* 3dnow! support required */
+#define CpuUnknown 0x8000 /* The CPU is unknown, be on the safe side. */
+
+ /* These flags are set by gas depending on the flag_code. */
+#define Cpu64 0x4000000 /* 64bit support required */
+#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
+
+ /* The default value for unknown CPUs - enable all features to avoid problems. */
+#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
#define ShortForm 0x10 /* register is in low 3 bits of opcode */
#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
-#define Jump 0x40 /* special case for jump insns. */
+#define Jump 0x40 /* special case for jump insns. */
#define JumpDword 0x80 /* call and jump */
#define JumpByte 0x100 /* loop and jecxz */
#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
-#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
+#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
-#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
-#define DefaultSize 0x10000 /* default insn size depends on mode */
-#define No_bSuf 0x20000 /* b suffix on instruction illegal */
-#define No_wSuf 0x40000 /* w suffix on instruction illegal */
-#define No_lSuf 0x80000 /* l suffix on instruction illegal */
-#define No_sSuf 0x100000 /* s suffix on instruction illegal */
-#define No_dSuf 0x200000 /* d suffix on instruction illegal */
-#define No_xSuf 0x400000 /* x suffix on instruction illegal */
-#define FWait 0x800000 /* instruction needs FWAIT */
-#define IsString 0x1000000 /* quick test for string instructions */
-#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
-#define IsPrefix 0x4000000 /* opcode is a prefix */
-#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
+#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
+#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
+#define DefaultSize 0x20000 /* default insn size depends on mode */
+#define No_bSuf 0x40000 /* b suffix on instruction illegal */
+#define No_wSuf 0x80000 /* w suffix on instruction illegal */
+#define No_lSuf 0x100000 /* l suffix on instruction illegal */
+#define No_sSuf 0x200000 /* s suffix on instruction illegal */
+#define No_qSuf 0x400000 /* q suffix on instruction illegal */
+#define No_xSuf 0x800000 /* x suffix on instruction illegal */
+#define FWait 0x1000000 /* instruction needs FWAIT */
+#define IsString 0x2000000 /* quick test for string instructions */
+#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
+#define IsPrefix 0x8000000 /* opcode is a prefix */
+#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
+#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
+#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
/* operand_types[i] describes the type of operand i. This is made
#define Reg8 0x1 /* 8 bit reg */
#define Reg16 0x2 /* 16 bit reg */
#define Reg32 0x4 /* 32 bit reg */
+#define Reg64 0x8 /* 64 bit reg */
/* immediate */
-#define Imm8 0x8 /* 8 bit immediate */
-#define Imm8S 0x10 /* 8 bit immediate sign extended */
-#define Imm16 0x20 /* 16 bit immediate */
-#define Imm32 0x40 /* 32 bit immediate */
-#define Imm1 0x80 /* 1 bit immediate */
+#define Imm8 0x10 /* 8 bit immediate */
+#define Imm8S 0x20 /* 8 bit immediate sign extended */
+#define Imm16 0x40 /* 16 bit immediate */
+#define Imm32 0x80 /* 32 bit immediate */
+#define Imm32S 0x100 /* 32 bit immediate sign extended */
+#define Imm64 0x200 /* 64 bit immediate */
+#define Imm1 0x400 /* 1 bit immediate */
/* memory */
-#define BaseIndex 0x100
+#define BaseIndex 0x800
/* Disp8,16,32 are used in different ways, depending on the
instruction. For jumps, they specify the size of the PC relative
displacement, for baseindex type instructions, they specify the
size of the offset relative to the base register, and for memory
offset instructions such as `mov 1234,%al' they specify the size of
the offset relative to the segment base. */
-#define Disp8 0x200 /* 8 bit displacement */
-#define Disp16 0x400 /* 16 bit displacement */
-#define Disp32 0x800 /* 32 bit displacement */
+#define Disp8 0x1000 /* 8 bit displacement */
+#define Disp16 0x2000 /* 16 bit displacement */
+#define Disp32 0x4000 /* 32 bit displacement */
+#define Disp32S 0x8000 /* 32 bit signed displacement */
+#define Disp64 0x10000 /* 64 bit displacement */
/* specials */
-#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
-#define ShiftCount 0x2000 /* register to hold shift cound = cl */
-#define Control 0x4000 /* Control register */
-#define Debug 0x8000 /* Debug register */
-#define Test 0x10000 /* Test register */
-#define FloatReg 0x20000 /* Float register */
-#define FloatAcc 0x40000 /* Float stack top %st(0) */
-#define SReg2 0x80000 /* 2 bit segment register */
-#define SReg3 0x100000 /* 3 bit segment register */
-#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
-#define JumpAbsolute 0x400000
-#define RegMMX 0x800000 /* MMX register */
-#define RegXMM 0x1000000 /* XMM registers in PIII */
-#define EsSeg 0x2000000 /* String insn operand with fixed es segment */
+#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
+#define ShiftCount 0x40000 /* register to hold shift cound = cl */
+#define Control 0x80000 /* Control register */
+#define Debug 0x100000 /* Debug register */
+#define Test 0x200000 /* Test register */
+#define FloatReg 0x400000 /* Float register */
+#define FloatAcc 0x800000 /* Float stack top %st(0) */
+#define SReg2 0x1000000 /* 2 bit segment register */
+#define SReg3 0x2000000 /* 3 bit segment register */
+#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
+#define JumpAbsolute 0x8000000
+#define RegMMX 0x10000000 /* MMX register */
+#define RegXMM 0x20000000 /* XMM registers in PIII */
+#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
+
/* InvMem is for instructions with a modrm byte that only allow a
general register encoding in the i.tm.mode and i.tm.regmem fields,
eg. control reg moves. They really ought to support a memory form,
but don't, so we add an InvMem flag to the register operand to
indicate that it should be encoded in the i.tm.regmem field. */
-#define InvMem 0x4000000
+#define InvMem 0x80000000
-#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
-#define WordReg (Reg16|Reg32)
+#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
+#define WordReg (Reg16|Reg32|Reg64)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
-#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
-#define Disp (Disp8|Disp16|Disp32) /* General displacement */
-#define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
+#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
+#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
+#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
+#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
/* The following aliases are defined because the opcode table
carefully specifies the allowed memory types for each instruction.
At the moment we can only tell a memory reference size by the
{
char *reg_name;
unsigned int reg_type;
+ unsigned int reg_flags;
+#define RegRex 0x1 /* Extended register. */
+#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
}
reg_entry;
}
seg_entry;
-/* 386 operand encoding bytes: see 386 book for details of this. */
+/* 386 operand encoding bytes: see 386 book for details of this. */
typedef struct
{
unsigned int regmem; /* codes register or memory operand */
}
modrm_byte;
-/* 386 opcode byte to code indirect addressing. */
+/* x86-64 extension prefix. */
+typedef struct
+ {
+ unsigned int mode64;
+ unsigned int extX; /* Used to extend modrm reg field. */
+ unsigned int extY; /* Used to extend SIB index field. */
+ unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */
+ unsigned int empty; /* Used to old-style byte registers to new style. */
+ }
+rex_byte;
+
+/* 386 opcode byte to code indirect addressing. */
typedef struct
{
unsigned base;
arch_entry;
/* The name of the global offset table generated by the compiler. Allow
- this to be overridden if need be. */
+ this to be overridden if need be. */
#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif
&& (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
&& subseg_text_p (now_seg)) \
{ \
- char *p; \
- p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
- (symbolS *) 0, (offsetT) (n), (char *) 0); \
- *p = 0x90; \
+ frag_align_code ((n), (max)); \
goto around; \
}
+#define MAX_MEM_FOR_RS_ALIGN_CODE 15
+
extern void i386_align_code PARAMS ((fragS *, int));
#define HANDLE_ALIGN(fragP) \
#endif
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
-
-/* end of tc-i386.h */
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