/* tc-i960.c - All the i80960-specific stuff
- Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+ 1999, 2000, 2001
Free Software Foundation, Inc.
This file is part of GAS.
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-/* See comment on md_parse_option for 80960-specific invocation options. */
+/* See comment on md_parse_option for 80960-specific invocation options. */
/* There are 4 different lengths of (potentially) symbol-based displacements
in the 80960 instruction set, each of which could require address fix-ups
#NO_APP at the beginning of its output.
*/
-/* Also note that comments started like this one will always work. */
+/* Also note that comments started like this one will always work. */
-const char line_comment_chars[1];
+const char line_comment_chars[] = "";
-const char line_separator_chars[1];
+const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums */
const char EXP_CHARS[] = "eE";
*/
const char FLT_CHARS[] = "fFdDtT";
-
/* Table used by base assembler to relax addresses based on varying length
instructions. The fields are:
1) most positive reach of this state,
#define adds(e) e.X_add_symbol
#define offs(e) e.X_add_number
-
/* Branch-prediction bits for CTRL/COBR format opcodes */
#define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
-
/* Some instruction opcodes that we need explicitly */
#define BE 0x12000000
#define BG 0x11000000
#define CALLS 0x66003800
#define RET 0x0a000000
-
-/* These masks are used to build up a set of MEMB mode bits. */
+/* These masks are used to build up a set of MEMB mode bits. */
#define A_BIT 0x0400
#define I_BIT 0x0800
#define MEMB_BIT 0x1000
#define D_BIT 0x2000
-
/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
used). */
#define MEMA_ABASE 0x2000
memS;
-
/* The two pieces of info we need to generate a register operand */
struct regop
{
int n; /* Register number or literal value */
};
-
/* Number and assembler mnemonic for all registers that can appear in
operands. */
static const struct
{ NULL, 0 }, /* END OF LIST */
};
-
/* Hash tables */
static struct hash_control *op_hash; /* Opcode mnemonics */
static struct hash_control *reg_hash; /* Register name hash table */
static struct hash_control *areg_hash; /* Abase register hash table */
-
/* Architecture for which we are assembling */
#define ARCH_ANY 0 /* Default: no architecture checking done */
#define ARCH_KA 1
* instructions.
*/
-
/* BRANCH-PREDICTION INSTRUMENTATION
The following supports generation of branch-prediction instrumentation
const char *bp_error_msg = _("branch prediction invalid on this opcode");
-
/* Parse instruction into opcode and operands */
memset (args, '\0', sizeof (args));
n_ops = i_scan (textP, args);
}
}
-
-
/* Check for branch-prediction suffix on opcode mnemonic, strip it off */
n = strlen (args[0]) - 1;
branch_predict = 0;
return retval;
}
-
#define MAX_LITTLENUMS 6
-#define LNUM_SIZE sizeof(LITTLENUM_TYPE)
+#define LNUM_SIZE sizeof (LITTLENUM_TYPE)
/*****************************************************************************
md_atof: convert ascii to floating point
return 0;
}
-
/*****************************************************************************
md_number_to_imm
md_number_to_chars (buf, val, n);
}
-
/*****************************************************************************
md_number_to_disp
A table of all such "Labels" is also generated.
-
-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
Select the 80960 architecture. Instructions or features not
supported by the selected architecture cause fatal errors.
instr |= (regop.n << 14) | regop.special;
}
-
if (n < 3)
{
emit (instr);
}
} /* cobr_fmt() */
-
/*****************************************************************************
ctrl_fmt: generate a CTRL-format instruction
* how often the branch is taken
*/
-
if (num_ops == 0)
{
emit (opcode); /* Output opcode */
}
-
/*****************************************************************************
emit: output instruction binary
return toP;
}
-
/*****************************************************************************
get_args: break individual arguments out of comma-separated list
return n;
}
-
/*****************************************************************************
get_cdisp: handle displacement for a COBR or CTRL instruction.
}
}
-
/*****************************************************************************
get_ispec: parse a memory operand for an index specification
return (rP == NULL) ? -1 : *rP;
}
-
/*****************************************************************************
i_scan: perform lexical scan of ascii assembler instruction.
*************************************************************************** */
static int
i_scan (iP, args)
- /* Pointer to ascii instruction; MUCKED BY US. */
+ /* Pointer to ascii instruction; MUCKED BY US. */
register char *iP;
/* Output arg: pointers to opcode and operands placed here. MUST
ACCOMMODATE 4 ENTRIES. */
return (get_args (iP, args));
} /* i_scan() */
-
/*****************************************************************************
mem_fmt: generate a MEMA- or MEMB-format instruction
memset (&instr, '\0', sizeof (memS));
instr.opcode = oP->opcode;
- /* Process operands. */
+ /* Process operands. */
for (i = 1; i <= oP->num_ops; i++)
{
opdesc = oP->operand[i - 1];
}
} /* memfmt() */
-
/*****************************************************************************
mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
md_number_to_chars (opcodeP, opcode, 4);
} /* mema_to_memb() */
-
/*****************************************************************************
parse_expr: parse an expression
}
}
-
/*****************************************************************************
parse_ldcont:
Parse and replace a 'ldconst' pseudo-instruction with an appropriate
static char buf2[5]; /* Literal for second operand */
expressionS e; /* Parsed expression */
-
arg[3] = NULL; /* So we can tell at the end if it got used or not */
parse_expr (arg[1], &e);
16 /* MEM16 */
};
-
iprel_flag = mode = 0;
/* Any index present? */
extern char is_end_of_line[];
- /* Advance input pointer to end of line. */
+ /* Advance input pointer to end of line. */
p = input_line_pointer;
while (!is_end_of_line[(unsigned char) *input_line_pointer])
{
struct regop regop; /* Description of register operand */
int n_ops; /* Number of operands */
-
instr = oP->opcode;
n_ops = oP->num_ops;
emit (instr);
}
-
/*****************************************************************************
relax_cobr:
Replace cobr instruction in a code fragment with equivalent branch and
frag_wane (fragP);
}
-
/*****************************************************************************
reloc_callj: Relocate a 'callj' instruction
/* else Symbol is neither a sysproc nor a leafproc */
}
-
/*****************************************************************************
s_leafproc: process .leafproc pseudo-op
return;
} /* Check number of arguments */
- /* Find or create symbol for 'call' entry point. */
+ /* Find or create symbol for 'call' entry point. */
callP = symbol_find_or_make (args[1]);
if (TC_S_IS_CALLNAME (callP))
} /* if only one arg, or the args are the same */
}
-
/*
s_sysproc: process .sysproc pseudo-op
return;
} /* bad arg count */
- /* Parse "entry_num" argument and check it for validity. */
+ /* Parse "entry_num" argument and check it for validity. */
parse_expr (args[2], &exp);
if (exp.X_op != O_constant
|| (offs (exp) < 0)
TC_S_FORCE_TO_SYSPROC (symP);
}
-
/*****************************************************************************
shift_ok:
Determine if a "shlo" instruction can be used to implement a "ldconst".
return shift;
}
-
/* syntax: issue syntax error */
static void
as_bad (_("syntax error"));
} /* syntax() */
-
/* targ_has_sfr:
Return TRUE iff the target architecture supports the specified
}
}
-
/* targ_has_iclass:
Return TRUE iff the target architecture supports the indicated
demand_empty_rest_of_line ();
}
-/* We have no need to default values of symbols. */
+/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
char *name;
/* Exactly what point is a PC-relative offset relative TO?
On the i960, they're relative to the address of the instruction,
- which we have set up as the address of the fixup too. */
+ which we have set up as the address of the fixup too. */
long
md_pcrel_from (fixP)
fixS *fixP;
ri.r_index = S_GET_TYPE (symbolP);
}
- /* Output the relocation information in machine-dependent form. */
+ /* Output the relocation information in machine-dependent form. */
md_ri_to_chars (where, &ri);
}
if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
{
/* Relocation should be done via the associated 'bal'
- entry point symbol. */
+ entry point symbol. */
if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
{
displacement and are only to be used for local branches:
flag as error, don't generate relocation. */
as_bad (_("can't use COBR format with external label"));
- fixP->fx_addsy = NULL; /* No relocations please. */
+ fixP->fx_addsy = NULL; /* No relocations please. */
return 1;
}
}
projects / deliverable / binutils-gdb.git / blobdiff