/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
- Copyright (C) 1998, 1999 Free Software Foundation.
+ Copyright (C) 1998, 1999, 2000 Free Software Foundation.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GAS, the GNU Assembler.
.previous
.psr
.pushsection
- .save
- .vframe
- labels are wrong if automatic alignment is introduced
(e.g., checkout the second real10 definition in test-data.s)
- DV-related stuff:
- <reg>.safe_across_calls and any other DV-related directives I don't
- have documentation for.
- verify mod-sched-brs reads/writes are checked/marked (and other
- notes)
+ <reg>.safe_across_calls and any other DV-related directives I don't
+ have documentation for.
+ verify mod-sched-brs reads/writes are checked/marked (and other
+ notes)
*/
IND_PMC,
IND_PMD,
IND_RR,
+ /* The following pseudo-registers are used for unwind directives only: */
+ REG_PSP,
+ REG_PRIUNAT,
REG_NUM
};
track of the list of labels that appear in front of each
instruction. */
struct label_fix
- {
- struct label_fix *next;
- struct symbol *sym;
- };
+{
+ struct label_fix *next;
+ struct symbol *sym;
+};
extern int target_big_endian;
as in 0d1.0. */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
-/* ia64-specific option processing: */
+/* ia64-specific option processing: */
-const char *md_shortopts = "M:N:x::";
+const char *md_shortopts = "m:N:x::";
struct option md_longopts[] =
{
- { NULL, no_argument, NULL, 0}
+#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
+ {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
+#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
+ {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
};
size_t md_longopts_size = sizeof (md_longopts);
expressionS qp;
unsigned int
- manual_bundling : 1,
+ manual_bundling : 1,
debug_dv: 1,
detect_dv: 1,
explicit_mode : 1, /* which mode we're in */
/* Each bundle consists of up to three instructions. We keep
track of four most recent instructions so we can correctly set
- the end_of_insn_group for the last instruction in a bundle. */
+ the end_of_insn_group for the last instruction in a bundle. */
int curr_slot;
int num_slots_in_use;
struct slot
fixup[2]; /* at most two fixups per insn */
struct ia64_opcode *idesc;
struct label_fix *label_fixups;
+ struct label_fix *tag_fixups;
struct unw_rec_list *unwind_record; /* Unwind directive. */
expressionS opnd[6];
char *src_file;
int path; /* number of alt. entry points seen */
const char **entry_labels; /* labels of all alternate paths in
- the current DV-checking block. */
+ the current DV-checking block. */
int maxpaths; /* size currently allocated for
- entry_labels */
+ entry_labels */
}
md;
-/* application registers: */
+/* application registers: */
-#define AR_K0 0
-#define AR_K7 7
-#define AR_RSC 16
-#define AR_BSP 17
-#define AR_BSPSTORE 18
-#define AR_RNAT 19
-#define AR_UNAT 36
-#define AR_FPSR 40
-#define AR_ITC 44
+#define AR_K0 0
+#define AR_K7 7
+#define AR_RSC 16
+#define AR_BSP 17
+#define AR_BSPSTORE 18
+#define AR_RNAT 19
+#define AR_UNAT 36
+#define AR_FPSR 40
+#define AR_ITC 44
+#define AR_PFS 64
+#define AR_LC 65
static const struct
{
{"ar.ccv", 32}, {"ar.unat", 36},
{"ar.fpsr", 40}, {"ar.itc", 44},
{"ar.pfs", 64}, {"ar.lc", 65},
- {"ar.ec", 66},
+ {"ar.ec", 66},
};
#define CR_IPSR 16
#define CR_LRR0 80
#define CR_LRR1 81
-/* control registers: */
+/* control registers: */
static const struct
{
const char *name;
}
const_bits[] =
{
- /* PSR constant masks: */
+ /* PSR constant masks: */
/* 0: reserved */
{"psr.be", ((valueT) 1) << 1},
{"psr.bn", ((valueT) 1) << 44},
};
-/* indirect register-sets/memory: */
+/* indirect register-sets/memory: */
static const struct
{
PSEUDO_FUNC_NONE,
PSEUDO_FUNC_RELOC,
PSEUDO_FUNC_CONST,
+ PSEUDO_FUNC_REG,
PSEUDO_FUNC_FLOAT
}
type;
}
pseudo_func[] =
{
- /* reloc pseudo functions (these must come first!): */
+ /* reloc pseudo functions (these must come first!): */
{ "fptr", PSEUDO_FUNC_RELOC },
{ "gprel", PSEUDO_FUNC_RELOC },
{ "ltoff", PSEUDO_FUNC_RELOC },
{ "ltv", PSEUDO_FUNC_RELOC },
{ 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
- /* mbtype4 constants: */
+ /* mbtype4 constants: */
{ "alt", PSEUDO_FUNC_CONST, { 0xa } },
{ "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
{ "mix", PSEUDO_FUNC_CONST, { 0x8 } },
{ "rev", PSEUDO_FUNC_CONST, { 0xb } },
{ "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
- /* fclass constants: */
+ /* fclass constants: */
{ "nat", PSEUDO_FUNC_CONST, { 0x100 } },
{ "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
{ "snan", PSEUDO_FUNC_CONST, { 0x040 } },
{ "inf", PSEUDO_FUNC_CONST, { 0x020 } },
{ "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
+
+ /* unwind-related constants: */
+ { "svr4", PSEUDO_FUNC_CONST, { 0 } },
+ { "hpux", PSEUDO_FUNC_CONST, { 1 } },
+ { "nt", PSEUDO_FUNC_CONST, { 2 } },
+
+ /* unwind-related registers: */
+ { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
};
-/* 41-bit nop opcodes (one per unit): */
+/* 41-bit nop opcodes (one per unit): */
static const bfd_vma nop[IA64_NUM_UNITS] =
{
0x0000000000LL, /* NIL => break 0 */
char *file; /* what file marked this dependency */
int line; /* what line marked this dependency */
struct mem_offset mem_offset; /* optional memory offset hint */
+ enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
int path; /* corresponding code entry index */
} *regdeps = NULL;
static int regdepslen = 0;
static int regdepstotlen = 0;
static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
static const char *dv_sem[] = { "none", "implied", "impliedf",
- "data", "instr", "specific", "other" };
+ "data", "instr", "specific", "stop", "other" };
+static const char *dv_cmp_type[] = { "none", "OR", "AND" };
/* Current state of PR mutexation */
static struct qpmutex {
} *qp_mutexes = NULL; /* QP mutex bitmasks */
static int qp_mutexeslen = 0;
static int qp_mutexestotlen = 0;
-static valueT qp_safe_across_calls = 0;
+static valueT qp_safe_across_calls = 0;
/* Current state of PR implications */
static struct qp_imply {
static int qp_implieslen = 0;
static int qp_impliestotlen = 0;
-/* Keep track of static GR values so that indirect register usage can
- sometimes be tracked. */
+/* Keep track of static GR values so that indirect register usage can
+ sometimes be tracked. */
static struct gr {
unsigned known:1;
int path;
/* These are the routines required to output the various types of
unwind records. */
+/* A slot_number is a frag address plus the slot index (0-2). We use the
+ frag address here so that if there is a section switch in the middle of
+ a function, then instructions emitted to a different section are not
+ counted. Since there may be more than one frag for a function, this
+ means we also need to keep track of which frag this address belongs to
+ so we can compute inter-frag distances. This also nicely solves the
+ problem with nops emitted for align directives, which can't easily be
+ counted, but can easily be derived from frag sizes. */
+
typedef struct unw_rec_list {
unwind_record r;
- unsigned long slot_number;
+ unsigned long slot_number;
+ fragS *slot_frag;
struct unw_rec_list *next;
} unw_rec_list;
#define SLOT_NUM_NOT_SET -1
-/* TRUE if processing unwind directives in a prologue region. */
-static int unwind_prologue = 0;
+static struct
+{
+ unsigned long next_slot_number;
+ fragS *next_slot_frag;
+
+ /* Maintain a list of unwind entries for the current function. */
+ unw_rec_list *list;
+ unw_rec_list *tail;
-/* Maintain a list of unwind entries for the current function. */
-static unw_rec_list *unwind_list = 0;
-static unw_rec_list *unwind_tail = 0;
+ /* Any unwind entires that should be attached to the current slot
+ that an insn is being constructed for. */
+ unw_rec_list *current_entry;
-/* Any unwind entires that should be attached to the current
- slot that an insn is being constructed for. */
-static unw_rec_list *current_unwind_entry = 0;
+ /* These are used to create the unwind table entry for this function. */
+ symbolS *proc_start;
+ symbolS *proc_end;
+ symbolS *info; /* pointer to unwind info */
+ symbolS *personality_routine;
-/* These are used to create the unwind table entry for this function. */
-static symbolS *proc_start = 0;
-static symbolS *proc_end = 0;
-static symbolS *unwind_info = 0;
-static symbolS *personality_routine = 0;
+ /* TRUE if processing unwind directives in a prologue region. */
+ int prologue;
+ int prologue_mask;
+} unwind;
typedef void (*vbyte_func) PARAMS ((int, char *, char *));
-/* Forward delarations: */
+/* Forward delarations: */
static int ar_is_in_integer_unit PARAMS ((int regnum));
static void set_section PARAMS ((char *name));
static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
static void dot_proc PARAMS ((int));
static void dot_fframe PARAMS ((int));
static void dot_vframe PARAMS ((int));
+static void dot_vframesp PARAMS ((int));
+static void dot_vframepsp PARAMS ((int));
static void dot_save PARAMS ((int));
static void dot_restore PARAMS ((int));
+static void dot_restorereg PARAMS ((int));
+static void dot_restorereg_p PARAMS ((int));
static void dot_handlerdata PARAMS ((int));
static void dot_unwentry PARAMS ((int));
static void dot_altrp PARAMS ((int));
-static void dot_savesp PARAMS ((int));
-static void dot_savepsp PARAMS ((int));
+static void dot_savemem PARAMS ((int));
static void dot_saveg PARAMS ((int));
static void dot_savef PARAMS ((int));
static void dot_saveb PARAMS ((int));
static void dot_savegf PARAMS ((int));
static void dot_spill PARAMS ((int));
+static void dot_spillreg PARAMS ((int));
+static void dot_spillmem PARAMS ((int));
+static void dot_spillreg_p PARAMS ((int));
+static void dot_spillmem_p PARAMS ((int));
+static void dot_label_state PARAMS ((int));
+static void dot_copy_state PARAMS ((int));
static void dot_unwabi PARAMS ((int));
static void dot_personality PARAMS ((int));
static void dot_body PARAMS ((int));
static void dot_xstringer PARAMS ((int));
static void dot_xdata_ua PARAMS ((int));
static void dot_xfloat_cons_ua PARAMS ((int));
+static void print_prmask PARAMS ((valueT mask));
static void dot_pred_rel PARAMS ((int));
static void dot_reg_val PARAMS ((int));
static void dot_dv_mode PARAMS ((int));
static void dot_entry PARAMS ((int));
static void dot_mem_offset PARAMS ((int));
-static symbolS* declare_register PARAMS ((const char *name, int regnum));
+static void add_unwind_entry PARAMS((unw_rec_list *ptr));
+static symbolS *declare_register PARAMS ((const char *name, int regnum));
static void declare_register_set PARAMS ((const char *, int, int));
static unsigned int operand_width PARAMS ((enum ia64_opnd));
static int operand_match PARAMS ((const struct ia64_opcode *idesc,
static void build_insn PARAMS ((struct slot *, bfd_vma *));
static void emit_one_bundle PARAMS ((void));
static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
-static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
+static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
bfd_reloc_code_real_type r_type));
static void insn_group_break PARAMS ((int, int, int));
+static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
+ struct rsrc *, int depind, int path));
static void add_qp_mutex PARAMS((valueT mask));
static void add_qp_imply PARAMS((int p1, int p2));
static void clear_qp_branch_flag PARAMS((valueT mask));
static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
static void clear_register_values PARAMS ((void));
static void print_dependency PARAMS ((const char *action, int depind));
+static void instruction_serialization PARAMS ((void));
+static void data_serialization PARAMS ((void));
+static void remove_marked_resource PARAMS ((struct rsrc *));
static int is_conditional_branch PARAMS ((struct ia64_opcode *));
+static int is_taken_branch PARAMS ((struct ia64_opcode *));
static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
+static int depends_on PARAMS ((int, struct ia64_opcode *));
+static int specify_resource PARAMS ((const struct ia64_dependency *,
+ struct ia64_opcode *, int, struct rsrc [], int, int));
static int check_dv PARAMS((struct ia64_opcode *idesc));
static void check_dependencies PARAMS((struct ia64_opcode *));
static void mark_resources PARAMS((struct ia64_opcode *));
static void update_dependencies PARAMS((struct ia64_opcode *));
static void note_register_values PARAMS((struct ia64_opcode *));
+static int qp_mutex PARAMS ((int, int, int));
+static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
+static void output_vbyte_mem PARAMS ((int, char *, char *));
+static void count_output PARAMS ((int, char *, char *));
+static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
+static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+static void output_P1_format PARAMS ((vbyte_func, int));
+static void output_P2_format PARAMS ((vbyte_func, int, int));
+static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
+static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
+static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
+static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
+static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
+static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+static void output_P9_format PARAMS ((vbyte_func, int, int));
+static void output_P10_format PARAMS ((vbyte_func, int, int));
+static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+static char format_ab_reg PARAMS ((int, int));
+static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
+ unsigned long));
+static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
+static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
+ unsigned long));
+static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
+static void free_list_records PARAMS ((unw_rec_list *));
+static unw_rec_list *output_prologue PARAMS ((void));
+static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
+static unw_rec_list *output_body PARAMS ((void));
+static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
+static unw_rec_list *output_mem_stack_v PARAMS ((void));
+static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
+static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_rp_when PARAMS ((void));
+static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
+static unw_rec_list *output_rp_br PARAMS ((unsigned int));
+static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_pfs_when PARAMS ((void));
+static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
+static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_preds_when PARAMS ((void));
+static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
+static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
+static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
+static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
+static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
+static unw_rec_list *output_br_mem PARAMS ((unsigned int));
+static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
+static unw_rec_list *output_spill_base PARAMS ((unsigned int));
+static unw_rec_list *output_unat_when PARAMS ((void));
+static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
+static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_lc_when PARAMS ((void));
+static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
+static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_fpsr_when PARAMS ((void));
+static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
+static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_priunat_when_gr PARAMS ((void));
+static unw_rec_list *output_priunat_when_mem PARAMS ((void));
+static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
+static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_bsp_when PARAMS ((void));
+static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
+static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_bspstore_when PARAMS ((void));
+static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
+static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_rnat_when PARAMS ((void));
+static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
+static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
+static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
+static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
+static unw_rec_list *output_epilogue PARAMS ((unsigned long));
+static unw_rec_list *output_label_state PARAMS ((unsigned long));
+static unw_rec_list *output_copy_state PARAMS ((unsigned long));
+static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
+static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
+static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
+ unsigned int));
+static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
+ unsigned int));
+static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
+ unsigned int));
+static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int));
+static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
+static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
+static int calc_record_size PARAMS ((unw_rec_list *));
+static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
+static int count_bits PARAMS ((unsigned long));
+static unsigned long slot_index PARAMS ((unsigned long, fragS *,
+ unsigned long, fragS *));
+static void fixup_unw_records PARAMS ((unw_rec_list *));
+static int output_unw_records PARAMS ((unw_rec_list *, void **));
+static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
+static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
+static int generate_unwind_image PARAMS ((void));
/* Determine if application register REGNUM resides in the integer
unit (as opposed to the memory unit). */
set_regstack (ins, locs, outs, rots)
unsigned int ins, locs, outs, rots;
{
- unsigned int sof; /* size of frame */
+ /* Size of frame. */
+ unsigned int sof;
sof = ins + locs + outs;
if (sof > 96)
emit_one_bundle (); /* force out queued instructions */
/* In case there are labels following the last instruction, resolve
- those now: */
+ those now: */
for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
{
S_SET_VALUE (lfix->sym, frag_now_fix ());
symbol_set_frag (lfix->sym, frag_now);
}
CURR_SLOT.label_fixups = 0;
+ for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
+ {
+ S_SET_VALUE (lfix->sym, frag_now_fix ());
+ symbol_set_frag (lfix->sym, frag_now);
+ }
+ CURR_SLOT.tag_fixups = 0;
subseg_set (saved_seg, saved_subseg);
+
+ if (md.qp.X_op == O_register)
+ as_bad ("qualifying predicate not followed by instruction");
}
void
/* Output COUNT bytes to a memory location. */
static unsigned char *vbyte_mem_ptr = NULL;
-void
+void
output_vbyte_mem (count, ptr, comment)
int count;
char *ptr;
/* Count the number of bytes required for records. */
static int vbyte_count = 0;
-void
+void
count_output (count, ptr, comment)
int count;
char *ptr;
unw_record_type rtype;
int rlen;
{
- int r;
+ int r = 0;
char byte;
if (rlen > 0x1f)
{
output_R3_format (f, rtype, rlen);
return;
}
- if (rtype == prologue)
- r = 0;
- else
- if (rtype == body)
- r = 1;
- else
- as_bad ("record type is not valid");
-
+
+ if (rtype == body)
+ r = 1;
+ else if (rtype != prologue)
+ as_bad ("record type is not valid");
+
byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
(*f) (1, &byte, NULL);
}
unw_record_type rtype;
unsigned long rlen;
{
- int r, count;
+ int r = 0, count;
char bytes[20];
if (rlen <= 0x1f)
{
output_R1_format (f, rtype, rlen);
return;
}
- if (rtype == prologue)
- r = 0;
- else
- if (rtype == body)
- r = 1;
- else
- as_bad ("record type is not valid");
+
+ if (rtype == body)
+ r = 1;
+ else if (rtype != prologue)
+ as_bad ("record type is not valid");
bytes[0] = (UNW_R3 | r);
count = output_leb128 (bytes + 1, rlen, 0);
(*f) (count + 1, bytes, NULL);
int reg;
{
char bytes[2];
- int r;
+ int r = 0;
reg = (reg & 0x7f);
switch (rtype)
- {
+ {
case psp_gr:
r = 0;
break;
break;
default:
as_bad ("Invalid record type for P3 format.");
- }
+ }
bytes[0] = (UNW_P3 | (r >> 1));
bytes[1] = (((r & 1) << 7) | reg);
(*f) (2, bytes, NULL);
}
-
static void
-output_P4_format (f, count, imask)
+output_P4_format (f, imask, imask_size)
vbyte_func f;
- int count;
- char *imask;
+ unsigned char *imask;
+ unsigned long imask_size;
{
- char *bytes;
- bytes = alloca (count + 1);
- bytes[0] = UNW_P4;
- memcpy (bytes + 1, imask, count);
- (*f) (count + 1, bytes, NULL);
+ imask[0] = UNW_P4;
+ (*f) (imask_size, imask, NULL);
}
static void
int rmask;
{
char byte;
- int r;
- if (rtype == fr_mem)
- r = 0;
- else
- if (rtype == gr_mem)
- r = 1;
- else
- as_bad ("Invalid record type for format P6");
+ int r = 0;
+
+ if (rtype == gr_mem)
+ r = 1;
+ else if (rtype != fr_mem)
+ as_bad ("Invalid record type for format P6");
byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
(*f) (1, &byte, NULL);
}
{
char bytes[20];
int count = 1;
- int r;
+ int r = 0;
count += output_leb128 (bytes + 1, w1, 0);
switch (rtype)
{
- case mem_stack_f:
- r = 0;
- count += output_leb128 (bytes + count, w2 >> 4, 0);
- break;
- case mem_stack_v:
- r = 1;
- break;
- case spill_base:
- r = 2;
- break;
- case psp_sprel:
- r = 3;
- break;
- case rp_when:
- r = 4;
- break;
- case rp_psprel:
- r = 5;
- break;
- case pfs_when:
- r = 6;
- break;
- case pfs_psprel:
- r = 7;
- break;
- case preds_when:
- r = 8;
- break;
- case preds_psprel:
- r = 9;
- break;
- case lc_when:
- r = 10;
- break;
- case lc_psprel:
- r = 11;
- break;
- case unat_when:
- r = 12;
- break;
- case unat_psprel:
- r = 13;
- break;
- case fpsr_when:
- r = 14;
- break;
- case fpsr_psprel:
- r = 15;
- break;
+ case mem_stack_f:
+ r = 0;
+ count += output_leb128 (bytes + count, w2 >> 4, 0);
+ break;
+ case mem_stack_v:
+ r = 1;
+ break;
+ case spill_base:
+ r = 2;
+ break;
+ case psp_sprel:
+ r = 3;
+ break;
+ case rp_when:
+ r = 4;
+ break;
+ case rp_psprel:
+ r = 5;
+ break;
+ case pfs_when:
+ r = 6;
+ break;
+ case pfs_psprel:
+ r = 7;
+ break;
+ case preds_when:
+ r = 8;
+ break;
+ case preds_psprel:
+ r = 9;
+ break;
+ case lc_when:
+ r = 10;
+ break;
+ case lc_psprel:
+ r = 11;
+ break;
+ case unat_when:
+ r = 12;
+ break;
+ case unat_psprel:
+ r = 13;
+ break;
+ case fpsr_when:
+ r = 14;
+ break;
+ case fpsr_psprel:
+ r = 15;
+ break;
+ default:
+ break;
}
bytes[0] = (UNW_P7 | r);
(*f) (count, bytes, NULL);
unsigned long t;
{
char bytes[20];
- int r;
+ int r = 0;
int count = 2;
bytes[0] = UNW_P8;
switch (rtype)
{
- case rp_sprel:
- r = 1;
- break;
- case pfs_sprel:
- r = 2;
- break;
- case preds_sprel:
- r = 3;
- break;
- case lc_sprel:
- r = 4;
- break;
- case unat_sprel:
- r = 5;
- break;
- case fpsr_sprel:
- r = 6;
- break;
- case bsp_when:
- r = 7;
- break;
- case bsp_psprel:
- r = 8;
- break;
- case bsp_sprel:
- r = 9;
- break;
- case bspstore_when:
- r = 10;
- break;
- case bspstore_psprel:
- r = 11;
- break;
- case bspstore_sprel:
- r = 12;
- break;
- case rnat_when:
- r = 13;
- break;
- case rnat_psprel:
- r = 14;
- break;
- case rnat_sprel:
- r = 15;
- break;
- case priunat_when_gr:
- r = 16;
- break;
- case priunat_psprel:
- r = 17;
- break;
- case priunat_sprel:
- r = 18;
- break;
- case priunat_when_mem:
- r = 19;
- break;
+ case rp_sprel:
+ r = 1;
+ break;
+ case pfs_sprel:
+ r = 2;
+ break;
+ case preds_sprel:
+ r = 3;
+ break;
+ case lc_sprel:
+ r = 4;
+ break;
+ case unat_sprel:
+ r = 5;
+ break;
+ case fpsr_sprel:
+ r = 6;
+ break;
+ case bsp_when:
+ r = 7;
+ break;
+ case bsp_psprel:
+ r = 8;
+ break;
+ case bsp_sprel:
+ r = 9;
+ break;
+ case bspstore_when:
+ r = 10;
+ break;
+ case bspstore_psprel:
+ r = 11;
+ break;
+ case bspstore_sprel:
+ r = 12;
+ break;
+ case rnat_when:
+ r = 13;
+ break;
+ case rnat_psprel:
+ r = 14;
+ break;
+ case rnat_sprel:
+ r = 15;
+ break;
+ case priunat_when_gr:
+ r = 16;
+ break;
+ case priunat_psprel:
+ r = 17;
+ break;
+ case priunat_sprel:
+ r = 18;
+ break;
+ case priunat_when_mem:
+ r = 19;
+ break;
+ default:
+ break;
}
bytes[1] = r;
count += output_leb128 (bytes + 2, t, 0);
unsigned long label;
{
char byte;
- int r;
- if (label > 0x1f)
+ int r = 0;
+ if (label > 0x1f)
{
output_B4_format (f, rtype, label);
return;
}
- if (rtype == label_state)
- r = 0;
- else
- if (rtype == copy_state)
- r = 1;
- else
- as_bad ("Invalid record type for format B1");
+ if (rtype == copy_state)
+ r = 1;
+ else if (rtype != label_state)
+ as_bad ("Invalid record type for format B1");
byte = (UNW_B1 | (r << 5) | (label & 0x1f));
(*f) (1, &byte, NULL);
unsigned long label;
{
char bytes[20];
- int r;
+ int r = 0;
int count = 1;
- if (label <= 0x1f)
+ if (label <= 0x1f)
{
output_B1_format (f, rtype, label);
return;
}
- if (rtype == label_state)
- r = 0;
- else
- if (rtype == copy_state)
- r = 1;
- else
- as_bad ("Invalid record type for format B1");
+
+ if (rtype == copy_state)
+ r = 1;
+ else if (rtype != label_state)
+ as_bad ("Invalid record type for format B1");
bytes[0] = (UNW_B4 | (r << 3));
count += output_leb128 (bytes + 1, label, 0);
}
static char
-format_a_b_reg (a, b, reg)
- int a, b;
- int reg;
+format_ab_reg (ab, reg)
+ int ab;
+ int reg;
{
int ret;
- a = (a & 1);
- b = (b & 1);
+ ab = (ab & 3);
reg = (reg & 0x1f);
- ret = (a << 6) | (a << 5) | reg;
+ ret = (ab << 5) | reg;
return ret;
}
static void
-output_X1_format (f, rtype, a, b, reg, t, w1)
+output_X1_format (f, rtype, ab, reg, t, w1)
vbyte_func f;
unw_record_type rtype;
- int a, b, reg;
+ int ab, reg;
unsigned long t;
unsigned long w1;
{
char bytes[20];
- int r;
+ int r = 0;
int count = 2;
bytes[0] = UNW_X1;
- if (rtype == spill_psprel)
- r = 0;
- else
- if (rtype = spill_sprel)
- r = 1;
- else
- as_bad ("Invalid record type for format X1");
- bytes[1] = ((r << 7) | format_a_b_reg (a, b, reg));
+
+ if (rtype == spill_sprel)
+ r = 1;
+ else if (rtype != spill_psprel)
+ as_bad ("Invalid record type for format X1");
+ bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
count += output_leb128 (bytes + 2, t, 0);
count += output_leb128 (bytes + count, w1, 0);
(*f) (count, bytes, NULL);
}
static void
-output_X2_format (f, a, b, reg, x, y, treg, t)
+output_X2_format (f, ab, reg, x, y, treg, t)
vbyte_func f;
- int a, b, reg;
+ int ab, reg;
int x, y, treg;
unsigned long t;
{
char bytes[20];
- int r;
int count = 3;
bytes[0] = UNW_X2;
- bytes[1] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
+ bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
count += output_leb128 (bytes + 3, t, 0);
(*f) (count, bytes, NULL);
}
static void
-output_X3_format (f, rtype, qp, a, b, reg, t, w1)
+output_X3_format (f, rtype, qp, ab, reg, t, w1)
vbyte_func f;
unw_record_type rtype;
int qp;
- int a, b, reg;
+ int ab, reg;
unsigned long t;
unsigned long w1;
{
char bytes[20];
- int r;
+ int r = 0;
int count = 3;
- bytes[0] = UNW_X1;
- if (rtype == spill_psprel_p)
- r = 0;
- else
- if (rtype = spill_sprel_p)
- r = 1;
- else
- as_bad ("Invalid record type for format X1");
+ bytes[0] = UNW_X3;
+
+ if (rtype == spill_sprel_p)
+ r = 1;
+ else if (rtype != spill_psprel_p)
+ as_bad ("Invalid record type for format X3");
bytes[1] = ((r << 7) | (qp & 0x3f));
- bytes[2] = format_a_b_reg (a, b, reg);
+ bytes[2] = format_ab_reg (ab, reg);
count += output_leb128 (bytes + 3, t, 0);
count += output_leb128 (bytes + count, w1, 0);
(*f) (count, bytes, NULL);
}
static void
-output_X4_format (f, qp, a, b, reg, x, y, treg, t)
+output_X4_format (f, qp, ab, reg, x, y, treg, t)
vbyte_func f;
int qp;
- int a, b, reg;
+ int ab, reg;
int x, y, treg;
unsigned long t;
{
char bytes[20];
- int r;
int count = 4;
- bytes[0] = UNW_X2;
+ bytes[0] = UNW_X4;
bytes[1] = (qp & 0x3f);
- bytes[2] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
+ bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
count += output_leb128 (bytes + 4, t, 0);
(*f) (count, bytes, NULL);
}
/* This function allocates a record list structure, and initializes fields. */
+
static unw_rec_list *
-alloc_record (unw_record_type t)
+alloc_record (unw_record_type t)
{
unw_rec_list *ptr;
ptr = xmalloc (sizeof (*ptr));
return ptr;
}
-/* This function frees a record list structure. */
-static void
-free_record (unw_rec_list *ptr)
-{
- free (ptr);
-}
-
/* This function frees an entire list of record structures. */
+
void
free_list_records (unw_rec_list *first)
{
unw_rec_list *ptr;
- for (ptr = first; ptr != NULL; )
+ for (ptr = first; ptr != NULL;)
{
unw_rec_list *tmp = ptr;
+
+ if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
+ && tmp->r.record.r.mask.i)
+ free (tmp->r.record.r.mask.i);
+
ptr = ptr->next;
free (tmp);
}
output_prologue ()
{
unw_rec_list *ptr = alloc_record (prologue);
+ memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
return ptr;
}
unsigned int reg;
{
unw_rec_list *ptr = alloc_record (prologue_gr);
- ptr->r.record.r.mask = saved_mask;
+ memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
+ ptr->r.record.r.grmask = saved_mask;
ptr->r.record.r.grsave = reg;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (psp_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (rp_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (rp_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (pfs_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (pfs_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (preds_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (preds_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (spill_base);
- ptr->r.record.p.pspoff = offset;
- return ptr;
-}
-
-static unw_rec_list *
-output_spill_mask ()
-{
-/* TODO - how to implement this record.... I guess GAS could fill in the
- correct fields from the record list and construct one of these
- after the symbols have been resolved and we know how big the
- region is. This could be done in fixup_unw_records. */
- unw_rec_list *ptr = NULL;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (unat_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (unat_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (lc_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (lc_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (fpsr_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (fpsr_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (priunat_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (priunat_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (bsp_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (bsp_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (bspstore_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (bspstore_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (rnat_psprel);
- ptr->r.record.p.pspoff = offset;
+ ptr->r.record.p.pspoff = offset / 4;
return ptr;
}
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (rnat_sprel);
- ptr->r.record.p.spoff = offset;
+ ptr->r.record.p.spoff = offset / 4;
return ptr;
}
static unw_rec_list *
-output_epilogue ()
+output_unwabi (abi, context)
+ unsigned long abi;
+ unsigned long context;
{
- unw_rec_list *ptr = NULL;
+ unw_rec_list *ptr = alloc_record (unwabi);
+ ptr->r.record.p.abi = abi;
+ ptr->r.record.p.context = context;
return ptr;
}
static unw_rec_list *
-output_label_state ()
+output_epilogue (unsigned long ecount)
{
- unw_rec_list *ptr = NULL;
+ unw_rec_list *ptr = alloc_record (epilogue);
+ ptr->r.record.b.ecount = ecount;
return ptr;
}
static unw_rec_list *
-output_copy_state ()
+output_label_state (unsigned long label)
{
- unw_rec_list *ptr = NULL;
+ unw_rec_list *ptr = alloc_record (label_state);
+ ptr->r.record.b.label = label;
return ptr;
}
static unw_rec_list *
-output_spill_psprel (reg, offset)
+output_copy_state (unsigned long label)
+{
+ unw_rec_list *ptr = alloc_record (copy_state);
+ ptr->r.record.b.label = label;
+ return ptr;
+}
+
+static unw_rec_list *
+output_spill_psprel (ab, reg, offset)
+ unsigned int ab;
unsigned int reg;
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (spill_psprel);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
- ptr->r.record.x.pspoff = offset;
+ ptr->r.record.x.pspoff = offset / 4;
return ptr;
}
static unw_rec_list *
-output_spill_sprel (reg, offset)
+output_spill_sprel (ab, reg, offset)
+ unsigned int ab;
unsigned int reg;
unsigned int offset;
{
unw_rec_list *ptr = alloc_record (spill_sprel);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
- ptr->r.record.x.spoff = offset;
+ ptr->r.record.x.spoff = offset / 4;
return ptr;
}
static unw_rec_list *
-output_spill_psprel_p (reg, offset, predicate)
+output_spill_psprel_p (ab, reg, offset, predicate)
+ unsigned int ab;
unsigned int reg;
unsigned int offset;
unsigned int predicate;
{
unw_rec_list *ptr = alloc_record (spill_psprel_p);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
- ptr->r.record.x.pspoff = offset;
+ ptr->r.record.x.pspoff = offset / 4;
ptr->r.record.x.qp = predicate;
return ptr;
}
static unw_rec_list *
-output_spill_sprel_p (reg, offset, predicate)
+output_spill_sprel_p (ab, reg, offset, predicate)
+ unsigned int ab;
unsigned int reg;
unsigned int offset;
unsigned int predicate;
{
unw_rec_list *ptr = alloc_record (spill_sprel_p);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
- ptr->r.record.x.spoff = offset;
+ ptr->r.record.x.spoff = offset / 4;
ptr->r.record.x.qp = predicate;
return ptr;
}
static unw_rec_list *
-output_spill_reg (reg, targ_reg, xy)
+output_spill_reg (ab, reg, targ_reg, xy)
+ unsigned int ab;
unsigned int reg;
unsigned int targ_reg;
unsigned int xy;
{
unw_rec_list *ptr = alloc_record (spill_reg);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
ptr->r.record.x.treg = targ_reg;
ptr->r.record.x.xy = xy;
}
static unw_rec_list *
-output_spill_reg_p (reg, targ_reg, xy, predicate)
+output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
+ unsigned int ab;
unsigned int reg;
unsigned int targ_reg;
unsigned int xy;
unsigned int predicate;
{
unw_rec_list *ptr = alloc_record (spill_reg_p);
+ ptr->r.record.x.ab = ab;
ptr->r.record.x.reg = reg;
ptr->r.record.x.treg = targ_reg;
ptr->r.record.x.xy = xy;
return ptr;
}
-/* Given a unw_rec_list process the correct format with the
+/* Given a unw_rec_list process the correct format with the
specified function. */
+
static void
process_one_record (ptr, f)
unw_rec_list *ptr;
vbyte_func f;
{
- switch (ptr->r.type)
+ unsigned long fr_mask, gr_mask;
+
+ switch (ptr->r.type)
{
- case prologue:
- case body:
- output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
- break;
- case prologue_gr:
- output_R2_format (f, ptr->r.record.r.mask,
+ case gr_mem:
+ case fr_mem:
+ case br_mem:
+ case frgr_mem:
+ /* These are taken care of by prologue/prologue_gr. */
+ break;
+
+ case prologue_gr:
+ case prologue:
+ if (ptr->r.type == prologue_gr)
+ output_R2_format (f, ptr->r.record.r.grmask,
ptr->r.record.r.grsave, ptr->r.record.r.rlen);
- break;
- case mem_stack_f:
- case mem_stack_v:
- output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
- ptr->r.record.p.size);
- break;
- case psp_gr:
- case rp_gr:
- case pfs_gr:
- case preds_gr:
- case unat_gr:
- case lc_gr:
- case fpsr_gr:
- case priunat_gr:
- case bsp_gr:
- case bspstore_gr:
- case rnat_gr:
- output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
- break;
- case rp_br:
- output_P3_format (f, rp_br, ptr->r.record.p.br);
- break;
- case psp_sprel:
- output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
- break;
- case rp_when:
- case pfs_when:
- case preds_when:
- case unat_when:
- case lc_when:
- case fpsr_when:
- output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
- break;
- case rp_psprel:
- case pfs_psprel:
- case preds_psprel:
- case unat_psprel:
- case lc_psprel:
- case fpsr_psprel:
- case spill_base:
- output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
- break;
- case rp_sprel:
- case pfs_sprel:
- case preds_sprel:
- case unat_sprel:
- case lc_sprel:
- case fpsr_sprel:
- case priunat_sprel:
- case bsp_sprel:
- case bspstore_sprel:
- case rnat_sprel:
- output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
- break;
- case fr_mem:
- case gr_mem:
- output_P6_format (f, ptr->r.type, ptr->r.record.p.rmask);
- break;
- case frgr_mem:
- output_P5_format (f, ptr->r.record.p.grmask, ptr->r.record.p.frmask);
- break;
- case gr_gr:
- output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
- break;
- case br_mem:
- output_P1_format (f, ptr->r.record.p.brmask);
- break;
- case br_gr:
- output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
- break;
- case spill_mask:
- as_bad ("spill_mask record unimplemented.");
- break;
- case priunat_when_gr:
- case priunat_when_mem:
- case bsp_when:
- case bspstore_when:
- case rnat_when:
- output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
- break;
- case priunat_psprel:
- case bsp_psprel:
- case bspstore_psprel:
- case rnat_psprel:
- output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
- break;
- case epilogue:
- as_bad ("epilogue record unimplemented.");
- break;
- case label_state:
- as_bad ("label_state record unimplemented.");
- break;
- case copy_state:
- as_bad ("copy_state record unimplemented.");
- break;
- case spill_psprel:
- case spill_sprel:
- case spill_reg:
- case spill_psprel_p:
- case spill_sprel_p:
- case spill_reg_p:
- as_bad ("spill_* record unimplemented.");
- break;
- default:
- as_bad ("record_type_not_valid");
- break;
+ else
+ output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
+
+ /* Output descriptor(s) for union of register spills (if any). */
+ gr_mask = ptr->r.record.r.mask.gr_mem;
+ fr_mask = ptr->r.record.r.mask.fr_mem;
+ if (fr_mask)
+ {
+ if ((fr_mask & ~0xfUL) == 0)
+ output_P6_format (f, fr_mem, fr_mask);
+ else
+ {
+ output_P5_format (f, gr_mask, fr_mask);
+ gr_mask = 0;
+ }
+ }
+ if (gr_mask)
+ output_P6_format (f, gr_mem, gr_mask);
+ if (ptr->r.record.r.mask.br_mem)
+ output_P1_format (f, ptr->r.record.r.mask.br_mem);
+
+ /* output imask descriptor if necessary: */
+ if (ptr->r.record.r.mask.i)
+ output_P4_format (f, ptr->r.record.r.mask.i,
+ ptr->r.record.r.imask_size);
+ break;
+
+ case body:
+ output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
+ break;
+ case mem_stack_f:
+ case mem_stack_v:
+ output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
+ ptr->r.record.p.size);
+ break;
+ case psp_gr:
+ case rp_gr:
+ case pfs_gr:
+ case preds_gr:
+ case unat_gr:
+ case lc_gr:
+ case fpsr_gr:
+ case priunat_gr:
+ case bsp_gr:
+ case bspstore_gr:
+ case rnat_gr:
+ output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
+ break;
+ case rp_br:
+ output_P3_format (f, rp_br, ptr->r.record.p.br);
+ break;
+ case psp_sprel:
+ output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
+ break;
+ case rp_when:
+ case pfs_when:
+ case preds_when:
+ case unat_when:
+ case lc_when:
+ case fpsr_when:
+ output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
+ break;
+ case rp_psprel:
+ case pfs_psprel:
+ case preds_psprel:
+ case unat_psprel:
+ case lc_psprel:
+ case fpsr_psprel:
+ case spill_base:
+ output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
+ break;
+ case rp_sprel:
+ case pfs_sprel:
+ case preds_sprel:
+ case unat_sprel:
+ case lc_sprel:
+ case fpsr_sprel:
+ case priunat_sprel:
+ case bsp_sprel:
+ case bspstore_sprel:
+ case rnat_sprel:
+ output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
+ break;
+ case gr_gr:
+ output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
+ break;
+ case br_gr:
+ output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
+ break;
+ case spill_mask:
+ as_bad ("spill_mask record unimplemented.");
+ break;
+ case priunat_when_gr:
+ case priunat_when_mem:
+ case bsp_when:
+ case bspstore_when:
+ case rnat_when:
+ output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
+ break;
+ case priunat_psprel:
+ case bsp_psprel:
+ case bspstore_psprel:
+ case rnat_psprel:
+ output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
+ break;
+ case unwabi:
+ output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
+ break;
+ case epilogue:
+ output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
+ break;
+ case label_state:
+ case copy_state:
+ output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
+ break;
+ case spill_psprel:
+ output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
+ ptr->r.record.x.reg, ptr->r.record.x.t,
+ ptr->r.record.x.pspoff);
+ break;
+ case spill_sprel:
+ output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
+ ptr->r.record.x.reg, ptr->r.record.x.t,
+ ptr->r.record.x.spoff);
+ break;
+ case spill_reg:
+ output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
+ ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
+ ptr->r.record.x.treg, ptr->r.record.x.t);
+ break;
+ case spill_psprel_p:
+ output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
+ ptr->r.record.x.ab, ptr->r.record.x.reg,
+ ptr->r.record.x.t, ptr->r.record.x.pspoff);
+ break;
+ case spill_sprel_p:
+ output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
+ ptr->r.record.x.ab, ptr->r.record.x.reg,
+ ptr->r.record.x.t, ptr->r.record.x.spoff);
+ break;
+ case spill_reg_p:
+ output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
+ ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
+ ptr->r.record.x.xy, ptr->r.record.x.treg,
+ ptr->r.record.x.t);
+ break;
+ default:
+ as_bad ("record_type_not_valid");
+ break;
}
}
-/* Given a unw_rec_list list, process all the records with
+/* Given a unw_rec_list list, process all the records with
the specified function. */
static void
process_unw_records (list, f)
return vbyte_count;
}
-/* Given a complete record list, process any records which have
- unresolved fields, (ie length counts for a prologue). After
- this has been run, all neccessary information should be available
- within each record to generate an image. */
+/* Update IMASK bitmask to reflect the fact that one or more registers
+ of type TYPE are saved starting at instruction with index T. If N
+ bits are set in REGMASK, it is assumed that instructions T through
+ T+N-1 save these registers.
+
+ TYPE values:
+ 0: no save
+ 1: instruction saves next fp reg
+ 2: instruction saves next general reg
+ 3: instruction saves next branch reg */
static void
-fixup_unw_records (list)
- unw_rec_list *list;
+set_imask (region, regmask, t, type)
+ unw_rec_list *region;
+ unsigned long regmask;
+ unsigned long t;
+ unsigned int type;
{
- unw_rec_list *ptr;
- unsigned long first_addr = 0;
- for (ptr = list; ptr; ptr = ptr->next)
+ unsigned char *imask;
+ unsigned long imask_size;
+ unsigned int i;
+ int pos;
+
+ imask = region->r.record.r.mask.i;
+ imask_size = region->r.record.r.imask_size;
+ if (!imask)
{
- if (ptr->slot_number == SLOT_NUM_NOT_SET)
- as_bad (" Insn slot not set in unwind record.");
- switch (ptr->r.type)
+ imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
+ imask = xmalloc (imask_size);
+ memset (imask, 0, imask_size);
+
+ region->r.record.r.imask_size = imask_size;
+ region->r.record.r.mask.i = imask;
+ }
+
+ i = (t / 4) + 1;
+ pos = 2 * (3 - t % 4);
+ while (regmask)
+ {
+ if (i >= imask_size)
{
- case prologue:
- case prologue_gr:
- case body:
- {
- unw_rec_list *last;
- int size;
- unsigned long last_addr;
- first_addr = ptr->slot_number;
- ptr->slot_number = 0;
- /* Find either the next body/prologue start, or the end of
- the list, and determine the size of the region. */
- for (last = ptr; last->next != NULL; last = last->next)
- if (last->next->r.type == prologue
- || last->next->r.type == prologue_gr
- || last->next->r.type == body)
- {
- break;
- }
- last_addr = last->slot_number;
- size = ((last_addr - first_addr) / 16) * 3 + last_addr % 4;
- ptr->r.record.r.rlen = size;
- break;
+ as_bad ("Ignoring attempt to spill beyond end of region");
+ return;
+ }
+
+ imask[i] |= (type & 0x3) << pos;
+
+ regmask &= (regmask - 1);
+ pos -= 2;
+ if (pos < 0)
+ {
+ pos = 0;
+ ++i;
+ }
+ }
+}
+
+static int
+count_bits (unsigned long mask)
+{
+ int n = 0;
+
+ while (mask)
+ {
+ mask &= mask - 1;
+ ++n;
+ }
+ return n;
+}
+
+/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
+ SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
+ containing FIRST_ADDR. */
+
+unsigned long
+slot_index (slot_addr, slot_frag, first_addr, first_frag)
+ unsigned long slot_addr;
+ fragS *slot_frag;
+ unsigned long first_addr;
+ fragS *first_frag;
+{
+ unsigned long index = 0;
+
+ /* First time we are called, the initial address and frag are invalid. */
+ if (first_addr == 0)
+ return 0;
+
+ /* If the two addresses are in different frags, then we need to add in
+ the remaining size of this frag, and then the entire size of intermediate
+ frags. */
+ while (slot_frag != first_frag)
+ {
+ unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
+
+ /* Add in the full size of the frag converted to instruction slots. */
+ index += 3 * (first_frag->fr_fix >> 4);
+ /* Subtract away the initial part before first_addr. */
+ index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
+ + ((first_addr & 0x3) - (start_addr & 0x3)));
+
+ /* Move to the beginning of the next frag. */
+ first_frag = first_frag->fr_next;
+ first_addr = (unsigned long) &first_frag->fr_literal;
+ }
+
+ /* Add in the used part of the last frag. */
+ index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
+ + ((slot_addr & 0x3) - (first_addr & 0x3)));
+ return index;
+}
+
+/* Given a complete record list, process any records which have
+ unresolved fields, (ie length counts for a prologue). After
+ this has been run, all neccessary information should be available
+ within each record to generate an image. */
+
+static void
+fixup_unw_records (list)
+ unw_rec_list *list;
+{
+ unw_rec_list *ptr, *region = 0;
+ unsigned long first_addr = 0, rlen = 0, t;
+ fragS *first_frag = 0;
+
+ for (ptr = list; ptr; ptr = ptr->next)
+ {
+ if (ptr->slot_number == SLOT_NUM_NOT_SET)
+ as_bad (" Insn slot not set in unwind record.");
+ t = slot_index (ptr->slot_number, ptr->slot_frag,
+ first_addr, first_frag);
+ switch (ptr->r.type)
+ {
+ case prologue:
+ case prologue_gr:
+ case body:
+ {
+ unw_rec_list *last;
+ int size, dir_len = 0;
+ unsigned long last_addr;
+ fragS *last_frag;
+
+ first_addr = ptr->slot_number;
+ first_frag = ptr->slot_frag;
+ ptr->slot_number = 0;
+ /* Find either the next body/prologue start, or the end of
+ the list, and determine the size of the region. */
+ last_addr = unwind.next_slot_number;
+ last_frag = unwind.next_slot_frag;
+ for (last = ptr->next; last != NULL; last = last->next)
+ if (last->r.type == prologue || last->r.type == prologue_gr
+ || last->r.type == body)
+ {
+ last_addr = last->slot_number;
+ last_frag = last->slot_frag;
+ break;
+ }
+ else if (!last->next)
+ {
+ /* In the absence of an explicit .body directive,
+ the prologue ends after the last instruction
+ covered by an unwind directive. */
+ if (ptr->r.type != body)
+ {
+ last_addr = last->slot_number;
+ last_frag = last->slot_frag;
+ switch (last->r.type)
+ {
+ case frgr_mem:
+ dir_len = (count_bits (last->r.record.p.frmask)
+ + count_bits (last->r.record.p.grmask));
+ break;
+ case fr_mem:
+ case gr_mem:
+ dir_len += count_bits (last->r.record.p.rmask);
+ break;
+ case br_mem:
+ case br_gr:
+ dir_len += count_bits (last->r.record.p.brmask);
+ break;
+ case gr_gr:
+ dir_len += count_bits (last->r.record.p.grmask);
+ break;
+ default:
+ dir_len = 1;
+ break;
+ }
+ }
+ break;
+ }
+ size = (slot_index (last_addr, last_frag, first_addr, first_frag)
+ + dir_len);
+ rlen = ptr->r.record.r.rlen = size;
+ region = ptr;
+ break;
+ }
+ case epilogue:
+ ptr->r.record.b.t = rlen - 1 - t;
+ break;
+
+ case mem_stack_f:
+ case mem_stack_v:
+ case rp_when:
+ case pfs_when:
+ case preds_when:
+ case unat_when:
+ case lc_when:
+ case fpsr_when:
+ case priunat_when_gr:
+ case priunat_when_mem:
+ case bsp_when:
+ case bspstore_when:
+ case rnat_when:
+ ptr->r.record.p.t = t;
+ break;
+
+ case spill_reg:
+ case spill_sprel:
+ case spill_psprel:
+ case spill_reg_p:
+ case spill_sprel_p:
+ case spill_psprel_p:
+ ptr->r.record.x.t = t;
+ break;
+
+ case frgr_mem:
+ if (!region)
+ {
+ as_bad ("frgr_mem record before region record!\n");
+ return;
}
- case mem_stack_f:
- case mem_stack_v:
- case rp_when:
- case pfs_when:
- case preds_when:
- case unat_when:
- case lc_when:
- case fpsr_when:
- case priunat_when_gr:
- case priunat_when_mem:
- case bsp_when:
- case bspstore_when:
- case rnat_when:
+ region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
+ region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
+ set_imask (region, ptr->r.record.p.frmask, t, 1);
+ set_imask (region, ptr->r.record.p.grmask, t, 2);
+ break;
+ case fr_mem:
+ if (!region)
{
- /* All the time fields. */
- int x = ptr->slot_number - first_addr;
- ptr->r.record.p.t = (x / 16) * 3 + (ptr->slot_number % 4);
- break;
+ as_bad ("fr_mem record before region record!\n");
+ return;
+ }
+ region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
+ set_imask (region, ptr->r.record.p.rmask, t, 1);
+ break;
+ case gr_mem:
+ if (!region)
+ {
+ as_bad ("gr_mem record before region record!\n");
+ return;
+ }
+ region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
+ set_imask (region, ptr->r.record.p.rmask, t, 2);
+ break;
+ case br_mem:
+ if (!region)
+ {
+ as_bad ("br_mem record before region record!\n");
+ return;
+ }
+ region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
+ set_imask (region, ptr->r.record.p.brmask, t, 3);
+ break;
+
+ case gr_gr:
+ if (!region)
+ {
+ as_bad ("gr_gr record before region record!\n");
+ return;
}
- /* TODO. We also need to combine all the register masks into a single
- record. (Ie, all the save.g save.gf, save.f and save.br's) */
+ set_imask (region, ptr->r.record.p.grmask, t, 2);
+ break;
+ case br_gr:
+ if (!region)
+ {
+ as_bad ("br_gr record before region record!\n");
+ return;
+ }
+ set_imask (region, ptr->r.record.p.brmask, t, 3);
+ break;
+
+ default:
+ break;
}
}
}
/* Clear the padding area and personality. */
memset (mem + 8 + size, 0 , extra + 8);
/* Initialize the header area. */
- md_number_to_chars (mem, ( ((bfd_vma) 1 << 48) /* version */
- | ((bfd_vma) 3 << 32) /* U & E handler flags */
+ md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
+ | (unwind.personality_routine
+ ? ((bfd_vma) 3 << 32) /* U & E handler flags */
+ : 0)
| ((size + extra) / 8)), /* length (dwords) */
8);
return size + extra + 16;
}
+static int
+convert_expr_to_ab_reg (e, ab, regp)
+ expressionS *e;
+ unsigned int *ab;
+ unsigned int *regp;
+{
+ unsigned int reg;
+
+ if (e->X_op != O_register)
+ return 0;
+
+ reg = e->X_add_number;
+ if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
+ {
+ *ab = 0;
+ *regp = reg - REG_GR;
+ }
+ else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
+ || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
+ {
+ *ab = 1;
+ *regp = reg - REG_FR;
+ }
+ else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
+ {
+ *ab = 2;
+ *regp = reg - REG_BR;
+ }
+ else
+ {
+ *ab = 3;
+ switch (reg)
+ {
+ case REG_PR: *regp = 0; break;
+ case REG_PSP: *regp = 1; break;
+ case REG_PRIUNAT: *regp = 2; break;
+ case REG_BR + 0: *regp = 3; break;
+ case REG_AR + AR_BSP: *regp = 4; break;
+ case REG_AR + AR_BSPSTORE: *regp = 5; break;
+ case REG_AR + AR_RNAT: *regp = 6; break;
+ case REG_AR + AR_UNAT: *regp = 7; break;
+ case REG_AR + AR_FPSR: *regp = 8; break;
+ case REG_AR + AR_PFS: *regp = 9; break;
+ case REG_AR + AR_LC: *regp = 10; break;
+
+ default:
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int
+convert_expr_to_xy_reg (e, xy, regp)
+ expressionS *e;
+ unsigned int *xy;
+ unsigned int *regp;
+{
+ unsigned int reg;
+
+ if (e->X_op != O_register)
+ return 0;
+
+ reg = e->X_add_number;
+
+ if (reg >= REG_GR && reg <= REG_GR + 127)
+ {
+ *xy = 0;
+ *regp = reg - REG_GR;
+ }
+ else if (reg >= REG_FR && reg <= REG_FR + 127)
+ {
+ *xy = 1;
+ *regp = reg - REG_FR;
+ }
+ else if (reg >= REG_BR && reg <= REG_BR + 7)
+ {
+ *xy = 2;
+ *regp = reg - REG_BR;
+ }
+ else
+ return -1;
+ return 1;
+}
+
static void
dot_radix (dummy)
int dummy;
if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
{
as_bad ("Radix `%c' unsupported", *input_line_pointer);
- ignore_rest_of_line ();
+ ignore_rest_of_line ();
return;
}
}
add_unwind_entry (ptr)
unw_rec_list *ptr;
{
- if (unwind_tail)
- unwind_tail->next = ptr;
+ if (unwind.tail)
+ unwind.tail->next = ptr;
else
- unwind_list = ptr;
- unwind_tail = ptr;
+ unwind.list = ptr;
+ unwind.tail = ptr;
/* The current entry can in fact be a chain of unwind entries. */
- if (current_unwind_entry == NULL)
- current_unwind_entry = ptr;
+ if (unwind.current_entry == NULL)
+ unwind.current_entry = ptr;
}
-static void
+static void
dot_fframe (dummy)
int dummy;
{
expressionS e;
+
parse_operand (&e);
-
+
if (e.X_op != O_constant)
as_bad ("Operand to .fframe must be a constant");
else
+ add_unwind_entry (output_mem_stack_f (e.X_add_number));
+}
+
+static void
+dot_vframe (dummy)
+ int dummy;
+{
+ expressionS e;
+ unsigned reg;
+
+ parse_operand (&e);
+ reg = e.X_add_number - REG_GR;
+ if (e.X_op == O_register && reg < 128)
+ {
+ add_unwind_entry (output_mem_stack_v ());
+ if (! (unwind.prologue_mask & 2))
+ add_unwind_entry (output_psp_gr (reg));
+ }
+ else
+ as_bad ("First operand to .vframe must be a general register");
+}
+
+static void
+dot_vframesp (dummy)
+ int dummy;
+{
+ expressionS e;
+
+ parse_operand (&e);
+ if (e.X_op == O_constant)
{
- add_unwind_entry (output_mem_stack_f (e.X_add_number));
+ add_unwind_entry (output_mem_stack_v ());
+ add_unwind_entry (output_psp_sprel (e.X_add_number));
}
+ else
+ as_bad ("First operand to .vframesp must be a general register");
}
-static void
-dot_vframe (dummy)
+static void
+dot_vframepsp (dummy)
int dummy;
{
- discard_rest_of_line ();
+ expressionS e;
+
+ parse_operand (&e);
+ if (e.X_op == O_constant)
+ {
+ add_unwind_entry (output_mem_stack_v ());
+ add_unwind_entry (output_psp_sprel (e.X_add_number));
+ }
+ else
+ as_bad ("First operand to .vframepsp must be a general register");
}
-static void
+static void
dot_save (dummy)
int dummy;
{
as_bad ("No second operand to .save");
sep = parse_operand (&e2);
- reg1 = e1.X_add_number - REG_AR;
+ reg1 = e1.X_add_number;
reg2 = e2.X_add_number - REG_GR;
-
+
/* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
- if (e1.X_op == O_register
- && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR))
+ if (e1.X_op == O_register)
{
- if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
+ if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
{
switch (reg1)
{
- case 17: /* ar.bsp */
- add_unwind_entry (output_bsp_when ());
- add_unwind_entry (output_bsp_gr (reg2));
- break;
- case 18: /* ar.bspstore */
- add_unwind_entry (output_bspstore_when ());
- add_unwind_entry (output_bspstore_gr (reg2));
- break;
- case 19: /* ar.rnat */
- add_unwind_entry (output_rnat_when ());
- add_unwind_entry (output_rnat_gr (reg2));
- break;
- case 36: /* ar.unat */
- add_unwind_entry (output_unat_when ());
- add_unwind_entry (output_unat_gr (reg2));
- break;
- case 40: /* ar.fpsr */
- add_unwind_entry (output_fpsr_when ());
- add_unwind_entry (output_fpsr_gr (reg2));
- break;
- case 64: /* ar.pfs */
- add_unwind_entry (output_pfs_when ());
- add_unwind_entry (output_pfs_gr (reg2));
- break;
- case 65: /* ar.lc */
- add_unwind_entry (output_lc_when ());
- add_unwind_entry (output_lc_gr (reg2));
- break;
- case REG_BR - REG_AR: /* rp */
- add_unwind_entry (output_rp_when ());
+ case REG_AR + AR_BSP:
+ add_unwind_entry (output_bsp_when ());
+ add_unwind_entry (output_bsp_gr (reg2));
+ break;
+ case REG_AR + AR_BSPSTORE:
+ add_unwind_entry (output_bspstore_when ());
+ add_unwind_entry (output_bspstore_gr (reg2));
+ break;
+ case REG_AR + AR_RNAT:
+ add_unwind_entry (output_rnat_when ());
+ add_unwind_entry (output_rnat_gr (reg2));
+ break;
+ case REG_AR + AR_UNAT:
+ add_unwind_entry (output_unat_when ());
+ add_unwind_entry (output_unat_gr (reg2));
+ break;
+ case REG_AR + AR_FPSR:
+ add_unwind_entry (output_fpsr_when ());
+ add_unwind_entry (output_fpsr_gr (reg2));
+ break;
+ case REG_AR + AR_PFS:
+ add_unwind_entry (output_pfs_when ());
+ if (! (unwind.prologue_mask & 4))
+ add_unwind_entry (output_pfs_gr (reg2));
+ break;
+ case REG_AR + AR_LC:
+ add_unwind_entry (output_lc_when ());
+ add_unwind_entry (output_lc_gr (reg2));
+ break;
+ case REG_BR:
+ add_unwind_entry (output_rp_when ());
+ if (! (unwind.prologue_mask & 8))
add_unwind_entry (output_rp_gr (reg2));
- break;
- default:
- as_bad ("first operand is unknown application register");
+ break;
+ case REG_PR:
+ add_unwind_entry (output_preds_when ());
+ if (! (unwind.prologue_mask & 1))
+ add_unwind_entry (output_preds_gr (reg2));
+ break;
+ case REG_PRIUNAT:
+ add_unwind_entry (output_priunat_when_gr ());
+ add_unwind_entry (output_priunat_gr (reg2));
+ break;
+ default:
+ as_bad ("First operand not a valid register");
}
}
else
as_bad (" Second operand not a valid register");
}
else
- as_bad ("First operand not a valid register");
+ as_bad ("First operand not a register");
}
-static void
+static void
dot_restore (dummy)
int dummy;
{
- discard_rest_of_line ();
+ expressionS e1, e2;
+ unsigned long ecount = 0;
+ int sep;
+
+ sep = parse_operand (&e1);
+ if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
+ {
+ as_bad ("First operand to .restore must be stack pointer (sp)");
+ return;
+ }
+
+ if (sep == ',')
+ {
+ parse_operand (&e2);
+ if (e1.X_op != O_constant)
+ {
+ as_bad ("Second operand to .restore must be constant");
+ return;
+ }
+ ecount = e1.X_op;
+ }
+ add_unwind_entry (output_epilogue (ecount));
+}
+
+static void
+dot_restorereg (dummy)
+ int dummy;
+{
+ unsigned int ab, reg;
+ expressionS e;
+
+ parse_operand (&e);
+
+ if (!convert_expr_to_ab_reg (&e, &ab, ®))
+ {
+ as_bad ("First operand to .restorereg must be a preserved register");
+ return;
+ }
+ add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
+}
+
+static void
+dot_restorereg_p (dummy)
+ int dummy;
+{
+ unsigned int qp, ab, reg;
+ expressionS e1, e2;
+ int sep;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("No second operand to .restorereg.p");
+ return;
+ }
+
+ parse_operand (&e2);
+
+ qp = e1.X_add_number - REG_P;
+ if (e1.X_op != O_register || qp > 63)
+ {
+ as_bad ("First operand to .restorereg.p must be a predicate");
+ return;
+ }
+
+ if (!convert_expr_to_ab_reg (&e2, &ab, ®))
+ {
+ as_bad ("Second operand to .restorereg.p must be a preserved register");
+ return;
+ }
+ add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
}
static int
{
int size;
unsigned char *unw_rec;
- int x;
+
+ /* Force out pending instructions, to make sure all unwind records have
+ a valid slot_number field. */
+ ia64_flush_insns ();
/* Generate the unwind record. */
- size = output_unw_records (unwind_list, &unw_rec);
- if (size % 4 != 0)
- as_bad ("Unwind record is ont a multiple of 4 bytes.");
+ size = output_unw_records (unwind.list, (void **) &unw_rec);
+ if (size % 8 != 0)
+ as_bad ("Unwind record is not a multiple of 8 bytes.");
/* If there are unwind records, switch sections, and output the info. */
if (size != 0)
{
- int x;
unsigned char *where;
- unsigned char *personality;
expressionS exp;
- char *save;
set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
/* Set expression which points to start of unwind descriptor area. */
- unwind_info = expr_build_dot ();
+ unwind.info = expr_build_dot ();
- where = (unsigned char *)frag_more (size);
+ where = (unsigned char *) frag_more (size);
/* Issue a label for this address, and keep track of it to put it
in the unwind section. */
data is already in the correct byte order. */
memcpy (where, unw_rec, size);
/* Add the personality address to the image. */
- if (personality_routine != 0)
- {
+ if (unwind.personality_routine != 0)
+ {
exp.X_op = O_symbol;
- exp.X_add_symbol = personality_routine;
+ exp.X_add_symbol = unwind.personality_routine;
exp.X_add_number = 0;
fix_new_exp (frag_now, frag_now_fix () - 8, 8,
&exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
- personality_routine = 0;
- }
+ unwind.personality_routine = 0;
+ }
obj_elf_previous (0);
}
- free_list_records (unwind_list);
- unwind_list = unwind_tail = current_unwind_entry = NULL;
+ free_list_records (unwind.list);
+ unwind.list = unwind.tail = unwind.current_entry = NULL;
return size;
}
-static void
-dot_handlerdata (dummy)
+static void
+dot_handlerdata (dummy)
int dummy;
{
generate_unwind_image ();
+ demand_empty_rest_of_line ();
}
-static void
+static void
dot_unwentry (dummy)
int dummy;
{
- discard_rest_of_line ();
+ demand_empty_rest_of_line ();
}
-static void
+static void
dot_altrp (dummy)
int dummy;
{
- discard_rest_of_line ();
+ expressionS e;
+ unsigned reg;
+
+ parse_operand (&e);
+ reg = e.X_add_number - REG_BR;
+ if (e.X_op == O_register && reg < 8)
+ add_unwind_entry (output_rp_br (reg));
+ else
+ as_bad ("First operand not a valid branch register");
}
-static void
-dot_savesp (dummy)
- int dummy;
+static void
+dot_savemem (psprel)
+ int psprel;
{
expressionS e1, e2;
int sep;
sep = parse_operand (&e1);
if (sep != ',')
- as_bad ("No second operand to .savesp");
+ as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
sep = parse_operand (&e2);
- reg1 = e1.X_add_number - REG_AR;
+ reg1 = e1.X_add_number;
val = e2.X_add_number;
-
+
/* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
- if (e1.X_op == O_register
- && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR || reg1 == REG_PR - REG_AR))
+ if (e1.X_op == O_register)
{
if (e2.X_op == O_constant)
{
switch (reg1)
{
- case 17: /* ar.bsp */
- add_unwind_entry (output_bsp_when ());
- add_unwind_entry (output_bsp_sprel (val));
- break;
- case 18: /* ar.bspstore */
- add_unwind_entry (output_bspstore_when ());
- add_unwind_entry (output_bspstore_sprel (val));
- break;
- case 19: /* ar.rnat */
- add_unwind_entry (output_rnat_when ());
- add_unwind_entry (output_rnat_sprel (val));
- break;
- case 36: /* ar.unat */
- add_unwind_entry (output_unat_when ());
- add_unwind_entry (output_unat_sprel (val));
- break;
- case 40: /* ar.fpsr */
- add_unwind_entry (output_fpsr_when ());
- add_unwind_entry (output_fpsr_sprel (val));
- break;
- case 64: /* ar.pfs */
- add_unwind_entry (output_pfs_when ());
- add_unwind_entry (output_pfs_sprel (val));
- break;
- case 65: /* ar.lc */
- add_unwind_entry (output_lc_when ());
- add_unwind_entry (output_lc_sprel (val));
- break;
- case REG_BR - REG_AR: /* rp */
- add_unwind_entry (output_rp_when ());
- add_unwind_entry (output_rp_sprel (val));
- break;
- case REG_PR - REG_AR: /* Predicate registers. */
- add_unwind_entry (output_preds_when ());
- add_unwind_entry (output_preds_sprel (val));
- break;
- default:
- as_bad ("first operand is unknown application register");
- }
- }
- else
- as_bad (" Second operand not a valid constant");
- }
- else
- as_bad ("First operand not a valid register");
-}
-
-static void
-dot_savepsp (dummy)
- int dummy;
-{
- discard_rest_of_line ();
+ case REG_AR + AR_BSP:
+ add_unwind_entry (output_bsp_when ());
+ add_unwind_entry ((psprel
+ ? output_bsp_psprel
+ : output_bsp_sprel) (val));
+ break;
+ case REG_AR + AR_BSPSTORE:
+ add_unwind_entry (output_bspstore_when ());
+ add_unwind_entry ((psprel
+ ? output_bspstore_psprel
+ : output_bspstore_sprel) (val));
+ break;
+ case REG_AR + AR_RNAT:
+ add_unwind_entry (output_rnat_when ());
+ add_unwind_entry ((psprel
+ ? output_rnat_psprel
+ : output_rnat_sprel) (val));
+ break;
+ case REG_AR + AR_UNAT:
+ add_unwind_entry (output_unat_when ());
+ add_unwind_entry ((psprel
+ ? output_unat_psprel
+ : output_unat_sprel) (val));
+ break;
+ case REG_AR + AR_FPSR:
+ add_unwind_entry (output_fpsr_when ());
+ add_unwind_entry ((psprel
+ ? output_fpsr_psprel
+ : output_fpsr_sprel) (val));
+ break;
+ case REG_AR + AR_PFS:
+ add_unwind_entry (output_pfs_when ());
+ add_unwind_entry ((psprel
+ ? output_pfs_psprel
+ : output_pfs_sprel) (val));
+ break;
+ case REG_AR + AR_LC:
+ add_unwind_entry (output_lc_when ());
+ add_unwind_entry ((psprel
+ ? output_lc_psprel
+ : output_lc_sprel) (val));
+ break;
+ case REG_BR:
+ add_unwind_entry (output_rp_when ());
+ add_unwind_entry ((psprel
+ ? output_rp_psprel
+ : output_rp_sprel) (val));
+ break;
+ case REG_PR:
+ add_unwind_entry (output_preds_when ());
+ add_unwind_entry ((psprel
+ ? output_preds_psprel
+ : output_preds_sprel) (val));
+ break;
+ case REG_PRIUNAT:
+ add_unwind_entry (output_priunat_when_mem ());
+ add_unwind_entry ((psprel
+ ? output_priunat_psprel
+ : output_priunat_sprel) (val));
+ break;
+ default:
+ as_bad ("First operand not a valid register");
+ }
+ }
+ else
+ as_bad (" Second operand not a valid constant");
+ }
+ else
+ as_bad ("First operand not a register");
}
-static void
+static void
dot_saveg (dummy)
int dummy;
{
sep = parse_operand (&e1);
if (sep == ',')
parse_operand (&e2);
-
+
if (e1.X_op != O_constant)
as_bad ("First operand to .save.g must be a constant.");
else
if (sep != ',')
add_unwind_entry (output_gr_mem (grmask));
else
- {
+ {
int reg = e2.X_add_number - REG_GR;
- if (e2.X_op == O_register && reg >=0 && reg < 128)
+ if (e2.X_op == O_register && reg >= 0 && reg < 128)
add_unwind_entry (output_gr_gr (grmask, reg));
else
as_bad ("Second operand is an invalid register.");
}
}
-static void
+static void
dot_savef (dummy)
int dummy;
{
- expressionS e1, e2;
+ expressionS e1;
int sep;
sep = parse_operand (&e1);
-
+
if (e1.X_op != O_constant)
as_bad ("Operand to .save.f must be a constant.");
else
- {
- int frmask = e1.X_add_number;
- add_unwind_entry (output_fr_mem (e1.X_add_number));
- }
+ add_unwind_entry (output_fr_mem (e1.X_add_number));
}
-static void
+static void
dot_saveb (dummy)
int dummy;
{
- expressionS e1;
- int sep;
+ expressionS e1, e2;
+ unsigned int reg;
+ unsigned char sep;
+ int brmask;
+
sep = parse_operand (&e1);
-
if (e1.X_op != O_constant)
- as_bad ("Operand to .save.b must be a constant.");
- else
{
- int brmask = e1.X_add_number;
- add_unwind_entry (output_br_mem (brmask));
+ as_bad ("First operand to .save.b must be a constant.");
+ return;
+ }
+ brmask = e1.X_add_number;
+
+ if (sep == ',')
+ {
+ sep = parse_operand (&e2);
+ reg = e2.X_add_number - REG_GR;
+ if (e2.X_op != O_register || reg > 127)
+ {
+ as_bad ("Second operand to .save.b must be a general register.");
+ return;
+ }
+ add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
}
+ else
+ add_unwind_entry (output_br_mem (brmask));
+
+ if (!is_end_of_line[sep] && !is_it_end_of_statement ())
+ ignore_rest_of_line ();
}
-static void
+static void
dot_savegf (dummy)
int dummy;
{
sep = parse_operand (&e1);
if (sep == ',')
parse_operand (&e2);
-
+
if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
as_bad ("Both operands of .save.gf must be constants.");
else
}
}
-static void
+static void
dot_spill (dummy)
int dummy;
{
expressionS e;
- parse_operand (&e);
-
+ unsigned char sep;
+
+ sep = parse_operand (&e);
+ if (!is_end_of_line[sep] && !is_it_end_of_statement ())
+ ignore_rest_of_line ();
+
if (e.X_op != O_constant)
as_bad ("Operand to .spill must be a constant");
else
+ add_unwind_entry (output_spill_base (e.X_add_number));
+}
+
+static void
+dot_spillreg (dummy)
+ int dummy;
+{
+ int sep, ab, xy, reg, treg;
+ expressionS e1, e2;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("No second operand to .spillreg");
+ return;
+ }
+
+ parse_operand (&e2);
+
+ if (!convert_expr_to_ab_reg (&e1, &ab, ®))
+ {
+ as_bad ("First operand to .spillreg must be a preserved register");
+ return;
+ }
+
+ if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
+ {
+ as_bad ("Second operand to .spillreg must be a register");
+ return;
+ }
+
+ add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
+}
+
+static void
+dot_spillmem (psprel)
+ int psprel;
+{
+ expressionS e1, e2;
+ int sep, ab, reg;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("Second operand missing");
+ return;
+ }
+
+ parse_operand (&e2);
+
+ if (!convert_expr_to_ab_reg (&e1, &ab, ®))
+ {
+ as_bad ("First operand to .spill%s must be a preserved register",
+ psprel ? "psp" : "sp");
+ return;
+ }
+
+ if (e2.X_op != O_constant)
+ {
+ as_bad ("Second operand to .spill%s must be a constant",
+ psprel ? "psp" : "sp");
+ return;
+ }
+
+ if (psprel)
+ add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
+ else
+ add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
+}
+
+static void
+dot_spillreg_p (dummy)
+ int dummy;
+{
+ int sep, ab, xy, reg, treg;
+ expressionS e1, e2, e3;
+ unsigned int qp;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("No second and third operand to .spillreg.p");
+ return;
+ }
+
+ sep = parse_operand (&e2);
+ if (sep != ',')
+ {
+ as_bad ("No third operand to .spillreg.p");
+ return;
+ }
+
+ parse_operand (&e3);
+
+ qp = e1.X_add_number - REG_P;
+
+ if (e1.X_op != O_register || qp > 63)
+ {
+ as_bad ("First operand to .spillreg.p must be a predicate");
+ return;
+ }
+
+ if (!convert_expr_to_ab_reg (&e2, &ab, ®))
+ {
+ as_bad ("Second operand to .spillreg.p must be a preserved register");
+ return;
+ }
+
+ if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
+ {
+ as_bad ("Third operand to .spillreg.p must be a register");
+ return;
+ }
+
+ add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
+}
+
+static void
+dot_spillmem_p (psprel)
+ int psprel;
+{
+ expressionS e1, e2, e3;
+ int sep, ab, reg;
+ unsigned int qp;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("Second operand missing");
+ return;
+ }
+
+ parse_operand (&e2);
+ if (sep != ',')
+ {
+ as_bad ("Second operand missing");
+ return;
+ }
+
+ parse_operand (&e3);
+
+ qp = e1.X_add_number - REG_P;
+ if (e1.X_op != O_register || qp > 63)
+ {
+ as_bad ("First operand to .spill%s_p must be a predicate",
+ psprel ? "psp" : "sp");
+ return;
+ }
+
+ if (!convert_expr_to_ab_reg (&e2, &ab, ®))
+ {
+ as_bad ("Second operand to .spill%s_p must be a preserved register",
+ psprel ? "psp" : "sp");
+ return;
+ }
+
+ if (e3.X_op != O_constant)
+ {
+ as_bad ("Third operand to .spill%s_p must be a constant",
+ psprel ? "psp" : "sp");
+ return;
+ }
+
+ if (psprel)
+ add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
+ else
+ add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
+}
+
+static void
+dot_label_state (dummy)
+ int dummy;
+{
+ expressionS e;
+
+ parse_operand (&e);
+ if (e.X_op != O_constant)
+ {
+ as_bad ("Operand to .label_state must be a constant");
+ return;
+ }
+ add_unwind_entry (output_label_state (e.X_add_number));
+}
+
+static void
+dot_copy_state (dummy)
+ int dummy;
+{
+ expressionS e;
+
+ parse_operand (&e);
+ if (e.X_op != O_constant)
{
- add_unwind_entry (output_spill_base (e.X_add_number));
+ as_bad ("Operand to .copy_state must be a constant");
+ return;
}
+ add_unwind_entry (output_copy_state (e.X_add_number));
}
-static void
+static void
dot_unwabi (dummy)
int dummy;
{
- discard_rest_of_line ();
+ expressionS e1, e2;
+ unsigned char sep;
+
+ sep = parse_operand (&e1);
+ if (sep != ',')
+ {
+ as_bad ("Second operand to .unwabi missing");
+ return;
+ }
+ sep = parse_operand (&e2);
+ if (!is_end_of_line[sep] && !is_it_end_of_statement ())
+ ignore_rest_of_line ();
+
+ if (e1.X_op != O_constant)
+ {
+ as_bad ("First operand to .unwabi must be a constant");
+ return;
+ }
+
+ if (e2.X_op != O_constant)
+ {
+ as_bad ("Second operand to .unwabi must be a constant");
+ return;
+ }
+
+ add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
}
-static void
+static void
dot_personality (dummy)
int dummy;
{
name = input_line_pointer;
c = get_symbol_end ();
p = input_line_pointer;
- personality_routine = symbol_find_or_make (name);
+ unwind.personality_routine = symbol_find_or_make (name);
*p = c;
SKIP_WHITESPACE ();
demand_empty_rest_of_line ();
char *name, *p, c;
symbolS *sym;
- proc_start = expr_build_dot ();
- /* Parse names of main and alternate entry points and mark them s
- function symbols: */
+ unwind.proc_start = expr_build_dot ();
+ /* Parse names of main and alternate entry points and mark them as
+ function symbols: */
while (1)
{
SKIP_WHITESPACE ();
c = get_symbol_end ();
p = input_line_pointer;
sym = symbol_find_or_make (name);
- if (proc_start == 0)
- {
- proc_start = sym;
+ if (unwind.proc_start == 0)
+ {
+ unwind.proc_start = sym;
}
symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
*p = c;
demand_empty_rest_of_line ();
ia64_do_align (16);
- unwind_list = unwind_tail = current_unwind_entry = NULL;
- personality_routine = 0;
+ unwind.list = unwind.tail = unwind.current_entry = NULL;
+ unwind.personality_routine = 0;
}
static void
dot_body (dummy)
int dummy;
{
- unwind_prologue = 0;
+ unwind.prologue = 0;
+ unwind.prologue_mask = 0;
+
add_unwind_entry (output_body ());
+ demand_empty_rest_of_line ();
}
static void
dot_prologue (dummy)
int dummy;
{
- unwind_prologue = 1;
- SKIP_WHITESPACE ();
- if (! is_end_of_line[(unsigned char) *input_line_pointer])
+ unsigned char sep;
+ int mask = 0, grsave;
+
+ if (!is_it_end_of_statement ())
{
expressionS e1, e2;
- char sep;
sep = parse_operand (&e1);
if (sep != ',')
as_bad ("No second operand to .prologue");
sep = parse_operand (&e2);
+ if (!is_end_of_line[sep] && !is_it_end_of_statement ())
+ ignore_rest_of_line ();
if (e1.X_op == O_constant)
- {
+ {
+ mask = e1.X_add_number;
+
if (e2.X_op == O_constant)
- {
- int mask = e1.X_add_number;
- int reg = e2.X_add_number;
- add_unwind_entry (output_prologue_gr (mask, reg));
- }
+ grsave = e2.X_add_number;
+ else if (e2.X_op == O_register
+ && (grsave = e2.X_add_number - REG_GR) < 128)
+ ;
else
- as_bad ("Second operand not a constant");
+ as_bad ("Second operand not a constant or general register");
+
+ add_unwind_entry (output_prologue_gr (mask, grsave));
}
else
as_bad ("First operand not a constant");
}
else
add_unwind_entry (output_prologue ());
+
+ unwind.prologue = 1;
+ unwind.prologue_mask = mask;
}
static void
{
expressionS e;
unsigned char *ptr;
- int size;
+ int bytes_per_address;
long where;
segT saved_seg;
subsegT saved_subseg;
demand_empty_rest_of_line ();
insn_group_break (1, 0, 0);
- ia64_flush_insns ();
/* If there was a .handlerdata, we haven't generated an image yet. */
- if (unwind_info == 0)
+ if (unwind.info == 0)
{
generate_unwind_image ();
}
subseg_set (md.last_text_seg, 0);
- proc_end = expr_build_dot ();
+ unwind.proc_end = expr_build_dot ();
set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
ptr = frag_more (24);
where = frag_now_fix () - 24;
+ bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
/* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
e.X_op = O_pseudo_fixup;
e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
e.X_add_number = 0;
- e.X_add_symbol = proc_start;
- ia64_cons_fix_new (frag_now, where, 8, &e);
+ e.X_add_symbol = unwind.proc_start;
+ ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
e.X_op = O_pseudo_fixup;
e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
e.X_add_number = 0;
- e.X_add_symbol = proc_end;
- ia64_cons_fix_new (frag_now, where + 8, 8, &e);
+ e.X_add_symbol = unwind.proc_end;
+ ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e);
- if (unwind_info != 0)
+ if (unwind.info != 0)
{
e.X_op = O_pseudo_fixup;
e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
e.X_add_number = 0;
- e.X_add_symbol = unwind_info;
- ia64_cons_fix_new (frag_now, where + 16, 8, &e);
+ e.X_add_symbol = unwind.info;
+ ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e);
}
else
- md_number_to_chars (ptr + 16, 0, 8);
+ md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address);
subseg_set (saved_seg, saved_subseg);
- proc_start = proc_end = unwind_info = 0;
+ unwind.proc_start = unwind.proc_end = unwind.info = 0;
}
static void
default: break;
}
- /* first, remove existing names from hash table: */
+ /* First, remove existing names from hash table. */
for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
{
hash_delete (md.dynreg_hash, dr->name);
demand_empty_rest_of_line ();
}
-static char*
+static char *
parse_section_name ()
{
char *name;
}
/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
+
static void
stmt_float_cons (kind)
int kind;
}
/* .reg.val <regname>,value */
+
static void
dot_reg_val (dummy)
- int dummy;
+ int dummy;
{
expressionS reg;
as_bad (_("Comma expected"));
ignore_rest_of_line ();
}
- else
+ else
{
valueT value = get_absolute_expression ();
int regno = reg.X_add_number;
- if (regno < REG_GR || regno > REG_GR+128)
- as_warn (_("Register value annotation ignored"));
+ if (regno < REG_GR || regno > REG_GR + 128)
+ as_warn (_("Register value annotation ignored"));
else
- {
- gr_values[regno-REG_GR].known = 1;
- gr_values[regno-REG_GR].value = value;
- gr_values[regno-REG_GR].path = md.path;
- }
+ {
+ gr_values[regno - REG_GR].known = 1;
+ gr_values[regno - REG_GR].value = value;
+ gr_values[regno - REG_GR].path = md.path;
+ }
}
demand_empty_rest_of_line ();
}
-/* select dv checking mode
+/* select dv checking mode
.auto
.explicit
.default
- A stop is inserted when changing modes
+ A stop is inserted when changing modes
*/
+
static void
dot_dv_mode (type)
- int type;
+ int type;
{
if (md.manual_bundling)
as_warn (_("Directive invalid within a bundle"));
case 'A':
case 'a':
if (md.explicit_mode)
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
md.explicit_mode = 0;
break;
case 'E':
case 'e':
if (!md.explicit_mode)
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
md.explicit_mode = 1;
break;
default:
case 'd':
if (md.explicit_mode != md.default_explicit_mode)
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
md.explicit_mode = md.default_explicit_mode;
md.mode_explicitly_set = 0;
break;
static void
print_prmask (mask)
- valueT mask;
+ valueT mask;
{
int regno;
char *comma = "";
- for (regno = 0;regno < 64;regno++)
+ for (regno = 0; regno < 64; regno++)
{
- if (mask & ((valueT)1<<regno))
- {
- fprintf (stderr, "%s p%d", comma, regno);
- comma = ",";
- }
+ if (mask & ((valueT) 1 << regno))
+ {
+ fprintf (stderr, "%s p%d", comma, regno);
+ comma = ",";
+ }
}
}
.pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
.pred.safe_across_calls p1 [, p2 [,...]]
*/
+
static void
dot_pred_rel (type)
- int type;
+ int type;
{
valueT mask = 0;
int count = 0;
if (type == 0)
{
if (*input_line_pointer != '"')
- {
- as_bad (_("Missing predicate relation type"));
- ignore_rest_of_line ();
- return;
- }
- else
- {
- int len;
- char *form = demand_copy_C_string (&len);
- if (strcmp (form, "mutex") == 0)
- type = 'm';
- else if (strcmp (form, "clear") == 0)
- type = 'c';
- else if (strcmp (form, "imply") == 0)
- type = 'i';
- else
- {
- as_bad (_("Unrecognized predicate relation type"));
- ignore_rest_of_line ();
- return;
- }
- }
+ {
+ as_bad (_("Missing predicate relation type"));
+ ignore_rest_of_line ();
+ return;
+ }
+ else
+ {
+ int len;
+ char *form = demand_copy_C_string (&len);
+ if (strcmp (form, "mutex") == 0)
+ type = 'm';
+ else if (strcmp (form, "clear") == 0)
+ type = 'c';
+ else if (strcmp (form, "imply") == 0)
+ type = 'i';
+ else
+ {
+ as_bad (_("Unrecognized predicate relation type"));
+ ignore_rest_of_line ();
+ return;
+ }
+ }
if (*input_line_pointer == ',')
- ++input_line_pointer;
+ ++input_line_pointer;
SKIP_WHITESPACE ();
}
{
valueT bit = 1;
int regno;
-
+
if (toupper (*input_line_pointer) != 'P'
- || (regno = atoi (++input_line_pointer)) < 0
- || regno > 63)
- {
- as_bad (_("Predicate register expected"));
- ignore_rest_of_line ();
- return;
- }
+ || (regno = atoi (++input_line_pointer)) < 0
+ || regno > 63)
+ {
+ as_bad (_("Predicate register expected"));
+ ignore_rest_of_line ();
+ return;
+ }
while (isdigit (*input_line_pointer))
- ++input_line_pointer;
+ ++input_line_pointer;
if (p1 == -1)
- p1 = regno;
+ p1 = regno;
else if (p2 == -1)
- p2 = regno;
+ p2 = regno;
bit <<= regno;
if (mask & bit)
- as_warn (_("Duplicate predicate register ignored"));
- mask |= bit; count++;
- /* see if it's a range */
+ as_warn (_("Duplicate predicate register ignored"));
+ mask |= bit;
+ count++;
+ /* See if it's a range. */
if (*input_line_pointer == '-')
- {
- valueT stop = 1;
- ++input_line_pointer;
-
- if (toupper (*input_line_pointer) != 'P'
- || (regno = atoi (++input_line_pointer)) < 0
- || regno > 63)
- {
- as_bad (_("Predicate register expected"));
- ignore_rest_of_line ();
- return;
- }
- while (isdigit (*input_line_pointer))
- ++input_line_pointer;
- stop <<= regno;
- if (bit >= stop)
- {
- as_bad (_("Bad register range"));
- ignore_rest_of_line ();
- return;
- }
- while (bit < stop)
- {
- bit <<= 1;
- mask |= bit; count++;
- }
- SKIP_WHITESPACE ();
- }
- if (*input_line_pointer != ',')
- break;
- ++input_line_pointer;
- SKIP_WHITESPACE ();
- }
+ {
+ valueT stop = 1;
+ ++input_line_pointer;
+
+ if (toupper (*input_line_pointer) != 'P'
+ || (regno = atoi (++input_line_pointer)) < 0
+ || regno > 63)
+ {
+ as_bad (_("Predicate register expected"));
+ ignore_rest_of_line ();
+ return;
+ }
+ while (isdigit (*input_line_pointer))
+ ++input_line_pointer;
+ stop <<= regno;
+ if (bit >= stop)
+ {
+ as_bad (_("Bad register range"));
+ ignore_rest_of_line ();
+ return;
+ }
+ while (bit < stop)
+ {
+ bit <<= 1;
+ mask |= bit;
+ count++;
+ }
+ SKIP_WHITESPACE ();
+ }
+ if (*input_line_pointer != ',')
+ break;
+ ++input_line_pointer;
+ SKIP_WHITESPACE ();
+ }
switch (type)
{
case 'c':
if (count == 0)
- mask = ~(valueT)0;
+ mask = ~(valueT) 0;
clear_qp_mutex (mask);
- clear_qp_implies (mask, (valueT)0);
+ clear_qp_implies (mask, (valueT) 0);
break;
case 'i':
if (count != 2 || p1 == -1 || p2 == -1)
- as_bad (_("Predicate source and target required"));
+ as_bad (_("Predicate source and target required"));
else if (p1 == 0 || p2 == 0)
- as_bad (_("Use of p0 is not valid in this context"));
+ as_bad (_("Use of p0 is not valid in this context"));
else
- add_qp_imply (p1, p2);
+ add_qp_imply (p1, p2);
break;
case 'm':
if (count < 2)
- {
- as_bad (_("At least two PR arguments expected"));
- break;
- }
+ {
+ as_bad (_("At least two PR arguments expected"));
+ break;
+ }
else if (mask & 1)
- {
- as_bad (_("Use of p0 is not valid in this context"));
- break;
- }
+ {
+ as_bad (_("Use of p0 is not valid in this context"));
+ break;
+ }
add_qp_mutex (mask);
break;
case 's':
/* note that we don't override any existing relations */
if (count == 0)
- {
- as_bad (_("At least one PR argument expected"));
- break;
- }
+ {
+ as_bad (_("At least one PR argument expected"));
+ break;
+ }
if (md.debug_dv)
- {
- fprintf (stderr, "Safe across calls: ");
- print_prmask (mask);
- fprintf (stderr, "\n");
- }
+ {
+ fprintf (stderr, "Safe across calls: ");
+ print_prmask (mask);
+ fprintf (stderr, "\n");
+ }
qp_safe_across_calls = mask;
break;
}
/* .entry label [, label [, ...]]
Hint to DV code that the given labels are to be considered entry points.
- Otherwise, only global labels are considered entry points.
- */
+ Otherwise, only global labels are considered entry points. */
+
static void
dot_entry (dummy)
- int dummy;
+ int dummy;
{
const char *err;
char *name;
err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
if (err)
- as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
- name, err);
+ as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
+ name, err);
*input_line_pointer = c;
SKIP_WHITESPACE ();
demand_empty_rest_of_line ();
}
-/* .mem.offset offset, base
- "base" is used to distinguish between offsets from a different base.
- */
+/* .mem.offset offset, base
+ "base" is used to distinguish between offsets from a different base. */
+
static void
dot_mem_offset (dummy)
int dummy;
demand_empty_rest_of_line ();
}
-/* ia64-specific pseudo-ops: */
+/* ia64-specific pseudo-ops: */
const pseudo_typeS md_pseudo_table[] =
{
{ "radix", dot_radix, 0 },
{ "fframe", dot_fframe },
{ "vframe", dot_vframe },
+ { "vframesp", dot_vframesp },
+ { "vframepsp", dot_vframepsp },
{ "save", dot_save },
{ "restore", dot_restore },
+ { "restorereg", dot_restorereg },
+ { "restorereg.p", dot_restorereg_p },
{ "handlerdata", dot_handlerdata },
{ "unwentry", dot_unwentry },
- { "alprp", dot_altrp },
- { "savesp", dot_savesp },
- { "savepsp", dot_savepsp },
+ { "altrp", dot_altrp },
+ { "savesp", dot_savemem, 0 },
+ { "savepsp", dot_savemem, 1 },
{ "save.g", dot_saveg },
{ "save.f", dot_savef },
{ "save.b", dot_saveb },
{ "save.gf", dot_savegf },
{ "spill", dot_spill },
+ { "spillreg", dot_spillreg },
+ { "spillsp", dot_spillmem, 0 },
+ { "spillpsp", dot_spillmem, 1 },
+ { "spillreg.p", dot_spillreg_p },
+ { "spillsp.p", dot_spillmem_p, 0 },
+ { "spillpsp.p", dot_spillmem_p, 1 },
+ { "label_state", dot_label_state },
+ { "copy_state", dot_copy_state },
{ "unwabi", dot_unwabi },
{ "personality", dot_personality },
#if 0
{ "xstring", dot_xstringer, 0 },
{ "xstringz", dot_xstringer, 1 },
- /* unaligned versions: */
+ /* unaligned versions: */
{ "xdata2.ua", dot_xdata_ua, 2 },
{ "xdata4.ua", dot_xdata_ua, 4 },
{ "xdata8.ua", dot_xdata_ua, 8 },
{ "string", stringer, 0 },
{ "stringz", stringer, 1 },
- /* unaligned versions: */
+ /* unaligned versions: */
{ "data2.ua", stmt_cons_ua, 2 },
{ "data4.ua", stmt_cons_ua, 4 },
{ "data8.ua", stmt_cons_ua, 8 },
/* Declare a register by creating a symbol for it and entering it in
the symbol table. */
-static symbolS*
+
+static symbolS *
declare_register (name, regnum)
const char *name;
int regnum;
switch (opnd)
{
- /* constants: */
+ /* constants: */
case IA64_OPND_AR_CCV:
if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
return 1;
break;
- /* register operands: */
+ /* register operands: */
case IA64_OPND_AR3:
if (e->X_op == O_register && e->X_add_number >= REG_AR
return 1;
break;
- /* indirect operands: */
+ /* indirect operands: */
case IA64_OPND_CPUID_R3:
case IA64_OPND_DBR_R3:
case IA64_OPND_DTR_R3:
return 1;
break;
- /* immediate operands: */
+ /* immediate operands: */
case IA64_OPND_CNT2a:
case IA64_OPND_LEN4:
case IA64_OPND_LEN6:
case IA64_OPND_IMMU62:
if (e->X_op == O_constant)
- {
+ {
if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
- return 1;
- }
- else
- {
- /* FIXME -- need 62-bit relocation type */
- as_bad (_("62-bit relocation not yet implemented"));
- }
+ return 1;
+ }
+ else
+ {
+ /* FIXME -- need 62-bit relocation type */
+ as_bad (_("62-bit relocation not yet implemented"));
+ }
break;
case IA64_OPND_IMMU64:
bits = operand_width (idesc->operands[index]);
if (e->X_op == O_constant
&& (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
- {
- int lobits = e->X_add_number & 0x3;
- if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
- e->X_add_number |= (bfd_vma)0x3;
- return 1;
- }
+ {
+ int lobits = e->X_add_number & 0x3;
+ if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
+ e->X_add_number |= (bfd_vma) 0x3;
+ return 1;
+ }
break;
case IA64_OPND_IMM44:
/* least 16 bits must be zero */
if ((e->X_add_number & 0xffff) != 0)
- as_warn (_("lower 16 bits of mask ignored"));
+ as_warn (_("lower 16 bits of mask ignored"));
if (e->X_op == O_constant
&& ((e->X_add_number >= 0
&& e->X_add_number < ((bfd_vma) 1 << 44))
|| (e->X_add_number < 0
&& -e->X_add_number <= ((bfd_vma) 1 << 44))))
- {
- /* sign-extend */
- if (e->X_add_number >= 0
- && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
- {
- e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
- }
- return 1;
- }
+ {
+ /* sign-extend */
+ if (e->X_add_number >= 0
+ && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
+ {
+ e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
+ }
+ return 1;
+ }
break;
case IA64_OPND_IMM17:
&& e->X_add_number < ((bfd_vma) 1 << 17))
|| (e->X_add_number < 0
&& -e->X_add_number <= ((bfd_vma) 1 << 17))))
- {
- /* sign-extend */
- if (e->X_add_number >= 0
- && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
- {
- e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
- }
- return 1;
- }
+ {
+ /* sign-extend */
+ if (e->X_add_number >= 0
+ && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
+ {
+ e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
+ }
+ return 1;
+ }
break;
case IA64_OPND_IMM14:
/* Sign-extend 32-bit unsigned numbers, so that the following range
checks will work. */
val = e->X_add_number;
- if (((val & (~(bfd_vma)0 << 32)) == 0)
- && ((val & ((bfd_vma)1 << 31)) != 0))
+ if (((val & (~(bfd_vma) 0 << 32)) == 0)
+ && ((val & ((bfd_vma) 1 << 31)) != 0))
val = ((val << 32) >> 32);
/* Check for 0x100000000. This is valid because
/* Sign-extend 32-bit unsigned numbers, so that the following range
checks will work. */
val = e->X_add_number;
- if (((val & (~(bfd_vma)0 << 32)) == 0)
- && ((val & ((bfd_vma)1 << 31)) != 0))
+ if (((val & (~(bfd_vma) 0 << 32)) == 0)
+ && ((val & ((bfd_vma) 1 << 31)) != 0))
val = ((val << 32) >> 32);
}
else
fix->code = BFD_RELOC_IA64_PCREL21M;
else if (opnd == IA64_OPND_TGT25c)
fix->code = BFD_RELOC_IA64_PCREL21B;
- else if (opnd == IA64_OPND_TGT64)
+ else if (opnd == IA64_OPND_TGT64)
fix->code = BFD_RELOC_IA64_PCREL60B;
else
abort ();
/* Returns the next entry in the opcode table that matches the one in
IDESC, and frees the entry in IDESC. If no matching entry is
- found, NULL is returned instead. */
+ found, NULL is returned instead. */
static struct ia64_opcode *
get_next_opcode (struct ia64_opcode *idesc)
/* Parse the operands for the opcode and find the opcode variant that
matches the specified operands, or NULL if no match is possible. */
-static struct ia64_opcode*
+
+static struct ia64_opcode *
parse_operands (idesc)
struct ia64_opcode *idesc;
{
as_bad ("Illegal operand separator `%c'", sep);
return 0;
}
-
+
if (idesc->operands[2] == IA64_OPND_SOF)
{
/* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
CURR_SLOT.opnd[4].X_add_number,
CURR_SLOT.opnd[5].X_add_number);
- /* now we can parse the first arg: */
+ /* now we can parse the first arg: */
saved_input_pointer = input_line_pointer;
input_line_pointer = first_arg;
sep = parse_operand (CURR_SLOT.opnd + 0);
continue;
case IA64_OPND_IMMU62:
- val &= 0x3fffffffffffffffULL;
- if (val != slot->opnd[i].X_add_number)
- as_warn (_("Value truncated to 62 bits"));
- *insnp++ = (val >> 21) & 0x1ffffffffffLL;
- insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
+ val &= 0x3fffffffffffffffULL;
+ if (val != slot->opnd[i].X_add_number)
+ as_warn (_("Value truncated to 62 bits"));
+ *insnp++ = (val >> 21) & 0x1ffffffffffLL;
+ insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
continue;
case IA64_OPND_TGT64:
case IA64_OPND_PKR_R3:
case IA64_OPND_PMC_R3:
case IA64_OPND_PMD_R3:
- case IA64_OPND_RR_R3:
+ case IA64_OPND_RR_R3:
val -= REG_GR;
break;
enum ia64_unit required_unit, insn_unit = 0;
enum ia64_insn_type type[3], insn_type;
unsigned int template, orig_template;
- bfd_vma insn[3] = {-1, -1, -1};
+ bfd_vma insn[3] = { -1, -1, -1 };
struct ia64_opcode *idesc;
int end_of_insn_group = 0, user_template = -1;
int n, i, j, first, curr;
+ unw_rec_list *ptr, *prev;
bfd_vma t0 = 0, t1 = 0;
struct label_fix *lfix;
struct insn_fix *ifix;
n = MIN (3, md.num_slots_in_use);
/* Determine template: user user_template if specified, best match
- otherwise: */
+ otherwise: */
if (md.slot[first].user_template >= 0)
user_template = template = md.slot[first].user_template;
else
{
- /* auto select appropriate template */
+ /* Auto select appropriate template. */
memset (type, 0, sizeof (type));
curr = first;
for (i = 0; i < n; ++i)
{
+ if (md.slot[curr].label_fixups && i != 0)
+ break;
type[i] = md.slot[curr].idesc->type;
curr = (curr + 1) % NUM_SLOTS;
}
template = best_template[type[0]][type[1]][type[2]];
}
- /* initialize instructions with appropriate nops: */
+ /* initialize instructions with appropriate nops: */
for (i = 0; i < 3; ++i)
insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
f = frag_more (16);
- /* now fill in slots with as many insns as possible: */
+ /* now fill in slots with as many insns as possible: */
curr = first;
idesc = md.slot[curr].idesc;
end_of_insn_group = 0;
for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
{
+ /* Set the slot number for prologue/body records now as those
+ refer to the current point, not the point after the
+ instruction has been issued: */
+ /* Don't try to delete prologue/body records here, as that will cause
+ them to also be deleted from the master list of unwind records. */
+ for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
+ if (ptr->r.type == prologue || ptr->r.type == prologue_gr
+ || ptr->r.type == body)
+ {
+ ptr->slot_number = (unsigned long) f + i;
+ ptr->slot_frag = frag_now;
+ }
+
if (idesc->flags & IA64_OPCODE_SLOT2)
{
if (manual_bundling && i != 2)
}
required_unit = ia64_templ_desc[template].exec_unit[i];
- /* resolve dynamic opcodes such as "break" and "nop": */
+ /* resolve dynamic opcodes such as "break" and "nop": */
if (idesc->type == IA64_TYPE_DYN)
{
if ((strcmp (idesc->name, "nop") == 0)
as_fatal ("emit_one_bundle: unexpected dynamic op");
sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
+ ia64_free_opcode (idesc);
md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
#if 0
know (!idesc->next); /* no resolved dynamic ops have collisions */
if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
insn_unit = required_unit;
break;
- case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
+ case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
if (insn_unit != required_unit)
{
if (required_unit == IA64_UNIT_L
- && insn_unit == IA64_UNIT_I
+ && insn_unit == IA64_UNIT_I
&& !(idesc->flags & IA64_OPCODE_X_IN_MLX))
{
/* we got ourselves an MLX template but the current
- instruction isn't an X-unit, or an I-unit instruction
+ instruction isn't an X-unit, or an I-unit instruction
that can go into the X slot of an MLX template. Duh. */
if (md.num_slots_in_use >= NUM_SLOTS)
{
md.slot[curr].src_line,
"`%s' can't go in X slot of "
"MLX template", idesc->name);
- /* drop this insn so we don't livelock: */
+ /* drop this insn so we don't livelock: */
--md.num_slots_in_use;
}
break;
{
bfd_vma addr;
- addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
+ addr = frag_now->fr_address + frag_now_fix () - 16 + i;
dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
}
build_insn (md.slot + curr, insn + i);
- /* Set slot counts for unwind records. */
- while (md.slot[curr].unwind_record)
- {
- md.slot[curr].unwind_record->slot_number = (unsigned long) (f + i);
- md.slot[curr].unwind_record = md.slot[curr].unwind_record->next;
- }
+ /* Set slot counts for non prologue/body unwind records. */
+ for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
+ if (ptr->r.type != prologue && ptr->r.type != prologue_gr
+ && ptr->r.type != body)
+ {
+ ptr->slot_number = (unsigned long) f + i;
+ ptr->slot_frag = frag_now;
+ }
+ md.slot[curr].unwind_record = NULL;
+
if (required_unit == IA64_UNIT_L)
{
know (i == 1);
}
--md.num_slots_in_use;
- /* now is a good time to fix up the labels for this insn: */
+ /* now is a good time to fix up the labels for this insn: */
for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
{
S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
symbol_set_frag (lfix->sym, frag_now);
}
+ /* and fix up the tags also. */
+ for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
+ {
+ S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
+ symbol_set_frag (lfix->sym, frag_now);
+ }
for (j = 0; j < md.slot[curr].num_fixups; ++j)
{
end_of_insn_group = md.slot[curr].end_of_insn_group;
- /* clear slot: */
+ /* clear slot: */
ia64_free_opcode (md.slot[curr].idesc);
memset (md.slot + curr, 0, sizeof (md.slot[curr]));
md.slot[curr].user_template = -1;
t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
- md_number_to_chars (f + 0, t0, 8);
- md_number_to_chars (f + 8, t1, 8);
+ number_to_chars_littleendian (f + 0, t0, 8);
+ number_to_chars_littleendian (f + 8, t1, 8);
+
+ unwind.next_slot_number = (unsigned long) f + 16;
+ unwind.next_slot_frag = frag_now;
}
int
int c;
char *arg;
{
- /* Switches from the Intel assembler. */
switch (c)
{
- case 'M':
+ /* Switches from the Intel assembler. */
+ case 'm':
if (strcmp (arg, "ilp64") == 0
|| strcmp (arg, "lp64") == 0
|| strcmp (arg, "p64") == 0)
case 'N':
if (strcmp (arg, "so") == 0)
{
- /* Suppress signon message. */
+ /* Suppress signon message. */
}
else if (strcmp (arg, "pi") == 0)
{
/* -X conflicts with an ignored option, use -x instead */
md.detect_dv = 1;
if (!arg || strcmp (arg, "explicit") == 0)
- {
- /* set default mode to explicit */
- md.default_explicit_mode = 1;
- break;
- }
+ {
+ /* set default mode to explicit */
+ md.default_explicit_mode = 1;
+ break;
+ }
else if (strcmp (arg, "auto") == 0)
- {
- md.default_explicit_mode = 0;
- }
+ {
+ md.default_explicit_mode = 0;
+ }
else if (strcmp (arg, "debug") == 0)
- {
- md.debug_dv = 1;
- }
+ {
+ md.debug_dv = 1;
+ }
else if (strcmp (arg, "debugx") == 0)
- {
- md.default_explicit_mode = 1;
- md.debug_dv = 1;
- }
+ {
+ md.default_explicit_mode = 1;
+ md.debug_dv = 1;
+ }
else
- {
- as_bad (_("Unrecognized option '-x%s'"), arg);
- }
+ {
+ as_bad (_("Unrecognized option '-x%s'"), arg);
+ }
break;
case 'S':
/* nops Print nops statistics. */
break;
+ /* GNU specific switches for gcc. */
+ case OPTION_MCONSTANT_GP:
+ md.flags |= EF_IA_64_CONS_GP;
+ break;
+
+ case OPTION_MAUTO_PIC:
+ md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
+ break;
+
default:
return 0;
}
md_show_usage (stream)
FILE *stream;
{
- fputs(_("\
+ fputs (_("\
IA-64 options:\n\
- -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
- -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
+ -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
+ -mle | -mbe select little- or big-endian byte order (default -mle)\n\
-x | -xexplicit turn on dependency violation checking (default)\n\
-xauto automagically remove dependency violations\n\
-xdebug debug dependency violation checker\n"),
stream);
}
-static inline int
+/* Return true if TYPE fits in TEMPL at SLOT. */
+
+static int
match (int templ, int type, int slot)
{
enum ia64_unit unit;
return result;
}
+/* Add a bit of extra goodness if a nop of type F or B would fit
+ in TEMPL at SLOT. */
+
+static inline int
+extra_goodness (int templ, int slot)
+{
+ if (slot == 1 && match (templ, IA64_TYPE_F, slot))
+ return 2;
+ if (slot == 2 && match (templ, IA64_TYPE_B, slot))
+ return 1;
+ return 0;
+}
+
/* This function is called once, at assembler startup time. It sets
up all the tables, etc. that the MD part of the assembler will need
that can be determined before arguments are parsed. */
void
md_begin ()
{
- int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
+ int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
const char *err;
char name[8];
bfd_set_section_alignment (stdoutput, text_section, 4);
- target_big_endian = 0;
+ target_big_endian = TARGET_BYTES_BIG_ENDIAN;
pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
- symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_GP_RELATIVE].u.sym =
- symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_LT_RELATIVE].u.sym =
- symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_PC_RELATIVE].u.sym =
-
symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_PLT_RELATIVE].u.sym =
-
symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_SEC_RELATIVE].u.sym =
- symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_SEG_RELATIVE].u.sym =
- symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_LTV_RELATIVE].u.sym =
- symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
- &zero_address_frag);
+ symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
+ &zero_address_frag);
pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
- symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
- &zero_address_frag);
-
- /* compute the table of best templates: */
+ symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
+ &zero_address_frag);
+
+ /* Compute the table of best templates. We compute goodness as a
+ base 4 value, in which each match counts for 3, each F counts
+ for 2, each B counts for 1. This should maximize the number of
+ F and B nops in the chosen bundles, which is good because these
+ pipelines are least likely to be overcommitted. */
for (i = 0; i < IA64_NUM_TYPES; ++i)
for (j = 0; j < IA64_NUM_TYPES; ++j)
for (k = 0; k < IA64_NUM_TYPES; ++k)
if (match (t, j, 1))
{
if (match (t, k, 2))
- goodness = 3;
+ goodness = 3 + 3 + 3;
else
- goodness = 2;
+ goodness = 3 + 3 + extra_goodness (t, 2);
}
else if (match (t, j, 2))
- goodness = 2;
+ goodness = 3 + 3 + extra_goodness (t, 1);
else
- goodness = 1;
+ {
+ goodness = 3;
+ goodness += extra_goodness (t, 1);
+ goodness += extra_goodness (t, 2);
+ }
}
else if (match (t, i, 1))
{
if (match (t, j, 2))
- goodness = 2;
+ goodness = 3 + 3;
else
- goodness = 1;
+ goodness = 3 + extra_goodness (t, 2);
}
else if (match (t, i, 2))
- goodness = 1;
+ goodness = 3 + extra_goodness (t, 1);
if (goodness > best)
{
md.const_hash = hash_new ();
md.entry_hash = hash_new ();
- /* general registers: */
+ /* general registers: */
total = 128;
for (i = 0; i < total; ++i)
md.regsym[i] = declare_register (name, i);
}
- /* floating point registers: */
+ /* floating point registers: */
total += 128;
for (; i < total; ++i)
{
md.regsym[i] = declare_register (name, i);
}
- /* application registers: */
+ /* application registers: */
total += 128;
ar_base = i;
for (; i < total; ++i)
md.regsym[i] = declare_register (name, i);
}
- /* control registers: */
+ /* control registers: */
total += 128;
cr_base = i;
for (; i < total; ++i)
md.regsym[i] = declare_register (name, i);
}
- /* predicate registers: */
+ /* predicate registers: */
total += 64;
for (; i < total; ++i)
{
md.regsym[i] = declare_register (name, i);
}
- /* branch registers: */
+ /* branch registers: */
total += 8;
for (; i < total; ++i)
{
md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
}
- /* define synonyms for application registers: */
+ /* define synonyms for application registers: */
for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
md.regsym[i] = declare_register (ar[i - REG_AR].name,
REG_AR + ar[i - REG_AR].regnum);
- /* define synonyms for control registers: */
+ /* define synonyms for control registers: */
for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
md.regsym[i] = declare_register (cr[i - REG_CR].name,
REG_CR + cr[i - REG_CR].regnum);
declare_register ("sp", REG_GR + 12);
declare_register ("rp", REG_BR + 0);
+ /* pseudo-registers used to specify unwind info: */
+ declare_register ("psp", REG_PSP);
+
declare_register_set ("ret", 4, REG_GR + 8);
declare_register_set ("farg", 8, REG_FR + 8);
declare_register_set ("fret", 8, REG_FR + 8);
name, err);
}
- /* Default to 64-bit mode. */
- md.flags = EF_IA_64_ABI64;
+ /* Set the architecture and machine depending on defaults and command line
+ options. */
+ if (md.flags & EF_IA_64_ABI64)
+ ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
+ else
+ ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
+
+ if (! ok)
+ as_warn (_("Could not set architecture and machine"));
md.mem_offset.hint = 0;
md.path = 0;
md.entry_labels = NULL;
}
+/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
+ because that is called after md_parse_option which is where we do the
+ dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
+ default endianness. */
+
+void
+ia64_init (argc, argv)
+ int argc;
+ char **argv;
+{
+ md.flags = EF_IA_64_ABI64;
+ if (TARGET_BYTES_BIG_ENDIAN)
+ md.flags |= EF_IA_64_BE;
+}
+
+/* Return a string for the target object file format. */
+
+const char *
+ia64_target_format ()
+{
+ if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+ {
+ if (md.flags & EF_IA_64_ABI64)
+ return "elf64-ia64-big";
+ else
+ return "elf32-ia64-big";
+ }
+ else
+ return "unknown-format";
+}
+
void
ia64_end_of_source ()
{
- /* terminate insn group upon reaching end of file: */
+ /* terminate insn group upon reaching end of file: */
insn_group_break (1, 0, 0);
- /* emits slots we haven't written yet: */
+ /* emits slots we haven't written yet: */
ia64_flush_insns ();
bfd_set_private_flags (stdoutput, md.flags);
void
ia64_start_line ()
{
+ if (md.qp.X_op == O_register)
+ as_bad ("qualifying predicate not followed by instruction");
md.qp.X_op = O_absent;
if (ignore_input ())
if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
{
if (md.detect_dv && !md.explicit_mode)
- as_warn (_("Explicit stops are ignored in auto mode"));
+ as_warn (_("Explicit stops are ignored in auto mode"));
else
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
}
}
+/* This is a hook for ia64_frob_label, so that it can distinguish tags from
+ labels. */
+static int defining_tag = 0;
+
int
ia64_unrecognized_line (ch)
int ch;
CURR_SLOT.manual_bundling_on = 1;
md.manual_bundling = 1;
- /* bundling is only acceptable in explicit mode
- or when in default automatic mode */
+ /* Bundling is only acceptable in explicit mode
+ or when in default automatic mode. */
if (md.detect_dv && !md.explicit_mode)
- {
- if (!md.mode_explicitly_set
- && !md.default_explicit_mode)
- dot_dv_mode ('E');
- else
- as_warn (_("Found '{' after explicit switch to automatic mode"));
- }
+ {
+ if (!md.mode_explicitly_set
+ && !md.default_explicit_mode)
+ dot_dv_mode ('E');
+ else
+ as_warn (_("Found '{' after explicit switch to automatic mode"));
+ }
return 1;
case '}':
md.manual_bundling = 0;
/* switch back to automatic mode, if applicable */
- if (md.detect_dv
- && md.explicit_mode
- && !md.mode_explicitly_set
- && !md.default_explicit_mode)
- dot_dv_mode ('A');
+ if (md.detect_dv
+ && md.explicit_mode
+ && !md.mode_explicitly_set
+ && !md.default_explicit_mode)
+ dot_dv_mode ('A');
/* Allow '{' to follow on the same line. We also allow ";;", but that
happens automatically because ';' is an end of line marker. */
demand_empty_rest_of_line ();
return 1;
+ case '[':
+ {
+ char *s;
+ char c;
+ symbolS *tag;
+
+ if (md.qp.X_op == O_register)
+ {
+ as_bad ("Tag must come before qualifying predicate.");
+ return 0;
+ }
+ s = input_line_pointer;
+ c = get_symbol_end ();
+ if (c != ':')
+ {
+ /* Put ':' back for error messages' sake. */
+ *input_line_pointer++ = ':';
+ as_bad ("Expected ':'");
+ return 0;
+ }
+ defining_tag = 1;
+ tag = colon (s);
+ defining_tag = 0;
+ /* Put ':' back for error messages' sake. */
+ *input_line_pointer++ = ':';
+ if (*input_line_pointer++ != ']')
+ {
+ as_bad ("Expected ']'");
+ return 0;
+ }
+ if (! tag)
+ {
+ as_bad ("Tag name expected");
+ return 0;
+ }
+ return 1;
+ }
+
default:
break;
}
- return 0; /* not a valid line */
+
+ /* Not a valid line. */
+ return 0;
}
void
{
struct label_fix *fix;
+ /* Tags need special handling since they are not bundle breaks like
+ labels. */
+ if (defining_tag)
+ {
+ fix = obstack_alloc (¬es, sizeof (*fix));
+ fix->sym = sym;
+ fix->next = CURR_SLOT.tag_fixups;
+ CURR_SLOT.tag_fixups = fix;
+
+ return;
+ }
+
if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
{
md.last_text_seg = now_seg;
fix->next = CURR_SLOT.label_fixups;
CURR_SLOT.label_fixups = fix;
- /* keep track of how many code entry points we've seen */
+ /* Keep track of how many code entry points we've seen. */
if (md.path == md.maxpaths)
- {
- md.maxpaths += 20;
- md.entry_labels = (const char **)
- xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
- }
+ {
+ md.maxpaths += 20;
+ md.entry_labels = (const char **)
+ xrealloc ((void *) md.entry_labels,
+ md.maxpaths * sizeof (char *));
+ }
md.entry_labels[md.path++] = S_GET_NAME (sym);
}
}
struct symbol *sym;
char *end;
- /* first see if NAME is a known register name: */
+ /* first see if NAME is a known register name: */
sym = hash_find (md.reg_hash, name);
if (sym)
{
return 1;
}
- /* check for inN, locN, or outN: */
+ /* check for inN, locN, or outN: */
switch (name[0])
{
case 'i':
if (dr)
{
- /* the name is inN, locN, or outN; parse the register number: */
+ /* The name is inN, locN, or outN; parse the register number. */
regnum = strtoul (name, &end, 10);
if (end > name && *end == '\0')
{
if (!dr->num_regs)
as_bad ("No current frame");
else
- as_bad ("Register number out of range 0..%u", dr->num_regs-1);
+ as_bad ("Register number out of range 0..%u",
+ dr->num_regs - 1);
regnum = 0;
}
e->X_op = O_register;
if ((dr = hash_find (md.dynreg_hash, name)))
{
/* We've got ourselves the name of a rotating register set.
- Store the base register number in the low 16 bits of
- X_add_number and the size of the register set in the top 16
- bits. */
+ Store the base register number in the low 16 bits of
+ X_add_number and the size of the register set in the top 16
+ bits. */
e->X_op = O_register;
e->X_add_number = dr->base | (dr->num_regs << 16);
return 1;
ia64_canonicalize_symbol_name (name)
char *name;
{
- size_t len = strlen(name);
- if (len > 1 && name[len-1] == '#')
- name[len-1] = '\0';
+ size_t len = strlen (name);
+ if (len > 1 && name[len - 1] == '#')
+ name[len - 1] = '\0';
return name;
}
static int
is_conditional_branch (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
return (strncmp (idesc->name, "br", 2) == 0
- && (strcmp (idesc->name, "br") == 0
- || strncmp (idesc->name, "br.cond", 7) == 0
- || strncmp (idesc->name, "br.call", 7) == 0
- || strncmp (idesc->name, "br.ret", 6) == 0
- || strcmp (idesc->name, "brl") == 0
- || strncmp (idesc->name, "brl.cond", 7) == 0
- || strncmp (idesc->name, "brl.call", 7) == 0
- || strncmp (idesc->name, "brl.ret", 6) == 0));
+ && (strcmp (idesc->name, "br") == 0
+ || strncmp (idesc->name, "br.cond", 7) == 0
+ || strncmp (idesc->name, "br.call", 7) == 0
+ || strncmp (idesc->name, "br.ret", 6) == 0
+ || strcmp (idesc->name, "brl") == 0
+ || strncmp (idesc->name, "brl.cond", 7) == 0
+ || strncmp (idesc->name, "brl.call", 7) == 0
+ || strncmp (idesc->name, "brl.ret", 6) == 0));
}
/* Return whether the given opcode is a taken branch. If there's any doubt,
- returns zero */
+ returns zero. */
+
static int
is_taken_branch (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
- || strncmp (idesc->name, "br.ia", 5) == 0);
+ || strncmp (idesc->name, "br.ia", 5) == 0);
}
/* Return whether the given opcode is an interruption or rfi. If there's any
- doubt, returns zero */
+ doubt, returns zero. */
+
static int
is_interruption_or_rfi (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
if (strcmp (idesc->name, "rfi") == 0)
return 1;
/* Returns the index of the given dependency in the opcode's list of chks, or
-1 if there is no dependency. */
+
static int
depends_on (depind, idesc)
- int depind;
- struct ia64_opcode *idesc;
+ int depind;
+ struct ia64_opcode *idesc;
{
int i;
const struct ia64_opcode_dependency *dep = idesc->dependencies;
- for (i = 0;i < dep->nchks; i++)
+ for (i = 0; i < dep->nchks; i++)
{
- if (depind == DEP(dep->chks[i]))
- return i;
+ if (depind == DEP (dep->chks[i]))
+ return i;
}
return -1;
}
/* Determine a set of specific resources used for a particular resource
class. Returns the number of specific resources identified For those
cases which are not determinable statically, the resource returned is
- marked nonspecific.
+ marked nonspecific.
Meanings of value in 'NOTE':
1) only read/write when the register number is explicitly encoded in the
insn.
2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
- accesses CFM when qualifying predicate is in the rotating region.
+ accesses CFM when qualifying predicate is in the rotating region.
3) general register value is used to specify an indirect register; not
determinable statically.
4) only read the given resource when bits 7:0 of the indirect index
5) all rules are implementation specific.
6) only when both the index specified by the reader and the index specified
by the writer have the same value in bits 63:61; not determinable
- statically.
+ statically.
7) only access the specified resource when the corresponding mask bit is
- set
+ set
8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
only read when these insns reference FR2-31
9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
12) This insn only reads the specified predicate register when that
register is the PR[qp].
13) This reference to ld-c only applies to teh GR whose value is loaded
- with data returned from memory, not the post-incremented address register.
+ with data returned from memory, not the post-incremented address register.
14) The RSE resource includes the implementation-specific RSE internal
state resources. At least one (and possibly more) of these resources are
read by each instruction listed in IC:rse-readers. At least one (and
possibly more) of these resources are written by each insn listed in
- IC:rse-writers.
+ IC:rse-writers.
15+16) Represents reserved instructions, which the assembler does not
- generate.
+ generate.
Memory resources (i.e. locations in memory) are *not* marked or tracked by
this code; there are no dependency violations based on memory access.
-
*/
#define MAX_SPECS 256
static int
specify_resource (dep, idesc, type, specs, note, path)
- const struct ia64_dependency *dep;
- struct ia64_opcode *idesc;
- int type; /* is this a DV chk or a DV reg? */
- struct rsrc specs[MAX_SPECS]; /* returned specific resources */
- int note; /* resource note for this insn's usage */
- int path; /* which execution path to examine */
+ const struct ia64_dependency *dep;
+ struct ia64_opcode *idesc;
+ int type; /* is this a DV chk or a DV reg? */
+ struct rsrc specs[MAX_SPECS]; /* returned specific resources */
+ int note; /* resource note for this insn's usage */
+ int path; /* which execution path to examine */
{
int count = 0;
int i;
int rsrc_write = 0;
struct rsrc tmpl;
-
+
if (dep->mode == IA64_DV_WAW
|| (dep->mode == IA64_DV_RAW && type == DV_REG)
|| (dep->mode == IA64_DV_WAR && type == DV_CHK))
tmpl.mem_offset.hint = 0;
tmpl.specific = 1;
tmpl.index = 0;
+ tmpl.cmp_type = CMP_NONE;
#define UNHANDLED \
as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
{
case IA64_RS_AR_K:
if (note == 1)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
- if (regno >= 0 && regno <= 7)
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+ if (regno >= 0 && regno <= 7)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
+ }
else if (note == 0)
- {
- for(i=0;i < 8;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
+ {
+ for (i = 0; i < 8; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_AR_UNAT:
specs[count] = tmpl;
if (md.mem_offset.hint)
{
- if (md.debug_dv)
- fprintf (stderr, " Using hint for spill/fill\n");
- /* the index isn't actually used, just set it to something
- approximating the bit index */
+ if (md.debug_dv)
+ fprintf (stderr, " Using hint for spill/fill\n");
+ /* The index isn't actually used, just set it to something
+ approximating the bit index. */
specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
specs[count].mem_offset.hint = 1;
specs[count].mem_offset.offset = md.mem_offset.offset;
case IA64_RS_AR:
if (note == 1)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
- if ((regno >= 8 && regno <= 15)
- || (regno >= 20 && regno <= 23)
- || (regno >= 31 && regno <= 39)
- || (regno >= 41 && regno <= 47)
- || (regno >= 67 && regno <= 111))
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+ if ((regno >= 8 && regno <= 15)
+ || (regno >= 20 && regno <= 23)
+ || (regno >= 31 && regno <= 39)
+ || (regno >= 41 && regno <= 47)
+ || (regno >= 67 && regno <= 111))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_ARb:
if (note == 1)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
- if ((regno >= 48 && regno <= 63)
- || (regno >= 112 && regno <= 127))
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+ if ((regno >= 48 && regno <= 63)
+ || (regno >= 112 && regno <= 127))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
+ }
else if (note == 0)
- {
- for (i=48;i < 64;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- for (i=112;i < 128;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- else
- {
- UNHANDLED;
- }
+ {
+ for (i = 48; i < 64; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ for (i = 112; i < 128; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_BR:
if (note != 1)
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
else
- {
- if (rsrc_write)
- {
- for (i=0;i < idesc->num_outputs;i++)
- if (idesc->operands[i] == IA64_OPND_B1
- || idesc->operands[i] == IA64_OPND_B2)
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[i].X_add_number - REG_BR;
- }
- }
- else
- {
- for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
- if (idesc->operands[i] == IA64_OPND_B1
- || idesc->operands[i] == IA64_OPND_B2)
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[i].X_add_number - REG_BR;
- }
- }
- }
+ {
+ if (rsrc_write)
+ {
+ for (i = 0; i < idesc->num_outputs; i++)
+ if (idesc->operands[i] == IA64_OPND_B1
+ || idesc->operands[i] == IA64_OPND_B2)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_BR;
+ }
+ }
+ else
+ {
+ for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
+ if (idesc->operands[i] == IA64_OPND_B1
+ || idesc->operands[i] == IA64_OPND_B2)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_BR;
+ }
+ }
+ }
break;
case IA64_RS_CPUID: /* four or more registers */
if (note == 3)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_DBR: /* four or more registers */
if (note == 3)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else if (note == 0 && !rsrc_write)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_IBR: /* four or more registers */
if (note == 3)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_MSR:
case IA64_RS_PKR: /* 16 or more registers */
if (note == 3 || note == 4)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- if (note == 3)
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else for (i=0;i < NELEMS(gr_values);i++)
- {
- /* uses all registers *except* the one in R3 */
- if (i != (gr_values[regno].value & 0xFF))
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ if (note == 3)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ for (i = 0; i < NELEMS (gr_values); i++)
+ {
+ /* Uses all registers *except* the one in R3. */
+ if (i != (gr_values[regno].value & 0xFF))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else if (note == 0)
- {
- /* probe et al. */
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
+ {
+ /* probe et al. */
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
break;
case IA64_RS_PMC: /* four or more registers */
if (note == 3)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
- || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
-
- {
- int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
- ? 1 : !rsrc_write);
- int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
+ || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
+
+ {
+ int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
+ ? 1 : !rsrc_write);
+ int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_PMD: /* four or more registers */
if (note == 3)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = gr_values[regno].value & 0xFF;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = gr_values[regno].value & 0xFF;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_RR: /* eight registers */
if (note == 6)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
- if (regno >= 0 && regno < NELEMS(gr_values)
- && KNOWN(regno))
- {
- specs[count] = tmpl;
- specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
- }
- else
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+ if (regno >= 0 && regno < NELEMS (gr_values)
+ && KNOWN (regno))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
+ }
+ else
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
else if (note == 0 && !rsrc_write)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- else
- {
- UNHANDLED;
- }
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ else
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_CR_IRR:
- if (note == 0)
- {
- /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
- int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
- if (rsrc_write
- && idesc->operands[1] == IA64_OPND_CR3
- && regno == CR_IVR)
- {
- for(i=0;i < 4;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = CR_IRR0 + i;
- }
- }
- }
+ if (note == 0)
+ {
+ /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
+ int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
+ if (rsrc_write
+ && idesc->operands[1] == IA64_OPND_CR3
+ && regno == CR_IVR)
+ {
+ for (i = 0; i < 4; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CR_IRR0 + i;
+ }
+ }
+ }
else if (note == 1)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
- if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
- && regno >= CR_IRR0
- && regno <= CR_IRR3)
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+ if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
+ && regno >= CR_IRR0
+ && regno <= CR_IRR3)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_CR_LRR:
if (note != 1)
- {
- UNHANDLED;
- }
- else
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
- if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
- && (regno == CR_LRR0 || regno == CR_LRR1))
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
+ {
+ UNHANDLED;
+ }
+ else
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+ if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
+ && (regno == CR_LRR0 || regno == CR_LRR1))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
break;
case IA64_RS_CR:
if (note == 1)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_FR:
case IA64_RS_FRb:
if (note != 1)
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
else if (rsrc_write)
- {
- if (dep->specifier == IA64_RS_FRb
- && idesc->operands[0] == IA64_OPND_F1)
- {
- specs[count] = tmpl;
- specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
- }
- }
+ {
+ if (dep->specifier == IA64_RS_FRb
+ && idesc->operands[0] == IA64_OPND_F1)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
+ }
+ }
else
- {
- for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
- {
- if (idesc->operands[i] == IA64_OPND_F2
- || idesc->operands[i] == IA64_OPND_F3
- || idesc->operands[i] == IA64_OPND_F4)
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[i].X_add_number - REG_FR;
- }
- }
- }
+ {
+ for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_F2
+ || idesc->operands[i] == IA64_OPND_F3
+ || idesc->operands[i] == IA64_OPND_F4)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_FR;
+ }
+ }
+ }
break;
case IA64_RS_GR:
if (note == 13)
- {
- /* This reference applies only to the GR whose value is loaded with
- data returned from memory */
- specs[count] = tmpl;
- specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
- }
+ {
+ /* This reference applies only to the GR whose value is loaded with
+ data returned from memory. */
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
+ }
else if (note == 1)
- {
- if (rsrc_write)
- {
- for (i=0;i < idesc->num_outputs;i++)
- {
- if (idesc->operands[i] == IA64_OPND_R1
- || idesc->operands[i] == IA64_OPND_R2
- || idesc->operands[i] == IA64_OPND_R3)
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[i].X_add_number - REG_GR;
- }
- }
- }
- else
- {
- /* Look for anything that reads a GR */
- for (i=0;i < NELEMS(idesc->operands);i++)
- {
- if (idesc->operands[i] == IA64_OPND_MR3
- || idesc->operands[i] == IA64_OPND_CPUID_R3
- || idesc->operands[i] == IA64_OPND_DBR_R3
- || idesc->operands[i] == IA64_OPND_IBR_R3
+ {
+ if (rsrc_write)
+ {
+ for (i = 0; i < idesc->num_outputs; i++)
+ if (idesc->operands[i] == IA64_OPND_R1
+ || idesc->operands[i] == IA64_OPND_R2
+ || idesc->operands[i] == IA64_OPND_R3)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ }
+ if (idesc->flags & IA64_OPCODE_POSTINC)
+ for (i = 0; i < NELEMS (idesc->operands); i++)
+ if (idesc->operands[i] == IA64_OPND_MR3)
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ }
+ }
+ else
+ {
+ /* Look for anything that reads a GR. */
+ for (i = 0; i < NELEMS (idesc->operands); i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_MR3
+ || idesc->operands[i] == IA64_OPND_CPUID_R3
+ || idesc->operands[i] == IA64_OPND_DBR_R3
+ || idesc->operands[i] == IA64_OPND_IBR_R3
|| idesc->operands[i] == IA64_OPND_MSR_R3
- || idesc->operands[i] == IA64_OPND_PKR_R3
- || idesc->operands[i] == IA64_OPND_PMC_R3
- || idesc->operands[i] == IA64_OPND_PMD_R3
- || idesc->operands[i] == IA64_OPND_RR_R3
- || ((i >= idesc->num_outputs)
- && (idesc->operands[i] == IA64_OPND_R1
- || idesc->operands[i] == IA64_OPND_R2
- || idesc->operands[i] == IA64_OPND_R3)))
- {
- specs[count] = tmpl;
- specs[count++].index =
- CURR_SLOT.opnd[i].X_add_number - REG_GR;
- }
- }
- }
- }
- else
- {
- UNHANDLED;
- }
+ || idesc->operands[i] == IA64_OPND_PKR_R3
+ || idesc->operands[i] == IA64_OPND_PMC_R3
+ || idesc->operands[i] == IA64_OPND_PMD_R3
+ || idesc->operands[i] == IA64_OPND_RR_R3
+ || ((i >= idesc->num_outputs)
+ && (idesc->operands[i] == IA64_OPND_R1
+ || idesc->operands[i] == IA64_OPND_R2
+ || idesc->operands[i] == IA64_OPND_R3
+ /* addl source register. */
+ || idesc->operands[i] == IA64_OPND_R3_2)))
+ {
+ specs[count] = tmpl;
+ specs[count++].index =
+ CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ }
+ }
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
break;
+ /* This is the same as IA64_RS_PRr, except that the register range is
+ from 1 - 15, and there are no rotating register reads/writes here. */
case IA64_RS_PR:
if (note == 0)
- {
- if (idesc->operands[0] == IA64_OPND_PR_ROT)
- {
- for (i=16;i < 63;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- else
- {
- for (i=1;i < 63;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- }
- else if (note == 7)
- {
- valueT mask = 0;
- /* mark only those registers indicated by the mask */
- if (rsrc_write
- && idesc->operands[0] == IA64_OPND_PR)
- {
- mask = CURR_SLOT.opnd[2].X_add_number;
- if (mask & ((valueT)1<<16))
- mask |= ~(valueT)0xffff;
- for (i=1;i < 63;i++)
- {
- if (mask & ((valueT)1<<i))
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- }
- else if (rsrc_write
- && idesc->operands[0] == IA64_OPND_PR_ROT)
- {
- for (i=16;i < 63;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- else
- {
- UNHANDLED;
- }
- }
+ {
+ for (i = 1; i < 16; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else if (note == 7)
+ {
+ valueT mask = 0;
+ /* Mark only those registers indicated by the mask. */
+ if (rsrc_write)
+ {
+ mask = CURR_SLOT.opnd[2].X_add_number;
+ for (i = 1; i < 16; i++)
+ if (mask & ((valueT) 1 << i))
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ }
else if (note == 11) /* note 11 implies note 1 as well */
- {
- if (rsrc_write)
- {
- for (i=0;i < idesc->num_outputs;i++)
- {
- if (idesc->operands[i] == IA64_OPND_P1
- || idesc->operands[i] == IA64_OPND_P2)
- {
- int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
- if (regno != 0)
- {
- specs[count] = tmpl;
- specs[count++].index = regno;
- }
- }
- }
- }
- else
- {
- UNHANDLED;
- }
- }
+ {
+ if (rsrc_write)
+ {
+ for (i = 0; i < idesc->num_outputs; i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_P1
+ || idesc->operands[i] == IA64_OPND_P2)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
+ if (regno >= 1 && regno < 16)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ }
else if (note == 12)
- {
- if (CURR_SLOT.qp_regno != 0)
- {
- specs[count] = tmpl;
- specs[count++].index = CURR_SLOT.qp_regno;
- }
- }
+ {
+ if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.qp_regno;
+ }
+ }
else if (note == 1)
- {
- if (rsrc_write)
- {
- int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
- int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
- if ((idesc->operands[0] == IA64_OPND_P1
- || idesc->operands[0] == IA64_OPND_P2)
- && p1 != 0 && p1 != 63)
- {
- specs[count] = tmpl;
- specs[count++].index = p1;
- }
- if ((idesc->operands[1] == IA64_OPND_P1
- || idesc->operands[1] == IA64_OPND_P2)
- && p2 != 0 && p2 != 63)
- {
- specs[count] = tmpl;
- specs[count++].index = p2;
- }
- }
- else
- {
- if (CURR_SLOT.qp_regno != 0)
- {
- specs[count] = tmpl;
- specs[count++].index = CURR_SLOT.qp_regno;
- }
- if (idesc->operands[1] == IA64_OPND_PR)
- {
- for (i=1;i < 63;i++)
- {
- specs[count] = tmpl;
- specs[count++].index = i;
- }
- }
- }
- }
- else
- {
- UNHANDLED;
- }
+ {
+ if (rsrc_write)
+ {
+ int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
+ int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
+ int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
+ int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
+
+ if ((idesc->operands[0] == IA64_OPND_P1
+ || idesc->operands[0] == IA64_OPND_P2)
+ && p1 >= 1 && p1 < 16)
+ {
+ specs[count] = tmpl;
+ specs[count].cmp_type =
+ (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
+ specs[count++].index = p1;
+ }
+ if ((idesc->operands[1] == IA64_OPND_P1
+ || idesc->operands[1] == IA64_OPND_P2)
+ && p2 >= 1 && p2 < 16)
+ {
+ specs[count] = tmpl;
+ specs[count].cmp_type =
+ (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
+ specs[count++].index = p2;
+ }
+ }
+ else
+ {
+ if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.qp_regno;
+ }
+ if (idesc->operands[1] == IA64_OPND_PR)
+ {
+ for (i = 1; i < 16; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ break;
+
+ /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
+ simplified cases of this. */
+ case IA64_RS_PRr:
+ if (note == 0)
+ {
+ for (i = 16; i < 63; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else if (note == 7)
+ {
+ valueT mask = 0;
+ /* Mark only those registers indicated by the mask. */
+ if (rsrc_write
+ && idesc->operands[0] == IA64_OPND_PR)
+ {
+ mask = CURR_SLOT.opnd[2].X_add_number;
+ if (mask & ((valueT) 1<<16))
+ for (i = 16; i < 63; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else if (rsrc_write
+ && idesc->operands[0] == IA64_OPND_PR_ROT)
+ {
+ for (i = 16; i < 63; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ }
+ else if (note == 11) /* note 11 implies note 1 as well */
+ {
+ if (rsrc_write)
+ {
+ for (i = 0; i < idesc->num_outputs; i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_P1
+ || idesc->operands[i] == IA64_OPND_P2)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
+ if (regno >= 16 && regno < 63)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = regno;
+ }
+ }
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ }
+ else if (note == 12)
+ {
+ if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.qp_regno;
+ }
+ }
+ else if (note == 1)
+ {
+ if (rsrc_write)
+ {
+ int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
+ int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
+ int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
+ int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
+
+ if ((idesc->operands[0] == IA64_OPND_P1
+ || idesc->operands[0] == IA64_OPND_P2)
+ && p1 >= 16 && p1 < 63)
+ {
+ specs[count] = tmpl;
+ specs[count].cmp_type =
+ (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
+ specs[count++].index = p1;
+ }
+ if ((idesc->operands[1] == IA64_OPND_P1
+ || idesc->operands[1] == IA64_OPND_P2)
+ && p2 >= 16 && p2 < 63)
+ {
+ specs[count] = tmpl;
+ specs[count].cmp_type =
+ (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
+ specs[count++].index = p2;
+ }
+ }
+ else
+ {
+ if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = CURR_SLOT.qp_regno;
+ }
+ if (idesc->operands[1] == IA64_OPND_PR)
+ {
+ for (i = 16; i < 63; i++)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = i;
+ }
+ }
+ }
+ }
+ else
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_PSR:
- /* Verify that the instruction is using the PSR bit indicated in
- dep->regindex */
+ /* Verify that the instruction is using the PSR bit indicated in
+ dep->regindex. */
if (note == 0)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
- {
- if (dep->regindex < 6)
- {
- specs[count++] = tmpl;
- }
- }
- else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
- {
- if (dep->regindex < 32
- || dep->regindex == 35
- || dep->regindex == 36
- || (!rsrc_write && dep->regindex == PSR_CPL))
- {
- specs[count++] = tmpl;
- }
- }
- else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
- {
- if (dep->regindex < 32
- || dep->regindex == 35
- || dep->regindex == 36
- || (rsrc_write && dep->regindex == PSR_CPL))
- {
- specs[count++] = tmpl;
- }
- }
- else
- {
- /* Several PSR bits have very specific dependencies. */
- switch (dep->regindex)
- {
- default:
- specs[count++] = tmpl;
- break;
- case PSR_IC:
- if (rsrc_write)
- {
- specs[count++] = tmpl;
- }
- else
- {
- /* Only certain CR accesses use PSR.ic */
- if (idesc->operands[0] == IA64_OPND_CR3
- || idesc->operands[1] == IA64_OPND_CR3)
- {
- int index =
- ((idesc->operands[0] == IA64_OPND_CR3)
- ? 0 : 1);
- int regno =
- CURR_SLOT.opnd[index].X_add_number - REG_CR;
-
- switch (regno)
- {
- default:
- break;
- case CR_ITIR:
- case CR_IFS:
- case CR_IIM:
- case CR_IIP:
- case CR_IPSR:
- case CR_ISR:
- case CR_IFA:
- case CR_IHA:
- case CR_IIPA:
- specs[count++] = tmpl;
- break;
- }
- }
- }
- break;
- case PSR_CPL:
- if (rsrc_write)
- {
- specs[count++] = tmpl;
- }
- else
- {
- /* Only some AR accesses use cpl */
- if (idesc->operands[0] == IA64_OPND_AR3
- || idesc->operands[1] == IA64_OPND_AR3)
- {
- int index =
- ((idesc->operands[0] == IA64_OPND_AR3)
- ? 0 : 1);
- int regno =
- CURR_SLOT.opnd[index].X_add_number - REG_AR;
-
- if (regno == AR_ITC
- || (index == 0
- && (regno == AR_ITC
- || regno == AR_RSC
- || (regno >= AR_K0
- && regno <= AR_K7))))
- {
- specs[count++] = tmpl;
- }
- }
- else
- {
- specs[count++] = tmpl;
- }
- break;
- }
- }
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
+ {
+ if (dep->regindex < 6)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
+ {
+ if (dep->regindex < 32
+ || dep->regindex == 35
+ || dep->regindex == 36
+ || (!rsrc_write && dep->regindex == PSR_CPL))
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
+ {
+ if (dep->regindex < 32
+ || dep->regindex == 35
+ || dep->regindex == 36
+ || (rsrc_write && dep->regindex == PSR_CPL))
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else
+ {
+ /* Several PSR bits have very specific dependencies. */
+ switch (dep->regindex)
+ {
+ default:
+ specs[count++] = tmpl;
+ break;
+ case PSR_IC:
+ if (rsrc_write)
+ {
+ specs[count++] = tmpl;
+ }
+ else
+ {
+ /* Only certain CR accesses use PSR.ic */
+ if (idesc->operands[0] == IA64_OPND_CR3
+ || idesc->operands[1] == IA64_OPND_CR3)
+ {
+ int index =
+ ((idesc->operands[0] == IA64_OPND_CR3)
+ ? 0 : 1);
+ int regno =
+ CURR_SLOT.opnd[index].X_add_number - REG_CR;
+
+ switch (regno)
+ {
+ default:
+ break;
+ case CR_ITIR:
+ case CR_IFS:
+ case CR_IIM:
+ case CR_IIP:
+ case CR_IPSR:
+ case CR_ISR:
+ case CR_IFA:
+ case CR_IHA:
+ case CR_IIPA:
+ specs[count++] = tmpl;
+ break;
+ }
+ }
+ }
+ break;
+ case PSR_CPL:
+ if (rsrc_write)
+ {
+ specs[count++] = tmpl;
+ }
+ else
+ {
+ /* Only some AR accesses use cpl */
+ if (idesc->operands[0] == IA64_OPND_AR3
+ || idesc->operands[1] == IA64_OPND_AR3)
+ {
+ int index =
+ ((idesc->operands[0] == IA64_OPND_AR3)
+ ? 0 : 1);
+ int regno =
+ CURR_SLOT.opnd[index].X_add_number - REG_AR;
+
+ if (regno == AR_ITC
+ || (index == 0
+ && (regno == AR_ITC
+ || regno == AR_RSC
+ || (regno >= AR_K0
+ && regno <= AR_K7))))
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else
+ {
+ specs[count++] = tmpl;
+ }
+ break;
+ }
+ }
+ }
+ }
else if (note == 7)
- {
- valueT mask = 0;
- if (idesc->operands[0] == IA64_OPND_IMMU24)
- {
- mask = CURR_SLOT.opnd[0].X_add_number;
- }
- else
- {
- UNHANDLED;
- }
- if (mask & ((valueT)1<<dep->regindex))
- {
- specs[count++] = tmpl;
- }
- }
+ {
+ valueT mask = 0;
+ if (idesc->operands[0] == IA64_OPND_IMMU24)
+ {
+ mask = CURR_SLOT.opnd[0].X_add_number;
+ }
+ else
+ {
+ UNHANDLED;
+ }
+ if (mask & ((valueT) 1 << dep->regindex))
+ {
+ specs[count++] = tmpl;
+ }
+ }
else if (note == 8)
- {
- int min = dep->regindex == PSR_DFL ? 2 : 32;
- int max = dep->regindex == PSR_DFL ? 31 : 127;
- /* dfh is read on FR32-127; dfl is read on FR2-31 */
- for (i=0;i < NELEMS(idesc->operands);i++)
- {
- if (idesc->operands[i] == IA64_OPND_F1
- || idesc->operands[i] == IA64_OPND_F2
- || idesc->operands[i] == IA64_OPND_F3
- || idesc->operands[i] == IA64_OPND_F4)
- {
- int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
- if (reg >= min && reg <= max)
- {
- specs[count++] = tmpl;
- }
- }
- }
- }
+ {
+ int min = dep->regindex == PSR_DFL ? 2 : 32;
+ int max = dep->regindex == PSR_DFL ? 31 : 127;
+ /* dfh is read on FR32-127; dfl is read on FR2-31 */
+ for (i = 0; i < NELEMS (idesc->operands); i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_F1
+ || idesc->operands[i] == IA64_OPND_F2
+ || idesc->operands[i] == IA64_OPND_F3
+ || idesc->operands[i] == IA64_OPND_F4)
+ {
+ int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+ if (reg >= min && reg <= max)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
+ }
else if (note == 9)
- {
- int min = dep->regindex == PSR_MFL ? 2 : 32;
- int max = dep->regindex == PSR_MFL ? 31 : 127;
- /* mfh is read on writes to FR32-127; mfl is read on writes to
- FR2-31 */
- for (i=0;i < idesc->num_outputs;i++)
- {
- if (idesc->operands[i] == IA64_OPND_F1)
- {
- int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
- if (reg >= min && reg <= max)
- {
- specs[count++] = tmpl;
- }
- }
- }
- }
+ {
+ int min = dep->regindex == PSR_MFL ? 2 : 32;
+ int max = dep->regindex == PSR_MFL ? 31 : 127;
+ /* mfh is read on writes to FR32-127; mfl is read on writes to
+ FR2-31 */
+ for (i = 0; i < idesc->num_outputs; i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_F1)
+ {
+ int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+ if (reg >= min && reg <= max)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
+ }
else if (note == 10)
- {
- for (i=0;i < NELEMS(idesc->operands);i++)
- {
- if (idesc->operands[i] == IA64_OPND_R1
- || idesc->operands[i] == IA64_OPND_R2
- || idesc->operands[i] == IA64_OPND_R3)
- {
- int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
- if (regno >= 16 && regno <= 31)
- {
- specs[count++] = tmpl;
- }
- }
- }
- }
+ {
+ for (i = 0; i < NELEMS (idesc->operands); i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_R1
+ || idesc->operands[i] == IA64_OPND_R2
+ || idesc->operands[i] == IA64_OPND_R3)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ if (regno >= 16 && regno <= 31)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_AR_FPSR:
if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
- if (regno == AR_FPSR)
- {
- specs[count++] = tmpl;
- }
- }
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+ if (regno == AR_FPSR)
+ {
+ specs[count++] = tmpl;
+ }
+ }
else
- {
- specs[count++] = tmpl;
- }
+ {
+ specs[count++] = tmpl;
+ }
break;
- case IA64_RS_ARX:
+ case IA64_RS_ARX:
/* Handle all AR[REG] resources */
if (note == 0 || note == 1)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
- if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
- && regno == dep->regindex)
- {
- specs[count++] = tmpl;
- }
- /* other AR[REG] resources may be affected by AR accesses */
- else if (idesc->operands[0] == IA64_OPND_AR3)
- {
- /* AR[] writes */
- regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
- switch (dep->regindex)
- {
- default:
- break;
- case AR_BSP:
- case AR_RNAT:
- if (regno == AR_BSPSTORE)
- {
- specs[count++] = tmpl;
- }
- case AR_RSC:
- if (!rsrc_write &&
- (regno == AR_BSPSTORE
- || regno == AR_RNAT))
- {
- specs[count++] = tmpl;
- }
- break;
- }
- }
- else if (idesc->operands[1] == IA64_OPND_AR3)
- {
- /* AR[] reads */
- regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
- switch (dep->regindex)
- {
- default:
- break;
- case AR_RSC:
- if (regno == AR_BSPSTORE || regno == AR_RNAT)
- {
- specs[count++] = tmpl;
- }
- break;
- }
- }
- else
- {
- specs[count++] = tmpl;
- }
- }
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+ if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
+ && regno == dep->regindex)
+ {
+ specs[count++] = tmpl;
+ }
+ /* other AR[REG] resources may be affected by AR accesses */
+ else if (idesc->operands[0] == IA64_OPND_AR3)
+ {
+ /* AR[] writes */
+ regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
+ switch (dep->regindex)
+ {
+ default:
+ break;
+ case AR_BSP:
+ case AR_RNAT:
+ if (regno == AR_BSPSTORE)
+ {
+ specs[count++] = tmpl;
+ }
+ case AR_RSC:
+ if (!rsrc_write &&
+ (regno == AR_BSPSTORE
+ || regno == AR_RNAT))
+ {
+ specs[count++] = tmpl;
+ }
+ break;
+ }
+ }
+ else if (idesc->operands[1] == IA64_OPND_AR3)
+ {
+ /* AR[] reads */
+ regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
+ switch (dep->regindex)
+ {
+ default:
+ break;
+ case AR_RSC:
+ if (regno == AR_BSPSTORE || regno == AR_RNAT)
+ {
+ specs[count++] = tmpl;
+ }
+ break;
+ }
+ }
+ else
+ {
+ specs[count++] = tmpl;
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_CRX:
/* Handle all CR[REG] resources */
if (note == 0 || note == 1)
- {
- if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
- {
- int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
- if (regno == dep->regindex)
- {
- specs[count++] = tmpl;
- }
- else if (!rsrc_write)
- {
- /* Reads from CR[IVR] affect other resources. */
- if (regno == CR_IVR)
- {
- if ((dep->regindex >= CR_IRR0
- && dep->regindex <= CR_IRR3)
- || dep->regindex == CR_TPR)
- {
- specs[count++] = tmpl;
- }
- }
- }
- }
- else
- {
- specs[count++] = tmpl;
- }
- }
+ {
+ if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
+ {
+ int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+ if (regno == dep->regindex)
+ {
+ specs[count++] = tmpl;
+ }
+ else if (!rsrc_write)
+ {
+ /* Reads from CR[IVR] affect other resources. */
+ if (regno == CR_IVR)
+ {
+ if ((dep->regindex >= CR_IRR0
+ && dep->regindex <= CR_IRR3)
+ || dep->regindex == CR_TPR)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
+ }
+ else
+ {
+ specs[count++] = tmpl;
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_INSERVICE:
/* look for write of EOI (67) or read of IVR (65) */
if ((idesc->operands[0] == IA64_OPND_CR3
- && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
- || (idesc->operands[1] == IA64_OPND_CR3
- && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
- {
- specs[count++] = tmpl;
- }
+ && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
+ || (idesc->operands[1] == IA64_OPND_CR3
+ && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
+ {
+ specs[count++] = tmpl;
+ }
break;
case IA64_RS_GR0:
if (note == 1)
- {
- specs[count++] = tmpl;
- }
+ {
+ specs[count++] = tmpl;
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_CFM:
if (note != 2)
- {
- specs[count++] = tmpl;
- }
+ {
+ specs[count++] = tmpl;
+ }
else
- {
- /* Check if any of the registers accessed are in the rotating region.
- mov to/from pr accesses CFM only when qp_regno is in the rotating
- region */
- for (i=0;i < NELEMS(idesc->operands);i++)
- {
- if (idesc->operands[i] == IA64_OPND_R1
- || idesc->operands[i] == IA64_OPND_R2
- || idesc->operands[i] == IA64_OPND_R3)
- {
- int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
- /* Assumes that md.rot.num_regs is always valid */
- if (md.rot.num_regs > 0
- && num > 31
- && num < 31 + md.rot.num_regs)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- else if (idesc->operands[i] == IA64_OPND_F1
- || idesc->operands[i] == IA64_OPND_F2
- || idesc->operands[i] == IA64_OPND_F3
- || idesc->operands[i] == IA64_OPND_F4)
- {
- int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
- if (num > 31)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- else if (idesc->operands[i] == IA64_OPND_P1
- || idesc->operands[i] == IA64_OPND_P2)
- {
- int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
- if (num > 15)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
- }
- if (CURR_SLOT.qp_regno > 15)
- {
- specs[count] = tmpl;
- specs[count++].specific = 0;
- }
- }
+ {
+ /* Check if any of the registers accessed are in the rotating region.
+ mov to/from pr accesses CFM only when qp_regno is in the rotating
+ region */
+ for (i = 0; i < NELEMS (idesc->operands); i++)
+ {
+ if (idesc->operands[i] == IA64_OPND_R1
+ || idesc->operands[i] == IA64_OPND_R2
+ || idesc->operands[i] == IA64_OPND_R3)
+ {
+ int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ /* Assumes that md.rot.num_regs is always valid */
+ if (md.rot.num_regs > 0
+ && num > 31
+ && num < 31 + md.rot.num_regs)
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ else if (idesc->operands[i] == IA64_OPND_F1
+ || idesc->operands[i] == IA64_OPND_F2
+ || idesc->operands[i] == IA64_OPND_F3
+ || idesc->operands[i] == IA64_OPND_F4)
+ {
+ int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+ if (num > 31)
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ else if (idesc->operands[i] == IA64_OPND_P1
+ || idesc->operands[i] == IA64_OPND_P2)
+ {
+ int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
+ if (num > 15)
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
+ }
+ if (CURR_SLOT.qp_regno > 15)
+ {
+ specs[count] = tmpl;
+ specs[count++].specific = 0;
+ }
+ }
break;
+ /* This is the same as IA64_RS_PRr, except simplified to account for
+ the fact that there is only one register. */
case IA64_RS_PR63:
if (note == 0)
- {
- specs[count++] = tmpl;
- }
- else if (note == 11)
- {
- if ((idesc->operands[0] == IA64_OPND_P1
- && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
- || (idesc->operands[1] == IA64_OPND_P2
- && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
- {
- specs[count++] = tmpl;
- }
- }
- else if (note == 12)
- {
- if (CURR_SLOT.qp_regno == 63)
- {
- specs[count++] = tmpl;
- }
- }
+ {
+ specs[count++] = tmpl;
+ }
else if (note == 7)
{
valueT mask = 0;
if (idesc->operands[2] == IA64_OPND_IMM17)
mask = CURR_SLOT.opnd[2].X_add_number;
- if (mask & ((valueT)1<<63))
- {
- specs[count++] = tmpl;
- }
+ if (mask & ((valueT) 1 << 63))
+ specs[count++] = tmpl;
}
+ else if (note == 11)
+ {
+ if ((idesc->operands[0] == IA64_OPND_P1
+ && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
+ || (idesc->operands[1] == IA64_OPND_P2
+ && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else if (note == 12)
+ {
+ if (CURR_SLOT.qp_regno == 63)
+ {
+ specs[count++] = tmpl;
+ }
+ }
else if (note == 1)
- {
- if (rsrc_write)
- {
- for (i=0;i < idesc->num_outputs;i++)
- if ((idesc->operands[i] == IA64_OPND_P1
- || idesc->operands[i] == IA64_OPND_P2)
- && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
- {
- specs[count++] = tmpl;
- }
- }
- else
- {
- if (CURR_SLOT.qp_regno == 63)
- {
- specs[count++] = tmpl;
- }
- }
- }
+ {
+ if (rsrc_write)
+ {
+ int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
+ int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
+ int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
+ int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
+
+ if (p1 == 63
+ && (idesc->operands[0] == IA64_OPND_P1
+ || idesc->operands[0] == IA64_OPND_P2))
+ {
+ specs[count] = tmpl;
+ specs[count++].cmp_type =
+ (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
+ }
+ if (p2 == 63
+ && (idesc->operands[1] == IA64_OPND_P1
+ || idesc->operands[1] == IA64_OPND_P2))
+ {
+ specs[count] = tmpl;
+ specs[count++].cmp_type =
+ (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
+ }
+ }
+ else
+ {
+ if (CURR_SLOT.qp_regno == 63)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
else
- {
- UNHANDLED;
- }
+ {
+ UNHANDLED;
+ }
break;
case IA64_RS_RSE:
/* FIXME we can identify some individual RSE written resources, but RSE
- read resources have not yet been completely identified, so for now
- treat RSE as a single resource */
+ read resources have not yet been completely identified, so for now
+ treat RSE as a single resource */
if (strncmp (idesc->name, "mov", 3) == 0)
- {
- if (rsrc_write)
- {
- if (idesc->operands[0] == IA64_OPND_AR3
- && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
- {
- specs[count] = tmpl;
- specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
- }
- }
- else
- {
- if (idesc->operands[0] == IA64_OPND_AR3)
- {
- if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
- || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
- {
- specs[count++] = tmpl;
- }
- }
- else if (idesc->operands[1] == IA64_OPND_AR3)
- {
- if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
- || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
- || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
- {
- specs[count++] = tmpl;
- }
- }
- }
- }
- else
- {
- specs[count++] = tmpl;
- }
+ {
+ if (rsrc_write)
+ {
+ if (idesc->operands[0] == IA64_OPND_AR3
+ && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
+ {
+ specs[count] = tmpl;
+ specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
+ }
+ }
+ else
+ {
+ if (idesc->operands[0] == IA64_OPND_AR3)
+ {
+ if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
+ || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ else if (idesc->operands[1] == IA64_OPND_AR3)
+ {
+ if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
+ || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
+ || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
+ {
+ specs[count++] = tmpl;
+ }
+ }
+ }
+ }
+ else
+ {
+ specs[count++] = tmpl;
+ }
break;
case IA64_RS_ANY:
}
/* Clear branch flags on marked resources. This breaks the link between the
- QP of the marking instruction and a subsequent branch on the same QP.
-*/
+ QP of the marking instruction and a subsequent branch on the same QP. */
+
static void
clear_qp_branch_flag (mask)
- valueT mask;
+ valueT mask;
{
int i;
- for (i = 0;i < regdepslen;i++)
+ for (i = 0; i < regdepslen; i++)
{
- valueT bit = ((valueT)1 << regdeps[i].qp_regno);
+ valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
if ((bit & mask) != 0)
- {
- regdeps[i].link_to_qp_branch = 0;
- }
+ {
+ regdeps[i].link_to_qp_branch = 0;
+ }
}
}
-/* Remove any mutexes which contain any of the PRs indicated in the mask.
+/* Remove any mutexes which contain any of the PRs indicated in the mask.
+
+ Any changes to a PR clears the mutex relations which include that PR. */
- Any changes to a PR clears the mutex relations which include that PR.
-*/
static void
clear_qp_mutex (mask)
- valueT mask;
+ valueT mask;
{
int i;
while (i < qp_mutexeslen)
{
if ((qp_mutexes[i].prmask & mask) != 0)
- {
- if (md.debug_dv)
- {
- fprintf (stderr, " Clearing mutex relation");
- print_prmask (qp_mutexes[i].prmask);
- fprintf (stderr, "\n");
- }
- qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
- }
+ {
+ if (md.debug_dv)
+ {
+ fprintf (stderr, " Clearing mutex relation");
+ print_prmask (qp_mutexes[i].prmask);
+ fprintf (stderr, "\n");
+ }
+ qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
+ }
else
- ++i;
+ ++i;
}
}
/* Clear implies relations which contain PRs in the given masks.
P1_MASK indicates the source of the implies relation, while P2_MASK
- indicates the implied PR.
-*/
+ indicates the implied PR. */
+
static void
clear_qp_implies (p1_mask, p2_mask)
- valueT p1_mask;
- valueT p2_mask;
+ valueT p1_mask;
+ valueT p2_mask;
{
int i;
i = 0;
while (i < qp_implieslen)
{
- if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
- || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
- {
- if (md.debug_dv)
- fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
- qp_implies[i].p1, qp_implies[i].p2);
- qp_implies[i] = qp_implies[--qp_implieslen];
- }
- else
- ++i;
+ if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
+ || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
+ {
+ if (md.debug_dv)
+ fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
+ qp_implies[i].p1, qp_implies[i].p2);
+ qp_implies[i] = qp_implies[--qp_implieslen];
+ }
+ else
+ ++i;
}
}
-/* add the PRs specified to the list of implied relations */
+/* Add the PRs specified to the list of implied relations. */
+
static void
add_qp_imply (p1, p2)
- int p1, p2;
+ int p1, p2;
{
valueT mask;
valueT bit;
int i;
- /* p0 is not meaningful here */
+ /* p0 is not meaningful here. */
if (p1 == 0 || p2 == 0)
abort ();
if (p1 == p2)
return;
- /* if it exists already, ignore it */
- for (i=0;i < qp_implieslen;i++)
+ /* If it exists already, ignore it. */
+ for (i = 0; i < qp_implieslen; i++)
{
- if (qp_implies[i].p1 == p1
- && qp_implies[i].p2 == p2
- && qp_implies[i].path == md.path
- && !qp_implies[i].p2_branched)
- return;
+ if (qp_implies[i].p1 == p1
+ && qp_implies[i].p2 == p2
+ && qp_implies[i].path == md.path
+ && !qp_implies[i].p2_branched)
+ return;
}
if (qp_implieslen == qp_impliestotlen)
{
qp_impliestotlen += 20;
qp_implies = (struct qp_imply *)
- xrealloc ((void *)qp_implies,
- qp_impliestotlen * sizeof (struct qp_imply));
+ xrealloc ((void *) qp_implies,
+ qp_impliestotlen * sizeof (struct qp_imply));
}
if (md.debug_dv)
fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
/* Add in the implied transitive relations; for everything that p2 implies,
make p1 imply that, too; for everything that implies p1, make it imply p2
- as well. */
- for (i=0;i < qp_implieslen;i++)
+ as well. */
+ for (i = 0; i < qp_implieslen; i++)
{
if (qp_implies[i].p1 == p2)
- add_qp_imply (p1, qp_implies[i].p2);
+ add_qp_imply (p1, qp_implies[i].p2);
if (qp_implies[i].p2 == p1)
- add_qp_imply (qp_implies[i].p1, p2);
+ add_qp_imply (qp_implies[i].p1, p2);
}
/* Add in mutex relations implied by this implies relation; for each mutex
- relation containing p2, duplicate it and replace p2 with p1. */
- bit = (valueT)1 << p1;
- mask = (valueT)1 << p2;
- for (i=0;i < qp_mutexeslen;i++)
+ relation containing p2, duplicate it and replace p2 with p1. */
+ bit = (valueT) 1 << p1;
+ mask = (valueT) 1 << p2;
+ for (i = 0; i < qp_mutexeslen; i++)
{
if (qp_mutexes[i].prmask & mask)
- add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
+ add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
}
}
-
/* Add the PRs specified in the mask to the mutex list; this means that only
one of the PRs can be true at any time. PR0 should never be included in
the mask. */
+
static void
add_qp_mutex (mask)
- valueT mask;
+ valueT mask;
{
if (mask & 0x1)
abort ();
{
qp_mutexestotlen += 20;
qp_mutexes = (struct qpmutex *)
- xrealloc ((void *)qp_mutexes,
- qp_mutexestotlen * sizeof (struct qpmutex));
+ xrealloc ((void *) qp_mutexes,
+ qp_mutexestotlen * sizeof (struct qpmutex));
}
if (md.debug_dv)
{
int i;
if (md.debug_dv)
fprintf (stderr, " Clearing register values\n");
- for (i=1;i < NELEMS(gr_values);i++)
+ for (i = 1; i < NELEMS (gr_values); i++)
gr_values[i].known = 0;
}
/* Keep track of register values/changes which affect DV tracking.
optimization note: should add a flag to classes of insns where otherwise we
- have to examine a group of strings to identify them.
+ have to examine a group of strings to identify them. */
- */
static void
note_register_values (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
valueT qp_changemask = 0;
int i;
- /* invalidate values for registers being written to */
- for (i=0;i < idesc->num_outputs;i++)
+ /* Invalidate values for registers being written to. */
+ for (i = 0; i < idesc->num_outputs; i++)
{
- if (idesc->operands[i] == IA64_OPND_R1
- || idesc->operands[i] == IA64_OPND_R2
- || idesc->operands[i] == IA64_OPND_R3)
- {
- int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
- if (regno > 0 && regno < NELEMS(gr_values))
- gr_values[regno].known = 0;
- }
- else if (idesc->operands[i] == IA64_OPND_P1
- || idesc->operands[i] == IA64_OPND_P2)
- {
- int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
- qp_changemask |= (valueT)1 << regno;
- }
+ if (idesc->operands[i] == IA64_OPND_R1
+ || idesc->operands[i] == IA64_OPND_R2
+ || idesc->operands[i] == IA64_OPND_R3)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ if (regno > 0 && regno < NELEMS (gr_values))
+ gr_values[regno].known = 0;
+ }
+ else if (idesc->operands[i] == IA64_OPND_R3_2)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+ if (regno > 0 && regno < 4)
+ gr_values[regno].known = 0;
+ }
+ else if (idesc->operands[i] == IA64_OPND_P1
+ || idesc->operands[i] == IA64_OPND_P2)
+ {
+ int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
+ qp_changemask |= (valueT) 1 << regno;
+ }
else if (idesc->operands[i] == IA64_OPND_PR)
- {
- if (idesc->operands[2] & (valueT)0x10000)
- qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
- else
- qp_changemask = idesc->operands[2];
- break;
- }
+ {
+ if (idesc->operands[2] & (valueT) 0x10000)
+ qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
+ else
+ qp_changemask = idesc->operands[2];
+ break;
+ }
else if (idesc->operands[i] == IA64_OPND_PR_ROT)
- {
- if (idesc->operands[1] & ((valueT)1 << 43))
- qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
- else
- qp_changemask = idesc->operands[1];
- qp_changemask &= ~(valueT)0xFFFF;
- break;
- }
+ {
+ if (idesc->operands[1] & ((valueT) 1 << 43))
+ qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
+ else
+ qp_changemask = idesc->operands[1];
+ qp_changemask &= ~(valueT) 0xFFFF;
+ break;
+ }
}
- /* Always clear qp branch flags on any PR change */
- /* FIXME there may be exceptions for certain compares */
+ /* Always clear qp branch flags on any PR change. */
+ /* FIXME there may be exceptions for certain compares. */
clear_qp_branch_flag (qp_changemask);
- /* invalidate rotating registers on insns which affect RRBs in CFM */
+ /* Invalidate rotating registers on insns which affect RRBs in CFM. */
if (idesc->flags & IA64_OPCODE_MOD_RRBS)
{
- qp_changemask |= ~(valueT)0xFFFF;
+ qp_changemask |= ~(valueT) 0xFFFF;
if (strcmp (idesc->name, "clrrrb.pr") != 0)
- {
- for (i=32;i < 32+md.rot.num_regs;i++)
- gr_values[i].known = 0;
- }
+ {
+ for (i = 32; i < 32 + md.rot.num_regs; i++)
+ gr_values[i].known = 0;
+ }
clear_qp_mutex (qp_changemask);
clear_qp_implies (qp_changemask, qp_changemask);
}
- /* after a call, all register values are undefined, except those marked
- as "safe" */
+ /* After a call, all register values are undefined, except those marked
+ as "safe". */
else if (strncmp (idesc->name, "br.call", 6) == 0
- || strncmp (idesc->name, "brl.call", 7) == 0)
+ || strncmp (idesc->name, "brl.call", 7) == 0)
{
- // FIXME keep GR values which are marked as "safe_across_calls"
+ /* FIXME keep GR values which are marked as "safe_across_calls" */
clear_register_values ();
clear_qp_mutex (~qp_safe_across_calls);
clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
clear_qp_branch_flag (~qp_safe_across_calls);
}
- /* Look for mutex and implies relations */
- else if ((idesc->operands[0] == IA64_OPND_P1
- || idesc->operands[0] == IA64_OPND_P2)
- && (idesc->operands[1] == IA64_OPND_P1
- || idesc->operands[1] == IA64_OPND_P2))
+ else if (is_interruption_or_rfi (idesc)
+ || is_taken_branch (idesc))
+ {
+ clear_register_values ();
+ clear_qp_mutex (~(valueT) 0);
+ clear_qp_implies (~(valueT) 0, ~(valueT) 0);
+ }
+ /* Look for mutex and implies relations. */
+ else if ((idesc->operands[0] == IA64_OPND_P1
+ || idesc->operands[0] == IA64_OPND_P2)
+ && (idesc->operands[1] == IA64_OPND_P1
+ || idesc->operands[1] == IA64_OPND_P2))
{
int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
- int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
- valueT p1mask = (valueT)1 << p1;
- valueT p2mask = (valueT)1 << p2;
+ int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
+ valueT p1mask = (valueT) 1 << p1;
+ valueT p2mask = (valueT) 1 << p2;
- /* if one of the PRs is PR0, we can't really do anything */
+ /* If one of the PRs is PR0, we can't really do anything. */
if (p1 == 0 || p2 == 0)
- {
- if (md.debug_dv)
- fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
- }
+ {
+ if (md.debug_dv)
+ fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
+ }
/* In general, clear mutexes and implies which include P1 or P2,
- with the following exceptions */
+ with the following exceptions. */
else if (strstr (idesc->name, ".or.andcm") != NULL)
- {
- add_qp_mutex (p1mask | p2mask);
- clear_qp_implies (p2mask, p1mask);
- }
+ {
+ add_qp_mutex (p1mask | p2mask);
+ clear_qp_implies (p2mask, p1mask);
+ }
else if (strstr (idesc->name, ".and.orcm") != NULL)
- {
- add_qp_mutex (p1mask | p2mask);
- clear_qp_implies (p1mask, p2mask);
- }
+ {
+ add_qp_mutex (p1mask | p2mask);
+ clear_qp_implies (p1mask, p2mask);
+ }
else if (strstr (idesc->name, ".and") != NULL)
- {
- clear_qp_implies (0, p1mask | p2mask);
- }
+ {
+ clear_qp_implies (0, p1mask | p2mask);
+ }
else if (strstr (idesc->name, ".or") != NULL)
- {
- clear_qp_mutex (p1mask | p2mask);
- clear_qp_implies (p1mask | p2mask, 0);
- }
+ {
+ clear_qp_mutex (p1mask | p2mask);
+ clear_qp_implies (p1mask | p2mask, 0);
+ }
else
- {
- clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
- if (strstr (idesc->name, ".unc") != NULL)
- {
- add_qp_mutex (p1mask | p2mask);
- if (CURR_SLOT.qp_regno != 0)
- {
- add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
- CURR_SLOT.qp_regno);
- add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
- CURR_SLOT.qp_regno);
- }
- }
- else if (CURR_SLOT.qp_regno == 0)
- {
- add_qp_mutex (p1mask | p2mask);
- }
- else
- {
- clear_qp_mutex (p1mask | p2mask);
- }
- }
+ {
+ clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
+ if (strstr (idesc->name, ".unc") != NULL)
+ {
+ add_qp_mutex (p1mask | p2mask);
+ if (CURR_SLOT.qp_regno != 0)
+ {
+ add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
+ CURR_SLOT.qp_regno);
+ add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
+ CURR_SLOT.qp_regno);
+ }
+ }
+ else if (CURR_SLOT.qp_regno == 0)
+ {
+ add_qp_mutex (p1mask | p2mask);
+ }
+ else
+ {
+ clear_qp_mutex (p1mask | p2mask);
+ }
+ }
}
- /* Look for mov imm insns into GRs */
+ /* Look for mov imm insns into GRs. */
else if (idesc->operands[0] == IA64_OPND_R1
- && (idesc->operands[1] == IA64_OPND_IMM22
- || idesc->operands[1] == IA64_OPND_IMMU64)
- && (strcmp(idesc->name, "mov") == 0
- || strcmp(idesc->name, "movl") == 0))
+ && (idesc->operands[1] == IA64_OPND_IMM22
+ || idesc->operands[1] == IA64_OPND_IMMU64)
+ && (strcmp (idesc->name, "mov") == 0
+ || strcmp (idesc->name, "movl") == 0))
{
int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
- if (regno > 0 && regno < NELEMS(gr_values))
- {
- gr_values[regno].known = 1;
- gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
- gr_values[regno].path = md.path;
- if (md.debug_dv)
- fprintf (stderr, " Know gr%d = 0x%llx\n",
- regno, gr_values[regno].value);
- }
+ if (regno > 0 && regno < NELEMS (gr_values))
+ {
+ gr_values[regno].known = 1;
+ gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
+ gr_values[regno].path = md.path;
+ if (md.debug_dv)
+ fprintf (stderr, " Know gr%d = 0x%llx\n",
+ regno, gr_values[regno].value);
+ }
}
- else
+ else
{
clear_qp_mutex (qp_changemask);
clear_qp_implies (qp_changemask, qp_changemask);
}
}
-/* Return whether the given predicate registers are currently mutex */
+/* Return whether the given predicate registers are currently mutex. */
+
static int
qp_mutex (p1, p2, path)
- int p1;
- int p2;
- int path;
+ int p1;
+ int p2;
+ int path;
{
int i;
valueT mask;
if (p1 != p2)
{
- mask = ((valueT)1<<p1) | (valueT)1<<p2;
- for (i=0;i < qp_mutexeslen;i++)
- {
- if (qp_mutexes[i].path >= path
- && (qp_mutexes[i].prmask & mask) == mask)
- return 1;
- }
+ mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
+ for (i = 0; i < qp_mutexeslen; i++)
+ {
+ if (qp_mutexes[i].path >= path
+ && (qp_mutexes[i].prmask & mask) == mask)
+ return 1;
+ }
}
return 0;
}
/* Return whether the given resource is in the given insn's list of chks
Return 1 if the conflict is absolutely determined, 2 if it's a potential
- conflict.
- */
+ conflict. */
+
static int
resources_match (rs, idesc, note, qp_regno, path)
- struct rsrc *rs;
- struct ia64_opcode *idesc;
- int note;
- int qp_regno;
- int path;
+ struct rsrc *rs;
+ struct ia64_opcode *idesc;
+ int note;
+ int qp_regno;
+ int path;
{
struct rsrc specs[MAX_SPECS];
int count;
/* If the marked resource's qp_regno and the given qp_regno are mutex,
we don't need to check. One exception is note 11, which indicates that
target predicates are written regardless of PR[qp]. */
- if (qp_mutex (rs->qp_regno, qp_regno, path)
+ if (qp_mutex (rs->qp_regno, qp_regno, path)
&& note != 11)
return 0;
{
/* UNAT checking is a bit more specific than other resources */
if (rs->dependency->specifier == IA64_RS_AR_UNAT
- && specs[count].mem_offset.hint
- && rs->mem_offset.hint)
- {
- if (rs->mem_offset.base == specs[count].mem_offset.base)
- {
- if (((rs->mem_offset.offset >> 3) & 0x3F) ==
- ((specs[count].mem_offset.offset >> 3) & 0x3F))
- return 1;
- else
- continue;
- }
- }
+ && specs[count].mem_offset.hint
+ && rs->mem_offset.hint)
+ {
+ if (rs->mem_offset.base == specs[count].mem_offset.base)
+ {
+ if (((rs->mem_offset.offset >> 3) & 0x3F) ==
+ ((specs[count].mem_offset.offset >> 3) & 0x3F))
+ return 1;
+ else
+ continue;
+ }
+ }
+
+ /* Skip apparent PR write conflicts where both writes are an AND or both
+ writes are an OR. */
+ if (rs->dependency->specifier == IA64_RS_PR
+ || rs->dependency->specifier == IA64_RS_PRr
+ || rs->dependency->specifier == IA64_RS_PR63)
+ {
+ if (specs[count].cmp_type != CMP_NONE
+ && specs[count].cmp_type == rs->cmp_type)
+ {
+ if (md.debug_dv)
+ fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
+ dv_mode[rs->dependency->mode],
+ rs->dependency->specifier != IA64_RS_PR63 ?
+ specs[count].index : 63);
+ continue;
+ }
+ if (md.debug_dv)
+ fprintf (stderr,
+ " %s on parallel compare conflict %s vs %s on PR%d\n",
+ dv_mode[rs->dependency->mode],
+ dv_cmp_type[rs->cmp_type],
+ dv_cmp_type[specs[count].cmp_type],
+ rs->dependency->specifier != IA64_RS_PR63 ?
+ specs[count].index : 63);
+
+ }
/* If either resource is not specific, conservatively assume a conflict
- */
+ */
if (!specs[count].specific || !rs->specific)
- return 2;
+ return 2;
else if (specs[count].index == rs->index)
- return 1;
+ return 1;
}
#if 0
if (md.debug_dv)
appropriately. If QP_REGNO is non-zero, only apply the break to resources
which use the same QP_REGNO and have the link_to_qp_branch flag set.
If SAVE_CURRENT is non-zero, don't affect resources marked by the current
- instruction.
-*/
+ instruction. */
static void
insn_group_break (insert_stop, qp_regno, save_current)
- int insert_stop;
- int qp_regno;
- int save_current;
+ int insert_stop;
+ int qp_regno;
+ int save_current;
{
int i;
if (md.debug_dv)
{
- fprintf (stderr, " Insn group break%s",
- (insert_stop ? " (w/stop)" : ""));
+ fprintf (stderr, " Insn group break%s",
+ (insert_stop ? " (w/stop)" : ""));
if (qp_regno != 0)
- fprintf (stderr, " effective for QP=%d", qp_regno);
+ fprintf (stderr, " effective for QP=%d", qp_regno);
fprintf (stderr, "\n");
}
const struct ia64_dependency *dep = regdeps[i].dependency;
if (qp_regno != 0
- && regdeps[i].qp_regno != qp_regno)
- {
- ++i;
- continue;
- }
+ && regdeps[i].qp_regno != qp_regno)
+ {
+ ++i;
+ continue;
+ }
if (save_current
- && CURR_SLOT.src_file == regdeps[i].file
- && CURR_SLOT.src_line == regdeps[i].line)
- {
- ++i;
- continue;
- }
+ && CURR_SLOT.src_file == regdeps[i].file
+ && CURR_SLOT.src_line == regdeps[i].line)
+ {
+ ++i;
+ continue;
+ }
/* clear dependencies which are automatically cleared by a stop, or
- those that have reached the appropriate state of insn serialization */
+ those that have reached the appropriate state of insn serialization */
if (dep->semantics == IA64_DVS_IMPLIED
- || dep->semantics == IA64_DVS_IMPLIEDF
- || regdeps[i].insn_srlz == STATE_SRLZ)
- {
- print_dependency ("Removing", i);
- regdeps[i] = regdeps[--regdepslen];
- }
+ || dep->semantics == IA64_DVS_IMPLIEDF
+ || regdeps[i].insn_srlz == STATE_SRLZ)
+ {
+ print_dependency ("Removing", i);
+ regdeps[i] = regdeps[--regdepslen];
+ }
else
- {
- if (dep->semantics == IA64_DVS_DATA
- || dep->semantics == IA64_DVS_INSTR
+ {
+ if (dep->semantics == IA64_DVS_DATA
+ || dep->semantics == IA64_DVS_INSTR
|| dep->semantics == IA64_DVS_SPECIFIC)
- {
- if (regdeps[i].insn_srlz == STATE_NONE)
- regdeps[i].insn_srlz = STATE_STOP;
- if (regdeps[i].data_srlz == STATE_NONE)
- regdeps[i].data_srlz = STATE_STOP;
- }
- ++i;
- }
+ {
+ if (regdeps[i].insn_srlz == STATE_NONE)
+ regdeps[i].insn_srlz = STATE_STOP;
+ if (regdeps[i].data_srlz == STATE_NONE)
+ regdeps[i].data_srlz = STATE_STOP;
+ }
+ ++i;
+ }
}
}
-/* Add the given resource usage spec to the list of active dependencies */
-static void
+/* Add the given resource usage spec to the list of active dependencies. */
+
+static void
mark_resource (idesc, dep, spec, depind, path)
- struct ia64_opcode *idesc;
- const struct ia64_dependency *dep;
- struct rsrc *spec;
- int depind;
- int path;
+ struct ia64_opcode *idesc;
+ const struct ia64_dependency *dep;
+ struct rsrc *spec;
+ int depind;
+ int path;
{
if (regdepslen == regdepstotlen)
{
regdepstotlen += 20;
regdeps = (struct rsrc *)
- xrealloc ((void *)regdeps,
- regdepstotlen * sizeof(struct rsrc));
+ xrealloc ((void *) regdeps,
+ regdepstotlen * sizeof(struct rsrc));
}
regdeps[regdepslen] = *spec;
static void
print_dependency (action, depind)
- const char *action;
- int depind;
+ const char *action;
+ int depind;
{
if (md.debug_dv)
{
- fprintf (stderr, " %s %s '%s'",
- action, dv_mode[(regdeps[depind].dependency)->mode],
- (regdeps[depind].dependency)->name);
+ fprintf (stderr, " %s %s '%s'",
+ action, dv_mode[(regdeps[depind].dependency)->mode],
+ (regdeps[depind].dependency)->name);
if (regdeps[depind].specific && regdeps[depind].index != 0)
- fprintf (stderr, " (%d)", regdeps[depind].index);
+ fprintf (stderr, " (%d)", regdeps[depind].index);
if (regdeps[depind].mem_offset.hint)
- fprintf (stderr, " 0x%llx+0x%llx",
- regdeps[depind].mem_offset.base,
- regdeps[depind].mem_offset.offset);
+ fprintf (stderr, " 0x%llx+0x%llx",
+ regdeps[depind].mem_offset.base,
+ regdeps[depind].mem_offset.offset);
fprintf (stderr, "\n");
}
}
int i;
if (md.debug_dv)
fprintf (stderr, " Instruction serialization\n");
- for (i=0;i < regdepslen;i++)
+ for (i = 0; i < regdepslen; i++)
if (regdeps[i].insn_srlz == STATE_STOP)
regdeps[i].insn_srlz = STATE_SRLZ;
}
while (i < regdepslen)
{
if (regdeps[i].data_srlz == STATE_STOP
- /* Note: as of 991210, all "other" dependencies are cleared by a
- data serialization. This might change with new tables */
- || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
- {
- print_dependency ("Removing", i);
- regdeps[i] = regdeps[--regdepslen];
- }
+ /* Note: as of 991210, all "other" dependencies are cleared by a
+ data serialization. This might change with new tables */
+ || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
+ {
+ print_dependency ("Removing", i);
+ regdeps[i] = regdeps[--regdepslen];
+ }
else
- ++i;
+ ++i;
}
}
-/* Insert stops and serializations as needed to avoid DVs */
+/* Insert stops and serializations as needed to avoid DVs. */
+
static void
remove_marked_resource (rs)
- struct rsrc *rs;
+ struct rsrc *rs;
{
switch (rs->dependency->semantics)
{
case IA64_DVS_SPECIFIC:
if (md.debug_dv)
fprintf (stderr, "Implementation-specific, assume worst case...\n");
- /* ...fall through... */
+ /* ...fall through... */
case IA64_DVS_INSTR:
if (md.debug_dv)
- fprintf (stderr, "Inserting instr serialization\n");
+ fprintf (stderr, "Inserting instr serialization\n");
if (rs->insn_srlz < STATE_STOP)
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
if (rs->insn_srlz < STATE_SRLZ)
- {
- int oldqp = CURR_SLOT.qp_regno;
- struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
- /* Manually jam a srlz.i insn into the stream */
- CURR_SLOT.qp_regno = 0;
- CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
- instruction_serialization ();
- md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
- if (++md.num_slots_in_use >= NUM_SLOTS)
- emit_one_bundle ();
- CURR_SLOT.qp_regno = oldqp;
- CURR_SLOT.idesc = oldidesc;
- }
+ {
+ int oldqp = CURR_SLOT.qp_regno;
+ struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+ /* Manually jam a srlz.i insn into the stream */
+ CURR_SLOT.qp_regno = 0;
+ CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
+ instruction_serialization ();
+ md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
+ if (++md.num_slots_in_use >= NUM_SLOTS)
+ emit_one_bundle ();
+ CURR_SLOT.qp_regno = oldqp;
+ CURR_SLOT.idesc = oldidesc;
+ }
insn_group_break (1, 0, 0);
break;
case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
- "other" types of DV are eliminated
- by a data serialization */
+ "other" types of DV are eliminated
+ by a data serialization */
case IA64_DVS_DATA:
if (md.debug_dv)
- fprintf (stderr, "Inserting data serialization\n");
+ fprintf (stderr, "Inserting data serialization\n");
if (rs->data_srlz < STATE_STOP)
- insn_group_break (1, 0, 0);
+ insn_group_break (1, 0, 0);
{
- int oldqp = CURR_SLOT.qp_regno;
- struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
- /* Manually jam a srlz.d insn into the stream */
- CURR_SLOT.qp_regno = 0;
- CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
- data_serialization ();
- md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
- if (++md.num_slots_in_use >= NUM_SLOTS)
- emit_one_bundle ();
- CURR_SLOT.qp_regno = oldqp;
- CURR_SLOT.idesc = oldidesc;
+ int oldqp = CURR_SLOT.qp_regno;
+ struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+ /* Manually jam a srlz.d insn into the stream */
+ CURR_SLOT.qp_regno = 0;
+ CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
+ data_serialization ();
+ md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
+ if (++md.num_slots_in_use >= NUM_SLOTS)
+ emit_one_bundle ();
+ CURR_SLOT.qp_regno = oldqp;
+ CURR_SLOT.idesc = oldidesc;
}
break;
case IA64_DVS_IMPLIED:
case IA64_DVS_IMPLIEDF:
if (md.debug_dv)
- fprintf (stderr, "Inserting stop\n");
+ fprintf (stderr, "Inserting stop\n");
insn_group_break (1, 0, 0);
break;
default:
}
/* Check the resources used by the given opcode against the current dependency
- list.
+ list.
The check is run once for each execution path encountered. In this case,
a unique execution path is the sequence of instructions following a code
entry point, e.g. the following has three execution paths, one starting
at L0, one at L1, and one at L2.
-
+
L0: nop
L1: add
L2: add
- br.ret
+ br.ret
*/
+
static void
check_dependencies (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
int path;
int i;
/* Note that the number of marked resources may change within the
- loop if in auto mode. */
+ loop if in auto mode. */
i = 0;
while (i < regdepslen)
{
int start_over = 0;
if (dep->semantics == IA64_DVS_NONE
- || (chkind = depends_on (rs->depind, idesc)) == -1)
- {
- ++i; continue;
- }
+ || (chkind = depends_on (rs->depind, idesc)) == -1)
+ {
+ ++i;
+ continue;
+ }
- note = NOTE(opdeps->chks[chkind]);
+ note = NOTE (opdeps->chks[chkind]);
- /* Check this resource against each execution path seen thus far */
- for (path=0;path <= md.path;path++)
- {
- int matchtype;
-
- /* If the dependency wasn't on the path being checked, ignore it */
- if (rs->path < path)
- continue;
-
- /* If the QP for this insn implies a QP which has branched, don't
- bother checking. Ed. NOTE: I don't think this check is terribly
- useful; what's the point of generating code which will only be
- reached if its QP is zero?
- This code was specifically inserted to handle the following code,
- based on notes from Intel's DV checking code, where p1 implies p2.
-
- mov r4 = 2
- (p2) br.cond L
- (p1) mov r4 = 7
-
- */
- if (CURR_SLOT.qp_regno != 0)
- {
- int skip = 0;
- int implies;
- for (implies=0;implies < qp_implieslen;implies++)
- {
- if (qp_implies[implies].path >= path
- && qp_implies[implies].p1 == CURR_SLOT.qp_regno
- && qp_implies[implies].p2_branched)
- {
- skip = 1;
- break;
- }
- }
- if (skip)
- continue;
- }
-
- if ((matchtype = resources_match (rs, idesc, note,
- CURR_SLOT.qp_regno, path)) != 0)
- {
- char msg[1024];
- char pathmsg[256] = "";
- char indexmsg[256] = "";
- int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
-
- if (path != 0)
- sprintf (pathmsg, " when entry is at label '%s'",
- md.entry_labels[path-1]);
- if (rs->specific && rs->index != 0)
- sprintf (indexmsg, ", specific resource number is %d",
- rs->index);
- sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
- idesc->name,
- (certain ? "violates" : "may violate"),
- dv_mode[dep->mode], dep->name,
- dv_sem[dep->semantics],
- pathmsg, indexmsg);
-
- if (md.explicit_mode)
- {
- as_warn ("%s", msg);
- if (path < md.path)
- as_warn (_("Only the first path encountering the conflict "
- "is reported"));
- as_warn_where (rs->file, rs->line,
- _("This is the location of the "
- "conflicting usage"));
- /* Don't bother checking other paths, to avoid duplicating
- the same warning */
- break;
- }
- else
- {
- if (md.debug_dv)
- fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
-
- remove_marked_resource (rs);
-
- /* since the set of dependencies has changed, start over */
- /* FIXME -- since we're removing dvs as we go, we
- probably don't really need to start over... */
- start_over = 1;
- break;
- }
- }
- }
+ /* Check this resource against each execution path seen thus far. */
+ for (path = 0; path <= md.path; path++)
+ {
+ int matchtype;
+
+ /* If the dependency wasn't on the path being checked, ignore it. */
+ if (rs->path < path)
+ continue;
+
+ /* If the QP for this insn implies a QP which has branched, don't
+ bother checking. Ed. NOTE: I don't think this check is terribly
+ useful; what's the point of generating code which will only be
+ reached if its QP is zero?
+ This code was specifically inserted to handle the following code,
+ based on notes from Intel's DV checking code, where p1 implies p2.
+
+ mov r4 = 2
+ (p2) br.cond L
+ (p1) mov r4 = 7
+ */
+ if (CURR_SLOT.qp_regno != 0)
+ {
+ int skip = 0;
+ int implies;
+ for (implies = 0; implies < qp_implieslen; implies++)
+ {
+ if (qp_implies[implies].path >= path
+ && qp_implies[implies].p1 == CURR_SLOT.qp_regno
+ && qp_implies[implies].p2_branched)
+ {
+ skip = 1;
+ break;
+ }
+ }
+ if (skip)
+ continue;
+ }
+
+ if ((matchtype = resources_match (rs, idesc, note,
+ CURR_SLOT.qp_regno, path)) != 0)
+ {
+ char msg[1024];
+ char pathmsg[256] = "";
+ char indexmsg[256] = "";
+ int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
+
+ if (path != 0)
+ sprintf (pathmsg, " when entry is at label '%s'",
+ md.entry_labels[path - 1]);
+ if (rs->specific && rs->index != 0)
+ sprintf (indexmsg, ", specific resource number is %d",
+ rs->index);
+ sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
+ idesc->name,
+ (certain ? "violates" : "may violate"),
+ dv_mode[dep->mode], dep->name,
+ dv_sem[dep->semantics],
+ pathmsg, indexmsg);
+
+ if (md.explicit_mode)
+ {
+ as_warn ("%s", msg);
+ if (path < md.path)
+ as_warn (_("Only the first path encountering the conflict "
+ "is reported"));
+ as_warn_where (rs->file, rs->line,
+ _("This is the location of the "
+ "conflicting usage"));
+ /* Don't bother checking other paths, to avoid duplicating
+ the same warning */
+ break;
+ }
+ else
+ {
+ if (md.debug_dv)
+ fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
+
+ remove_marked_resource (rs);
+
+ /* since the set of dependencies has changed, start over */
+ /* FIXME -- since we're removing dvs as we go, we
+ probably don't really need to start over... */
+ start_over = 1;
+ break;
+ }
+ }
+ }
if (start_over)
- i = 0;
+ i = 0;
else
- ++i;
+ ++i;
}
}
-/* register new dependencies based on the given opcode */
+/* Register new dependencies based on the given opcode. */
+
static void
mark_resources (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
int i;
const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
/* A conditional branch only uses its resources if it is taken; if it is
taken, we stop following that path. The other branch types effectively
*always* write their resources. If it's not taken, register only QP
- reads. */
+ reads. */
if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
{
add_only_qp_reads = 1;
if (md.debug_dv)
fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
- for (i=0;i < opdeps->nregs;i++)
+ for (i = 0; i < opdeps->nregs; i++)
{
const struct ia64_dependency *dep;
struct rsrc specs[MAX_SPECS];
int note;
int path;
int count;
-
+
dep = ia64_find_dependency (opdeps->regs[i]);
- note = NOTE(opdeps->regs[i]);
+ note = NOTE (opdeps->regs[i]);
if (add_only_qp_reads
- && !(dep->mode == IA64_DV_WAR
- && (dep->specifier == IA64_RS_PR
- || dep->specifier == IA64_RS_PR63)))
- continue;
+ && !(dep->mode == IA64_DV_WAR
+ && (dep->specifier == IA64_RS_PR
+ || dep->specifier == IA64_RS_PRr
+ || dep->specifier == IA64_RS_PR63)))
+ continue;
count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
#if 0
if (md.debug_dv && !count)
- fprintf (stderr, " No %s %s usage found (path %d)\n",
- dv_mode[dep->mode], dep->name, md.path);
+ fprintf (stderr, " No %s %s usage found (path %d)\n",
+ dv_mode[dep->mode], dep->name, md.path);
#endif
-
+
while (count-- > 0)
- {
- mark_resource (idesc, dep, &specs[count],
- DEP(opdeps->regs[i]), md.path);
- }
+ {
+ mark_resource (idesc, dep, &specs[count],
+ DEP (opdeps->regs[i]), md.path);
+ }
/* The execution path may affect register values, which may in turn
- affect which indirect-access resources are accessed. */
+ affect which indirect-access resources are accessed. */
switch (dep->specifier)
- {
- default:
- break;
- case IA64_RS_CPUID:
- case IA64_RS_DBR:
- case IA64_RS_IBR:
+ {
+ default:
+ break;
+ case IA64_RS_CPUID:
+ case IA64_RS_DBR:
+ case IA64_RS_IBR:
case IA64_RS_MSR:
- case IA64_RS_PKR:
- case IA64_RS_PMC:
- case IA64_RS_PMD:
- case IA64_RS_RR:
- for (path=0;path < md.path;path++)
- {
- count = specify_resource (dep, idesc, DV_REG, specs, note, path);
- while (count-- > 0)
- mark_resource (idesc, dep, &specs[count],
- DEP(opdeps->regs[i]), path);
- }
- break;
- }
+ case IA64_RS_PKR:
+ case IA64_RS_PMC:
+ case IA64_RS_PMD:
+ case IA64_RS_RR:
+ for (path = 0; path < md.path; path++)
+ {
+ count = specify_resource (dep, idesc, DV_REG, specs, note, path);
+ while (count-- > 0)
+ mark_resource (idesc, dep, &specs[count],
+ DEP (opdeps->regs[i]), path);
+ }
+ break;
+ }
}
}
-/* remove dependencies when they no longer apply */
+/* Remove dependencies when they no longer apply. */
+
static void
update_dependencies (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
int i;
data_serialization ();
}
else if (is_interruption_or_rfi (idesc)
- || is_taken_branch (idesc))
+ || is_taken_branch (idesc))
{
- /* although technically the taken branch doesn't clear dependencies
- which require a srlz.[id], we don't follow the branch; the next
- instruction is assumed to start with a clean slate */
+ /* Although technically the taken branch doesn't clear dependencies
+ which require a srlz.[id], we don't follow the branch; the next
+ instruction is assumed to start with a clean slate. */
regdepslen = 0;
- clear_register_values ();
- clear_qp_mutex (~(valueT)0);
- clear_qp_implies (~(valueT)0, ~(valueT)0);
md.path = 0;
}
else if (is_conditional_branch (idesc)
- && CURR_SLOT.qp_regno != 0)
+ && CURR_SLOT.qp_regno != 0)
{
int is_call = strstr (idesc->name, ".call") != NULL;
- for (i=0;i < qp_implieslen;i++)
- {
- /* if the conditional branch's predicate is implied by the predicate
- in an existing dependency, remove that dependency */
- if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
- {
- int depind = 0;
- /* note that this implied predicate takes a branch so that if
- a later insn generates a DV but its predicate implies this
- one, we can avoid the false DV warning */
- qp_implies[i].p2_branched = 1;
- while (depind < regdepslen)
- {
- if (regdeps[depind].qp_regno == qp_implies[i].p1)
- {
- print_dependency ("Removing", depind);
- regdeps[depind] = regdeps[--regdepslen];
- }
- else
- ++depind;
- }
- }
- }
+ for (i = 0; i < qp_implieslen; i++)
+ {
+ /* If the conditional branch's predicate is implied by the predicate
+ in an existing dependency, remove that dependency. */
+ if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
+ {
+ int depind = 0;
+ /* Note that this implied predicate takes a branch so that if
+ a later insn generates a DV but its predicate implies this
+ one, we can avoid the false DV warning. */
+ qp_implies[i].p2_branched = 1;
+ while (depind < regdepslen)
+ {
+ if (regdeps[depind].qp_regno == qp_implies[i].p1)
+ {
+ print_dependency ("Removing", depind);
+ regdeps[depind] = regdeps[--regdepslen];
+ }
+ else
+ ++depind;
+ }
+ }
+ }
/* Any marked resources which have this same predicate should be
- cleared, provided that the QP hasn't been modified between the
- marking instruction and the branch.
- */
+ cleared, provided that the QP hasn't been modified between the
+ marking instruction and the branch. */
if (is_call)
- {
- insn_group_break (0, CURR_SLOT.qp_regno, 1);
- }
+ {
+ insn_group_break (0, CURR_SLOT.qp_regno, 1);
+ }
else
- {
- i = 0;
- while (i < regdepslen)
- {
- if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
- && regdeps[i].link_to_qp_branch
- && (regdeps[i].file != CURR_SLOT.src_file
- || regdeps[i].line != CURR_SLOT.src_line))
- {
- /* Treat like a taken branch */
- print_dependency ("Removing", i);
- regdeps[i] = regdeps[--regdepslen];
- }
- else
- ++i;
- }
- }
+ {
+ i = 0;
+ while (i < regdepslen)
+ {
+ if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
+ && regdeps[i].link_to_qp_branch
+ && (regdeps[i].file != CURR_SLOT.src_file
+ || regdeps[i].line != CURR_SLOT.src_line))
+ {
+ /* Treat like a taken branch */
+ print_dependency ("Removing", i);
+ regdeps[i] = regdeps[--regdepslen];
+ }
+ else
+ ++i;
+ }
+ }
}
}
/* Examine the current instruction for dependency violations. */
+
static int
check_dv (idesc)
- struct ia64_opcode *idesc;
+ struct ia64_opcode *idesc;
{
if (md.debug_dv)
{
- fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
- idesc->name, CURR_SLOT.src_line,
- idesc->dependencies->nchks,
- idesc->dependencies->nregs);
+ fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
+ idesc->name, CURR_SLOT.src_line,
+ idesc->dependencies->nchks,
+ idesc->dependencies->nregs);
}
- /* Look through the list of currently marked resources; if the current
+ /* Look through the list of currently marked resources; if the current
instruction has the dependency in its chks list which uses that resource,
- check against the specific resources used.
- */
+ check against the specific resources used. */
check_dependencies (idesc);
- /*
- Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
- then add them to the list of marked resources.
- */
+ /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
+ then add them to the list of marked resources. */
mark_resources (idesc);
/* There are several types of dependency semantics, and each has its own
- requirements for being cleared
-
+ requirements for being cleared
+
Instruction serialization (insns separated by interruption, rfi, or
writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
update_dependencies (idesc);
/* Sometimes, knowing a register value allows us to avoid giving a false DV
- warning. Keep track of as many as possible that are useful. */
+ warning. Keep track of as many as possible that are useful. */
note_register_values (idesc);
- /* We don't need or want this anymore. */
+ /* We don't need or want this anymore. */
md.mem_offset.hint = 0;
return 0;
saved_input_line_pointer = input_line_pointer;
input_line_pointer = str;
- /* extract the opcode (mnemonic): */
+ /* extract the opcode (mnemonic): */
mnemonic = input_line_pointer;
ch = get_symbol_end ();
goto done;
}
- /* find the instruction descriptor matching the arguments: */
+ /* Find the instruction descriptor matching the arguments. */
idesc = ia64_find_opcode (mnemonic);
*input_line_pointer = ch;
if (!idesc)
goto done;
- /* Handle the dynamic ops we can handle now: */
+ /* Handle the dynamic ops we can handle now: */
if (idesc->type == IA64_TYPE_DYN)
{
if (strcmp (idesc->name, "add") == 0)
mnemonic = "addl";
else
mnemonic = "adds";
+ ia64_free_opcode (idesc);
idesc = ia64_find_opcode (mnemonic);
#if 0
know (!idesc->next);
mnemonic = "mov.i";
else
mnemonic = "mov.m";
+ ia64_free_opcode (idesc);
idesc = ia64_find_opcode (mnemonic);
while (idesc != NULL
&& (idesc->operands[0] != opnd1
qp_regno = 0;
if (md.qp.X_op == O_register)
- qp_regno = md.qp.X_add_number - REG_P;
+ {
+ qp_regno = md.qp.X_add_number - REG_P;
+ md.qp.X_op = O_absent;
+ }
flags = idesc->flags;
goto done;
}
- /* build the instruction: */
+ /* Build the instruction. */
CURR_SLOT.qp_regno = qp_regno;
CURR_SLOT.idesc = idesc;
as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
dwarf2_where (&CURR_SLOT.debug_line);
/* Add unwind entry, if there is one. */
- if (current_unwind_entry)
+ if (unwind.current_entry)
{
- CURR_SLOT.unwind_record = current_unwind_entry;
- current_unwind_entry = NULL;
+ CURR_SLOT.unwind_record = unwind.current_entry;
+ unwind.current_entry = NULL;
}
- /* check for dependency violations */
+ /* Check for dependency violations. */
if (md.detect_dv)
- check_dv(idesc);
+ check_dv (idesc);
md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
if (++md.num_slots_in_use >= NUM_SLOTS)
/* Called when symbol NAME cannot be found in the symbol table.
Should be used for dynamic valued symbols only. */
-symbolS*
+
+symbolS *
md_undefined_symbol (name)
char *name;
{
/* Called for any expression that can not be recognized. When the
function is called, `input_line_pointer' will point to the start of
the expression. */
+
void
md_operand (e)
expressionS *e;
{
enum pseudo_type pseudo_type;
+ const char *name;
size_t len;
int ch, i;
switch (*input_line_pointer)
{
case '@':
- /* find what relocation pseudo-function we're dealing with: */
+ /* Find what relocation pseudo-function we're dealing with. */
pseudo_type = 0;
ch = *++input_line_pointer;
for (i = 0; i < NELEMS (pseudo_func); ++i)
as_bad ("Expected '('");
goto err;
}
- ++input_line_pointer; /* skip '(' */
+ /* Skip '('. */
+ ++input_line_pointer;
expression (e);
if (*input_line_pointer++ != ')')
{
goto err;
}
}
- /* make sure gas doesn't get rid of local symbols that are used
- in relocs: */
+ /* Make sure gas doesn't get rid of local symbols that are used
+ in relocs. */
e->X_op = O_pseudo_fixup;
e->X_op_symbol = pseudo_func[i].u.sym;
break;
e->X_add_number = pseudo_func[i].u.ival;
break;
+ case PSEUDO_FUNC_REG:
+ e->X_op = O_register;
+ e->X_add_number = pseudo_func[i].u.ival;
+ break;
+
default:
- as_bad ("Unknown pseudo function `%s'", input_line_pointer - 1);
+ name = input_line_pointer - 1;
+ get_symbol_end ();
+ as_bad ("Unknown pseudo function `%s'", name);
goto err;
}
break;
segT sec;
{
unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
-
+
if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
off &= ~0xfUL;
/* Return the actual relocation we wish to associate with the pseudo
reloc described by SYM and R_TYPE. SYM should be one of the
- symbols in the pseudo_func array, or NULL. */
+ symbols in the pseudo_func array, or NULL. */
static bfd_reloc_code_real_type
ia64_gen_real_reloc_type (sym, r_type)
t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
- md_number_to_chars (fixpos + 0, t0, 8);
- md_number_to_chars (fixpos + 8, t1, 8);
+ number_to_chars_littleendian (fixpos + 0, t0, 8);
+ number_to_chars_littleendian (fixpos + 8, t1, 8);
}
/* Attempt to simplify or even eliminate a fixup. The return value is
To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
- (if possible). */
+ (if possible). */
int
md_apply_fix3 (fix, valuep, seg)
fixS *fix;
}
/* ??? This is a hack copied from tc-i386.c to make PCREL relocs
- work. There should be a better way to handle this. */
+ work. There should be a better way to handle this. */
if (adjust)
fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
}
/* Generate the BFD reloc to be stuck in the object file from the
fixup used internally in the assembler. */
-arelent*
+
+arelent *
tc_gen_reloc (sec, fixp)
asection *sec;
fixS *fixp;
}
/* Turn a string in input_line_pointer into a floating point constant
- of type type, and store the appropriate bytes in *lit. The number
- of LITTLENUMS emitted is stored in *size. An error message is
+ of type TYPE, and store the appropriate bytes in *LIT. The number
+ of LITTLENUMS emitted is stored in *SIZE. An error message is
returned, or NULL on OK. */
#define MAX_LITTLENUMS 5
-char*
+char *
md_atof (type, lit, size)
int type;
char *lit;
valueT size;
{
int align = bfd_get_section_alignment (stdoutput, seg);
- valueT mask = ((valueT)1 << align) - 1;
+ valueT mask = ((valueT) 1 << align) - 1;
return (size + mask) & ~mask;
}
static const unsigned char le_nop[]
= { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
-
+
/* Make sure we are on a 16-byte boundary, in case someone has been
putting data into a text section. */
frag_align (4, 0, 0);
projects / deliverable / binutils-gdb.git / blobdiff