/* tc-m68k.c -- Assemble for the m68k family
- Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
+ Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#include "opcode/m68k.h"
#include "m68k-parse.h"
-/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful */
+/* This string holds the chars that always start a comment. If the
+ pre-processor is disabled, these aren't very useful. The macro
+ tc_comment_chars points to this. We use this, rather than the
+ usual comment_chars, so that the --bitwise-or option will work. */
#if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
-const char comment_chars[] = "|#";
+const char *m68k_comment_chars = "|#";
#else
-const char comment_chars[] = "|";
+const char *m68k_comment_chars = "|";
#endif
/* This array holds the chars that only start a comment at the beginning of
be 32 bits. */
static int m68k_rel32 = 1;
+/* This is non-zero if m68k_rel32 was set from the command line. */
+static int m68k_rel32_from_cmdline;
+
+/* The default width to use for an index register when using a base
+ displacement. */
+static enum m68k_size m68k_index_width_default = SIZE_LONG;
+
+/* We want to warn if any text labels are misaligned. In order to get
+ the right line number, we need to record the line number for each
+ label. */
+
+struct label_line
+{
+ struct label_line *next;
+ symbolS *label;
+ char *file;
+ unsigned int line;
+ int text;
+};
+
+/* The list of labels. */
+
+static struct label_line *labels;
+
+/* The current label. */
+
+static struct label_line *current_label;
+
/* Its an arbitrary name: This means I don't approve of it */
/* See flames below */
static struct obstack robyn;
USP, VBR, URP, SRP, PCR,
0
};
+static const enum m68k_register mcf5200_control_regs[] = {
+ CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
+ RAMBAR0, RAMBAR1, MBAR,
+ 0
+};
#define cpu32_control_regs m68010_control_regs
static const enum m68k_register *control_regs;
reloc[5]; /* Five is enough??? */
};
-#define cpu_of_arch(x) ((x) & m68000up)
+#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
#define float_of_arch(x) ((x) & mfloat)
#define mmu_of_arch(x) ((x) & mmmu)
int pc_rel;
int pc_fix;
{
- the_ins.reloc[the_ins.nrel].n = (((width)=='B')
+ the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
? (the_ins.numo*2-1)
: (((width)=='b')
? (the_ins.numo*2+1)
{ cpu32, "cpu32", 0 },
{ m68881, "68881", 0 },
{ m68851, "68851", 0 },
+ { mcf5200, "5200", 0 },
/* Aliases (effectively, so far as gas is concerned) for the above
cpus. */
{ m68020, "68k", 1 },
{ m68020, "68ec020", 1 },
{ m68030, "68ec030", 1 },
{ m68040, "68ec040", 1 },
+ { m68060, "68ec060", 1 },
{ cpu32, "68330", 1 },
{ cpu32, "68331", 1 },
{ cpu32, "68332", 1 },
abort ();
if (fixp->fx_r_type != BFD_RELOC_NONE)
- code = fixp->fx_r_type;
+ {
+ code = fixp->fx_r_type;
+
+ /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
+ that fixup_segment converted a non-PC relative reloc into a
+ PC relative reloc. In such a case, we need to convert the
+ reloc code. */
+ if (fixp->fx_pcrel)
+ {
+ switch (code)
+ {
+ case BFD_RELOC_8:
+ code = BFD_RELOC_8_PCREL;
+ break;
+ case BFD_RELOC_16:
+ code = BFD_RELOC_16_PCREL;
+ break;
+ case BFD_RELOC_32:
+ code = BFD_RELOC_32_PCREL;
+ break;
+ case BFD_RELOC_8_PCREL:
+ case BFD_RELOC_16_PCREL:
+ case BFD_RELOC_32_PCREL:
+ case BFD_RELOC_8_GOT_PCREL:
+ case BFD_RELOC_16_GOT_PCREL:
+ case BFD_RELOC_32_GOT_PCREL:
+ case BFD_RELOC_8_GOTOFF:
+ case BFD_RELOC_16_GOTOFF:
+ case BFD_RELOC_32_GOTOFF:
+ case BFD_RELOC_8_PLT_PCREL:
+ case BFD_RELOC_16_PLT_PCREL:
+ case BFD_RELOC_32_PLT_PCREL:
+ case BFD_RELOC_8_PLTOFF:
+ case BFD_RELOC_16_PLTOFF:
+ case BFD_RELOC_32_PLTOFF:
+ break;
+ default:
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ "Cannot make %s relocation PC relative",
+ bfd_get_reloc_code_name (code));
+ }
+ }
+ }
else
{
#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
#else
if (!fixp->fx_pcrel)
reloc->addend = fixp->fx_addnumber;
- else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
+ else
reloc->addend = (section->vma
+ (fixp->fx_pcrel_adjust == 64
? -1 : fixp->fx_pcrel_adjust)
+ fixp->fx_addnumber
+ md_pcrel_from (fixp));
- else
- reloc->addend = (fixp->fx_offset
- + (fixp->fx_pcrel_adjust == 64
- ? -1 : fixp->fx_pcrel_adjust));
#endif
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
/* If we didn't get the right number of ops, or we have no
common model with this pattern then reject this pattern. */
+ ok_arch |= opcode->m_arch;
if (opsfound != opcode->m_opnum
|| ((opcode->m_arch & current_architecture) == 0))
- {
- ++losing;
- ok_arch |= opcode->m_arch;
- }
+ ++losing;
else
{
for (s = opcode->m_operands, opP = &the_ins.operands[0];
}
break;
+ case '<':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case FPREG:
+ case CONTROL:
+ case IMMED:
+ case ADEC:
+ case REGLST:
+ losing++;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case '>':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case FPREG:
+ case CONTROL:
+ case IMMED:
+ case AINC:
+ case REGLST:
+ losing++;
+ break;
+ case ABSL:
+ break;
+ default:
+ if (opP->reg == PC
+ || opP->reg == ZPC)
+ losing++;
+ break;
+ }
+ break;
+
+ case 'm':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'n':
+ switch (opP->mode)
+ {
+ case DISP:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'o':
+ switch (opP->mode)
+ {
+ case BASE:
+ case ABSL:
+ case IMMED:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'p':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ case DISP:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
case '#':
if (opP->mode != IMMED)
losing++;
&& (opP->disp.exp.X_op != O_constant
|| ! isbyte (opP->disp.exp.X_add_number)))
losing++;
+ else if (s[1] == 'B'
+ && ! isvar (&opP->disp)
+ && (opP->disp.exp.X_op != O_constant
+ || ! issbyte (opP->disp.exp.X_add_number)))
+ losing++;
else if (s[1] == 'w'
&& ! isvar (&opP->disp)
&& (opP->disp.exp.X_op != O_constant
break;
case 'O':
- if (opP->mode != DREG && opP->mode != IMMED)
+ if (opP->mode != DREG
+ && opP->mode != IMMED
+ && opP->mode != ABSL)
losing++;
break;
&& !(ok_arch & current_architecture))
{
char buf[200], *cp;
- int len;
+
strcpy (buf,
"invalid instruction for this architecture; needs ");
cp = buf + strlen (buf);
}
}
}
- len = cp - buf + 1;
- cp = malloc (len);
+ cp = xmalloc (strlen (buf) + 1);
strcpy (cp, buf);
the_ins.error = cp;
}
case '?':
case '/':
case '`':
+ case '<':
+ case '>':
+ case 'm':
+ case 'n':
+ case 'o':
+ case 'p':
#ifndef NO_68851
case '|':
#endif
&& cpu_of_arch (current_architecture) >= m68020)
|| opP->disp.size == SIZE_LONG)))
{
+ if (cpu_of_arch (current_architecture) < m68020)
+ opP->error =
+ "displacement too large for this architecture; needs 68020 or higher";
if (opP->reg == PC)
tmpreg = 0x3B; /* 7.3 */
else
{
nextword |= (opP->index.reg - DATA) << 12;
- if (opP->index.size == SIZE_UNSPEC
- || opP->index.size == SIZE_LONG)
+ if (opP->index.size == SIZE_LONG
+ || (opP->index.size == SIZE_UNSPEC
+ && m68k_index_width_default == SIZE_LONG))
nextword |= 0x800;
- if (cpu_of_arch (current_architecture) < m68020)
+ if ((opP->index.scale != 1
+ && cpu_of_arch (current_architecture) < m68020)
+ || (opP->index.scale == 8
+ && current_architecture == mcf5200))
{
- if (opP->index.scale != 1)
- {
- opP->error =
- "scale factor invalid on this architecture; needs 68020 or higher";
- }
+ opP->error =
+ "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
}
switch (opP->index.scale)
#endif
)
{
+ /* The code in md_convert_frag_1 needs to be
+ able to adjust nextword. Call frag_grow
+ to ensure that we have enough space in
+ the frag obstack to make all the bytes
+ contiguous. */
+ frag_grow (14);
nextword += baseo & 0xff;
addword (nextword);
add_frag (adds (&opP->disp), offs (&opP->disp),
/* Figure out innner displacement stuff */
if (opP->mode == POST || opP->mode == PRE)
{
+ if (cpu_of_arch (current_architecture) & cpu32)
+ opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
switch (siz2)
{
case SIZE_UNSPEC:
the_ins.reloc[the_ins.nrel - 1].n =
(opcode->m_codenum) * 2 + 1;
break;
+ case 'B':
+ if (!issbyte (tmpreg))
+ opP->error = "out of range";
+ opcode->m_opcode |= tmpreg;
+ if (isvar (&opP->disp))
+ the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
+ break;
case 'w':
if (!isword (tmpreg))
opP->error = "out of range";
case PCR:
tmpreg = 0x808;
break;
+ case ROMBAR:
+ tmpreg = 0xC00;
+ break;
+ case RAMBAR0:
+ tmpreg = 0xC04;
+ break;
+ case RAMBAR1:
+ tmpreg = 0xC05;
+ break;
+ case MBAR:
+ tmpreg = 0xC0F;
+ break;
default:
abort ();
}
{ "ccr", CCR },
{ "cc", CCR },
- { "usp", USP },
- { "isp", ISP },
- { "sfc", SFC },
+ /* control registers */
+ { "sfc", SFC }, /* Source Function Code */
{ "sfcr", SFC },
- { "dfc", DFC },
+ { "dfc", DFC }, /* Destination Function Code */
{ "dfcr", DFC },
- { "cacr", CACR },
- { "caar", CAAR },
-
- { "vbr", VBR },
-
- { "msp", MSP },
- { "itt0", ITT0 },
- { "itt1", ITT1 },
- { "dtt0", DTT0 },
- { "dtt1", DTT1 },
- { "mmusr", MMUSR },
- { "tc", TC },
- { "srp", SRP },
- { "urp", URP },
+ { "cacr", CACR }, /* Cache Control Register */
+ { "caar", CAAR }, /* Cache Address Register */
+
+ { "usp", USP }, /* User Stack Pointer */
+ { "vbr", VBR }, /* Vector Base Register */
+ { "msp", MSP }, /* Master Stack Pointer */
+ { "isp", ISP }, /* Interrupt Stack Pointer */
+
+ { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
+ { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
+ { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
+ { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
+
+ /* 68ec040 versions of same */
+ { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
+ { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
+ { "dacr0", DTT0 }, /* Data Access Control Register 0 */
+ { "dacr1", DTT1 }, /* Data Access Control Register 0 */
+
+ /* mcf5200 versions of same. The ColdFire programmer's reference
+ manual indicated that the order is 2,3,0,1, but Ken Rose
+ <rose@netcom.com> says that 0,1,2,3 is the correct order. */
+ { "acr0", ITT0 }, /* Access Control Unit 0 */
+ { "acr1", ITT1 }, /* Access Control Unit 1 */
+ { "acr2", DTT0 }, /* Access Control Unit 2 */
+ { "acr3", DTT1 }, /* Access Control Unit 3 */
+
+ { "tc", TC }, /* MMU Translation Control Register */
+ { "tcr", TC },
+
+ { "mmusr", MMUSR }, /* MMU Status Register */
+ { "srp", SRP }, /* User Root Pointer */
+ { "urp", URP }, /* Supervisor Root Pointer */
+
{ "buscr", BUSCR },
{ "pcr", PCR },
+ { "rombar", ROMBAR }, /* ROM Base Address Register */
+ { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
+ { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
+ { "mbar", MBAR }, /* Module Base Address Register */
+ /* end of control registers */
+
{ "ac", AC },
{ "bc", BC },
{ "cal", CAL },
return;
}
+ /* If there is a current label, record that it marks an instruction. */
+ if (current_label != NULL)
+ {
+ current_label->text = 1;
+ current_label = NULL;
+ }
+
if (the_ins.nfrag == 0)
{
/* No frag hacking involved; just put it out */
n = 1;
break;
case '3':
- n = 2;
+ n = 1;
break;
case 'w':
n = 2;
get_reloc_code (n, the_ins.reloc[m].pcrel,
the_ins.reloc[m].pic_reloc));
fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
+ if (the_ins.reloc[m].wid == 'B')
+ fixP->fx_signed = 1;
}
return;
}
{
flag_reg_prefix_optional = 1;
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
op_hash = hash_new ();
*/
alt_notend_table['@'] = 1;
+ /* We need to put digits in alt_notend_table to handle
+ bfextu %d0{24:1},%d0
+ */
+ alt_notend_table['0'] = 1;
+ alt_notend_table['1'] = 1;
+ alt_notend_table['2'] = 1;
+ alt_notend_table['3'] = 1;
+ alt_notend_table['4'] = 1;
+ alt_notend_table['5'] = 1;
+ alt_notend_table['6'] = 1;
+ alt_notend_table['7'] = 1;
+ alt_notend_table['8'] = 1;
+ alt_notend_table['9'] = 1;
+
#ifndef MIT_SYNTAX_ONLY
/* Insert pseudo ops, these have to go into the opcode table since
gas expects pseudo ops to start with a dot */
#endif
}
+static void
+select_control_regs ()
+{
+ /* Note which set of "movec" control registers is available. */
+ switch (cpu_of_arch (current_architecture))
+ {
+ case m68000:
+ control_regs = m68000_control_regs;
+ break;
+ case m68010:
+ control_regs = m68010_control_regs;
+ break;
+ case m68020:
+ case m68030:
+ control_regs = m68020_control_regs;
+ break;
+ case m68040:
+ control_regs = m68040_control_regs;
+ break;
+ case m68060:
+ control_regs = m68060_control_regs;
+ break;
+ case cpu32:
+ control_regs = cpu32_control_regs;
+ break;
+ case mcf5200:
+ control_regs = mcf5200_control_regs;
+ break;
+ default:
+ abort ();
+ }
+}
+
void
m68k_init_after_args ()
{
#endif
/* Note which set of "movec" control registers is available. */
- switch (cpu_of_arch (current_architecture))
- {
- case m68000:
- control_regs = m68000_control_regs;
- break;
- case m68010:
- control_regs = m68010_control_regs;
- break;
- case m68020:
- case m68030:
- control_regs = m68020_control_regs;
- break;
- case m68040:
- control_regs = m68040_control_regs;
- break;
- case m68060:
- control_regs = m68060_control_regs;
- break;
- case cpu32:
- control_regs = cpu32_control_regs;
- break;
- default:
- abort ();
- }
+ select_control_regs ();
if (cpu_of_arch (current_architecture) < m68020)
md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
}
+\f
+/* This is called when a label is defined. */
+void
+m68k_frob_label (sym)
+ symbolS *sym;
+{
+ struct label_line *n;
+
+ n = (struct label_line *) xmalloc (sizeof *n);
+ n->next = labels;
+ n->label = sym;
+ as_where (&n->file, &n->line);
+ labels = n;
+ current_label = n;
+}
+
+/* This is called when a value that is not an instruction is emitted. */
+
+void
+m68k_flush_pending_output ()
+{
+ current_label = NULL;
+}
+
+/* This is called at the end of the assembly, when the final value of
+ the label is known. We warn if this is a text symbol aligned at an
+ odd location. */
+
+void
+m68k_frob_symbol (sym)
+ symbolS *sym;
+{
+ if ((S_GET_VALUE (sym) & 1) != 0)
+ {
+ struct label_line *l;
+
+ for (l = labels; l != NULL; l = l->next)
+ {
+ if (l->label == sym)
+ {
+ if (l->text)
+ as_warn_where (l->file, l->line,
+ "text label `%s' aligned to odd boundary",
+ S_GET_NAME (sym));
+ break;
+ }
+ }
+ }
+}
+\f
/* This is called if we go in or out of MRI mode because of the .mri
pseudo-op. */
#endif
}
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
else
{
#endif
}
m68k_abspcadd = 0;
- m68k_rel32 = 1;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 1;
}
}
like "0xff" for a byte field. So extend the upper part of the range
to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
so that we can do any range checking at all. */
- if (!fixP->fx_pcrel)
+ if (! fixP->fx_pcrel && ! fixP->fx_signed)
upper_limit = upper_limit * 2 + 1;
if ((addressT) val > upper_limit
{
case TAB (BCC68000, BYTE):
case TAB (ABRANCH, BYTE):
- /* We can't do a short jump to the next instruction, so we force
- word mode. At this point S_GET_VALUE should return the
- offset of the symbol within its frag. If the symbol is at
- the start of a frag, and it is the next frag with any data in
- it (usually this just the next frag, but assembler listings
- may introduce empty frags), we must use word mode. */
+ /* We can't do a short jump to the next instruction, so in that
+ case we force word mode. At this point S_GET_VALUE should
+ return the offset of the symbol within its frag. If the
+ symbol is at the start of a frag, and it is the next frag
+ with any data in it (usually this is just the next frag, but
+ assembler listings may introduce empty frags), we must use
+ word mode. */
if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
{
fragS *l;
if (!need_pass_2) /* Never make frag if expect extra pass. */
frag_align (temp, (int) temp_fill);
demand_empty_rest_of_line ();
+ record_alignment (now_seg, temp);
}
static void
\f
/* Pseudo-ops handled for MRI compatibility. */
+/* This function returns non-zero if the argument is a conditional
+ pseudo-op. This is called when checking whether a pending
+ alignment is needed. */
+
+int
+m68k_conditional_pseudoop (pop)
+ pseudo_typeS *pop;
+{
+ return (pop->poc_handler == s_mri_if
+ || pop->poc_handler == s_mri_else);
+}
+
/* Handle an MRI style chip specification. */
static void
current_architecture |= m68851;
*input_line_pointer = c;
}
+
+ /* Update info about available control registers. */
+ select_control_regs ();
}
/* The MRI CHIP pseudo-op. */
* -pic Indicates PIC.
* -k Indicates PIC. (Sun 3 only.)
*
+ * --bitwise-or
+ * Permit `|' to be used in expressions.
+ *
*/
#ifdef OBJ_ELF
#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
{"register-prefix-optional", no_argument, NULL,
OPTION_REGISTER_PREFIX_OPTIONAL},
+#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
+ {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
+#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
+ {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
+#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
+ {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
+#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
+ {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
+#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
+ {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof(md_longopts);
case 'Q':
break;
+ case OPTION_BITWISE_OR:
+ {
+ char *n, *t;
+ const char *s;
+
+ n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
+ t = n;
+ for (s = m68k_comment_chars; *s != '\0'; s++)
+ if (*s != '|')
+ *t++ = *s;
+ *t = '\0';
+ m68k_comment_chars = n;
+ }
+ break;
+
+ case OPTION_BASE_SIZE_DEFAULT_16:
+ m68k_index_width_default = SIZE_WORD;
+ break;
+
+ case OPTION_BASE_SIZE_DEFAULT_32:
+ m68k_index_width_default = SIZE_LONG;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_16:
+ m68k_rel32 = 0;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_32:
+ m68k_rel32 = 1;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
default:
return 0;
}
-l use 1 word for refs to undefined symbols [default 2]\n\
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
| -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
- | -mcpu32\n\
+ | -mcpu32 | -m5200\n\
specify variant of 680X0 architecture [default 68020]\n\
-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
target has/lacks floating-point coprocessor\n\
-pic, -k generate position independent code\n\
-S turn jbsr into jsr\n\
--register-prefix-optional\n\
- recognize register names without prefix character\n");
+ recognize register names without prefix character\n\
+--bitwise-or do not treat `|' as a comment character\n");
+ fprintf (stream, "\
+--base-size-default-16 base reg without size is 16 bits\n\
+--base-size-default-32 base reg without size is 32 bits (default)\n\
+--disp-size-default-16 displacement with unknown size is 16 bits\n\
+--disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
}
\f
#ifdef TEST2
projects / deliverable / binutils-gdb.git / blobdiff