/* tc-m68k.c -- Assemble for the m68k family
- Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#include "opcode/m68k.h"
#include "m68k-parse.h"
+#if defined (OBJ_ELF)
+#include "elf/m68k.h"
+#endif
+
/* This string holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. The macro
tc_comment_chars points to this. We use this, rather than the
usual comment_chars, so that the --bitwise-or option will work. */
-#if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
+#if defined (TE_SVR4) || defined (TE_DELTA)
const char *m68k_comment_chars = "|#";
#else
const char *m68k_comment_chars = "|";
.line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
-/* Also note that comments like this one will always work. */
-const char line_comment_chars[] = "#";
+ #NO_APP at the beginning of its output. */
+/* Also note that comments like this one will always work. */
+const char line_comment_chars[] = "#*";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums */
CONST char EXP_CHARS[] = "eE";
/* Are we trying to generate PIC code? If so, absolute references
ought to be made into linkage table references or pc-relative
- references. Not implemented. For ELF there are other means
+ references. Not implemented. For ELF there are other means
to denote pic relocations. */
int flag_want_pic;
static int flag_short_refs; /* -l option */
static int flag_long_jumps; /* -S option */
+static int flag_keep_pcrel; /* --pcrel option. */
#ifdef REGISTER_PREFIX_OPTIONAL
int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
be 32 bits. */
static int m68k_rel32 = 1;
+/* This is non-zero if m68k_rel32 was set from the command line. */
+static int m68k_rel32_from_cmdline;
+
+/* The default width to use for an index register when using a base
+ displacement. */
+static enum m68k_size m68k_index_width_default = SIZE_LONG;
+
+/* We want to warn if any text labels are misaligned. In order to get
+ the right line number, we need to record the line number for each
+ label. */
+
+struct label_line
+{
+ struct label_line *next;
+ symbolS *label;
+ char *file;
+ unsigned int line;
+ int text;
+};
+
+/* The list of labels. */
+
+static struct label_line *labels;
+
+/* The current label. */
+
+static struct label_line *current_label;
+
/* Its an arbitrary name: This means I don't approve of it */
/* See flames below */
static struct obstack robyn;
-#define TAB(x,y) (((x)<<2)+(y))
-#define TABTYPE(xy) ((xy) >> 2)
-#define BYTE 0
-#define SHORT 1
-#define LONG 2
-#define SZ_UNDEF 3
-#undef BRANCH
-/* Case `g' except when BCC68000 is applicable. */
-#define ABRANCH 1
-/* Coprocessor branches. */
-#define FBRANCH 2
-/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
- supported on all cpus. Widens to 32-bit absolute. */
-#define PCREL 3
-/* For inserting an extra jmp instruction with long offset on 68000,
- for expanding conditional branches. (Not bsr or bra.) Since the
- 68000 doesn't support 32-bit displacements for conditional
- branches, we fake it by reversing the condition and branching
- around a jmp with an absolute long operand. */
-#define BCC68000 4
-/* For the DBcc "instructions". If the displacement requires 32 bits,
- the branch-around-a-jump game is played here too. */
-#define DBCC 5
-/* Not currently used? */
-#define PCLEA 6
-/* Mode AINDX (apc-relative) using PC, with variable target, might fit
- in 16 or 8 bits. */
-#define PCINDEX 7
-
struct m68k_incant
{
const char *m_operands;
USP, VBR, URP, SRP, PCR,
0
};
-static const enum m68k_register mcf5200_control_regs[] = {
- CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
+static const enum m68k_register mcf_control_regs[] = {
+ CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
RAMBAR0, RAMBAR1, MBAR,
0
};
{
int fragoff; /* Where in the current opcode the frag ends */
symbolS *fadd;
- long foff;
+ offsetT foff;
int fragty;
}
fragb[4];
reloc[5]; /* Five is enough??? */
};
-#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
+#define cpu_of_arch(x) ((x) & (m68000up|mcf))
#define float_of_arch(x) ((x) & mfloat)
#define mmu_of_arch(x) ((x) & mmmu)
+#define arch_coldfire_p(x) (((x) & mcf) != 0)
+
+/* Macros for determining if cpu supports a specific addressing mode */
+#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
static struct m68k_it the_ins; /* the instruction being assembled */
#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
+/* Static functions. */
+
+static void insop PARAMS ((int, const struct m68k_incant *));
+static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
+static void add_frag PARAMS ((symbolS *, offsetT, int));
+
/* Like addword, but goes BEFORE general operands */
static void
insop (w, opcode)
int w;
- struct m68k_incant *opcode;
+ const struct m68k_incant *opcode;
{
int z;
for(z=the_ins.numo;z>opcode->m_codenum;--z)
Blecch. */
static void
add_fix (width, exp, pc_rel, pc_fix)
- char width;
+ int width;
struct m68k_exp *exp;
int pc_rel;
int pc_fix;
{
- the_ins.reloc[the_ins.nrel].n = (((width)=='B')
+ the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
? (the_ins.numo*2-1)
: (((width)=='b')
? (the_ins.numo*2+1)
ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
static void
-add_frag(add,off,type)
+add_frag (add, off, type)
symbolS *add;
- long off;
+ offsetT off;
int type;
{
the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
static int get_num PARAMS ((struct m68k_exp *exp, int ok));
+static void m68k_ip PARAMS ((char *));
+static void insert_reg PARAMS ((const char *, int));
+static void select_control_regs PARAMS ((void));
+static void init_regtable PARAMS ((void));
static int reverse_16_bits PARAMS ((int in));
static int reverse_8_bits PARAMS ((int in));
static void install_gen_operand PARAMS ((int mode, int val));
static void s_mri_until PARAMS ((int));
static void s_mri_while PARAMS ((int));
static void s_mri_endw PARAMS ((int));
+static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
+static void md_convert_frag_1 PARAMS ((fragS *));
static int current_architecture;
-struct m68k_cpu {
- unsigned long arch;
- const char *name;
- int alias;
-};
+struct m68k_cpu
+ {
+ unsigned long arch;
+ const char *name;
+ int alias;
+ };
-static const struct m68k_cpu archs[] = {
- { m68000, "68000", 0 },
- { m68010, "68010", 0 },
- { m68020, "68020", 0 },
- { m68030, "68030", 0 },
- { m68040, "68040", 0 },
- { m68060, "68060", 0 },
- { cpu32, "cpu32", 0 },
- { m68881, "68881", 0 },
- { m68851, "68851", 0 },
- { mcf5200, "5200", 0 },
- /* Aliases (effectively, so far as gas is concerned) for the above
- cpus. */
- { m68020, "68k", 1 },
- { m68000, "68302", 1 },
- { m68000, "68008", 1 },
- { m68000, "68ec000", 1 },
- { m68000, "68hc000", 1 },
- { m68000, "68hc001", 1 },
- { m68020, "68ec020", 1 },
- { m68030, "68ec030", 1 },
- { m68040, "68ec040", 1 },
- { m68060, "68ec060", 1 },
- { cpu32, "68330", 1 },
- { cpu32, "68331", 1 },
- { cpu32, "68332", 1 },
- { cpu32, "68333", 1 },
- { cpu32, "68340", 1 },
- { cpu32, "68360", 1 },
- { m68881, "68882", 1 },
-};
+static const struct m68k_cpu archs[] =
+ {
+ { m68000, "68000", 0 },
+ { m68010, "68010", 0 },
+ { m68020, "68020", 0 },
+ { m68030, "68030", 0 },
+ { m68040, "68040", 0 },
+ { m68060, "68060", 0 },
+ { cpu32, "cpu32", 0 },
+ { m68881, "68881", 0 },
+ { m68851, "68851", 0 },
+ { mcf5200, "5200", 0 },
+ { mcf5206e, "5206e", 0 },
+ { mcf5307, "5307", 0},
+ { mcf5407, "5407", 0},
+ /* Aliases (effectively, so far as gas is concerned) for the above
+ cpus. */
+ { m68020, "68k", 1 },
+ { m68000, "68008", 1 },
+ { m68000, "68302", 1 },
+ { m68000, "68306", 1 },
+ { m68000, "68307", 1 },
+ { m68000, "68322", 1 },
+ { m68000, "68356", 1 },
+ { m68000, "68ec000", 1 },
+ { m68000, "68hc000", 1 },
+ { m68000, "68hc001", 1 },
+ { m68020, "68ec020", 1 },
+ { m68030, "68ec030", 1 },
+ { m68040, "68ec040", 1 },
+ { m68060, "68ec060", 1 },
+ { cpu32, "68330", 1 },
+ { cpu32, "68331", 1 },
+ { cpu32, "68332", 1 },
+ { cpu32, "68333", 1 },
+ { cpu32, "68334", 1 },
+ { cpu32, "68336", 1 },
+ { cpu32, "68340", 1 },
+ { cpu32, "68341", 1 },
+ { cpu32, "68349", 1 },
+ { cpu32, "68360", 1 },
+ { m68881, "68882", 1 },
+ { mcf5200, "5202", 1 },
+ { mcf5200, "5204", 1 },
+ { mcf5200, "5206", 1 },
+ };
static const int n_archs = sizeof (archs) / sizeof (archs[0]);
-/* BCC68000 is for patching in an extra jmp instruction for long offsets
- on the 68000. The 68000 doesn't support long branches with branchs */
+/* This is the assembler relaxation table for m68k. m68k is a rich CISC
+ architecture and we have a lot of relaxation modes. */
+
+/* Macros used in the relaxation code. */
+#define TAB(x,y) (((x) << 2) + (y))
+#define TABTYPE(x) ((x) >> 2)
+
+/* Relaxation states. */
+#define BYTE 0
+#define SHORT 1
+#define LONG 2
+#define SZ_UNDEF 3
-/* This table desribes how you change sizes for the various types of variable
- size expressions. This version only supports two kinds. */
+/* Here are all the relaxation modes we support. First we can relax ordinary
+ branches. On 68020 and higher and on CPU32 all branch instructions take
+ three forms, so on these CPUs all branches always remain as such. When we
+ have to expand to the LONG form on a 68000, though, we substitute an
+ absolute jump instead. This is a direct replacement for unconditional
+ branches and a branch over a jump for conditional branches. However, if the
+ user requires PIC and disables this with --pcrel, we can only relax between
+ BYTE and SHORT forms, punting if that isn't enough. This gives us four
+ different relaxation modes for branches: */
+
+#define BRANCHBWL 1 /* branch byte, word, or long */
+#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
+#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
+#define BRANCHBW 4 /* branch byte or word */
+
+/* We also relax coprocessor branches and DBcc's. All CPUs that support
+ coprocessor branches support them in word and long forms, so we have only
+ one relaxation mode for them. DBcc's are word only on all CPUs. We can
+ relax them to the LONG form with a branch-around sequence. This sequence
+ can use a long branch (if available) or an absolute jump (if acceptable).
+ This gives us two relaxation modes. If long branches are not available and
+ absolute jumps are not acceptable, we don't relax DBcc's. */
+
+#define FBRANCH 5 /* coprocessor branch */
+#define DBCCLBR 6 /* DBcc relaxable with a long branch */
+#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
+
+/* That's all for instruction relaxation. However, we also relax PC-relative
+ operands. Specifically, we have three operand relaxation modes. On the
+ 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
+ on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
+ two. Also PC+displacement+index operands in their simple form (with a non-
+ suppressed index without memory indirection) are supported on all CPUs, but
+ on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
+ and on CPU32 we relax it to SHORT and LONG forms as well using the extended
+ form of the PC+displacement+index operand. Finally, some absolute operands
+ can be relaxed down to 16-bit PC-relative. */
+
+#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
+#define PCINDEX 9 /* PC+displacement+index */
+#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
/* Note that calls to frag_var need to specify the maximum expansion
needed; this is currently 10 bytes for DBCC. */
{1, 1, 0, 0}, /* that the VAX doesn't either */
{1, 1, 0, 0},
- {(127), (-128), 0, TAB (ABRANCH, SHORT)},
- {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
+ {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
+ {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
{0, 0, 4, 0},
{1, 1, 0, 0},
- {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
- {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
+ {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
+ {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
{0, 0, 4, 0},
{1, 1, 0, 0},
- {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
- {(32767), (-32768), 2, TAB (PCREL, LONG)},
+ {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
+ {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
+ {0, 0, 6, 0},
+ {1, 1, 0, 0},
+
+ {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
+ {0, 0, 2, 0},
+ {1, 1, 0, 0},
+ {1, 1, 0, 0},
+
+ {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
+ {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
{0, 0, 4, 0},
{1, 1, 0, 0},
- {(127), (-128), 0, TAB (BCC68000, SHORT)},
- {(32767), (-32768), 2, TAB (BCC68000, LONG)},
- {0, 0, 6, 0}, /* jmp long space */
+ {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
+ {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
+ {0, 0, 10, 0},
{1, 1, 0, 0},
{1, 1, 0, 0}, /* DBCC doesn't come BYTE */
- {(32767), (-32768), 2, TAB (DBCC, LONG)},
- {0, 0, 10, 0}, /* bra/jmp long space */
+ {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
+ {0, 0, 10, 0},
{1, 1, 0, 0},
- {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
- {32767, -32768, 2, TAB (PCLEA, LONG)},
+ {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
+ {32767, -32768, 2, TAB (PCREL1632, LONG)},
{0, 0, 6, 0},
{1, 1, 0, 0},
- /* For, e.g., jmp pcrel indexed. */
{125, -130, 0, TAB (PCINDEX, SHORT)},
{32765, -32770, 2, TAB (PCINDEX, LONG)},
{0, 0, 4, 0},
{1, 1, 0, 0},
+
+ {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
+ {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
+ {0, 0, 4, 0},
+ {1, 1, 0, 0},
};
/* These are the machine dependent pseudo-ops. These are included so
{0, 0, 0}
};
-
/* The mote pseudo ops are put into the opcode table, since they
don't start with a . they look like opcodes to gas.
*/
-extern void obj_coff_section ();
+
+#ifdef M68KCOFF
+extern void obj_coff_section PARAMS ((int));
+#endif
CONST pseudo_typeS mote_pseudo_table[] =
{
extern char *input_line_pointer;
static char mklower_table[256];
-#define mklower(c) (mklower_table[(unsigned char)(c)])
+#define mklower(c) (mklower_table[(unsigned char) (c)])
static char notend_table[256];
static char alt_notend_table[256];
#define notend(s) \
opcode[1] = 0xb9;
}
else
- as_fatal ("Unknown PC relative instruction");
+ as_fatal (_("Unknown PC relative instruction"));
*add_number -= 4;
return 0;
}
}
}
- as_bad ("Can not do %d byte %s%srelocation", size,
- pcrel ? "pc-relative " : "",
- pic == pic_none ? "" : "pic ");
+ if (pcrel)
+ {
+ if (pic == pic_none)
+ as_bad (_("Can not do %d byte pc-relative relocation"), size);
+ else
+ as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
+ }
+ else
+ {
+ if (pic == pic_none)
+ as_bad (_("Can not do %d byte relocation"), size);
+ else
+ as_bad (_("Can not do %d byte pic relocation"), size);
+ }
+
return BFD_RELOC_NONE;
}
tc_m68k_fix_adjustable (fixP)
fixS *fixP;
{
- /* Prevent all adjustments to global symbols. */
- if (S_IS_EXTERNAL (fixP->fx_addsy))
+ /* Prevent all adjustments to global symbols. */
+ if (S_IS_EXTERNAL (fixP->fx_addsy)
+ || S_IS_WEAK (fixP->fx_addsy))
return 0;
/* adjust_reloc_syms doesn't know about the GOT */
case BFD_RELOC_32_PLTOFF:
return 0;
+ case BFD_RELOC_VTABLE_INHERIT:
+ case BFD_RELOC_VTABLE_ENTRY:
+ return 0;
+
default:
return 1;
}
arelent *reloc;
bfd_reloc_code_real_type code;
+ /* If the tcbit is set, then this was a fixup of a negative value
+ that was never resolved. We do not have a reloc to handle this,
+ so just return. We assume that other code will have detected this
+ situation and produced a helpful error message, so we just tell the
+ user that the reloc cannot be produced. */
if (fixp->fx_tcbit)
- abort ();
+ {
+ if (fixp->fx_addsy)
+ as_bad (_("Unable to produce reloc against symbol '%s'"),
+ S_GET_NAME (fixp->fx_addsy));
+ return NULL;
+ }
if (fixp->fx_r_type != BFD_RELOC_NONE)
{
break;
default:
as_bad_where (fixp->fx_file, fixp->fx_line,
- "Cannot make %s relocation PC relative",
+ _("Cannot make %s relocation PC relative"),
bfd_get_reloc_code_name (code));
}
}
#undef F
#undef MAP
- reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
- assert (reloc != 0);
- reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
+ reloc = (arelent *) xmalloc (sizeof (arelent));
+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
#ifndef OBJ_ELF
if (fixp->fx_pcrel)
#endif /* BFD_ASSEMBLER */
+/* Return zero if the reference to SYMBOL from within the same segment may
+ be relaxed. */
+#ifdef OBJ_ELF
+
+/* On an ELF system, we can't relax an externally visible symbol,
+ because it may be overridden by a shared library. However, if
+ TARGET_OS is "elf", then we presume that we are assembling for an
+ embedded system, in which case we don't have to worry about shared
+ libraries, and we can relax anything. */
+
+#define relaxable_symbol(symbol) \
+ (strcmp (TARGET_OS, "elf") == 0 \
+ || (! S_IS_EXTERNAL (symbol) \
+ && ! S_IS_WEAK (symbol)))
+
+#else
+
+#define relaxable_symbol(symbol) 1
+
+#endif
+
/* Handle of the OPCODE hash table. NULL means any use before
m68k_ip_begin() will crash. */
static struct hash_control *op_hash;
\f
/* Assemble an m68k instruction. */
-void
+static void
m68k_ip (instring)
char *instring;
{
register char *p;
register struct m68k_op *opP;
- register struct m68k_incant *opcode;
+ register const struct m68k_incant *opcode;
register const char *s;
register int tmpreg = 0, baseo = 0, outro = 0, nextword;
char *pdot, *pdotmove;
char c;
int losing;
int opsfound;
- char *crack_operand ();
LITTLENUM_TYPE words[6];
LITTLENUM_TYPE *wordp;
unsigned long ok_arch = 0;
instring++; /* skip leading whitespace */
/* Scan up to end of operation-code, which MUST end in end-of-string
- or exactly 1 space. */
+ or exactly 1 space. */
pdot = 0;
for (p = instring; *p != '\0'; p++)
{
if (p == instring)
{
- the_ins.error = "No operator";
+ the_ins.error = _("No operator");
return;
}
c = *p;
*p = '\0';
- opcode = (struct m68k_incant *) hash_find (op_hash, instring);
+ opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
*p = c;
if (pdot != NULL)
if (opcode == NULL)
{
- the_ins.error = "Unknown operator";
+ the_ins.error = _("Unknown operator");
return;
}
for (losing = 0;;)
{
/* If we didn't get the right number of ops, or we have no
- common model with this pattern then reject this pattern. */
+ common model with this pattern then reject this pattern. */
+ ok_arch |= opcode->m_arch;
if (opsfound != opcode->m_opnum
|| ((opcode->m_arch & current_architecture) == 0))
- {
- ++losing;
- ok_arch |= opcode->m_arch;
- }
+ ++losing;
else
{
for (s = opcode->m_operands, opP = &the_ins.operands[0];
}
break;
- case '`':
+ case '<':
switch (opP->mode)
{
+ case DREG:
+ case AREG:
+ case FPREG:
+ case CONTROL:
case IMMED:
+ case ADEC:
+ case REGLST:
+ losing++;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case '>':
+ switch (opP->mode)
+ {
case DREG:
case AREG:
case FPREG:
case CONTROL:
+ case IMMED:
case AINC:
case REGLST:
+ losing++;
+ break;
+ case ABSL:
+ break;
+ default:
+ if (opP->reg == PC
+ || opP->reg == ZPC)
+ losing++;
+ break;
+ }
+ break;
+
+ case 'm':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'n':
+ switch (opP->mode)
+ {
+ case DISP:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'o':
+ switch (opP->mode)
+ {
+ case BASE:
+ case ABSL:
+ case IMMED:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'p':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'q':
+ switch (opP->mode)
+ {
+ case DREG:
case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
+ default:
losing++;
break;
+ }
+ break;
+
+ case 'v':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ case ABSL:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
default:
+ losing++;
break;
}
break;
&& (opP->disp.exp.X_op != O_constant
|| ! isbyte (opP->disp.exp.X_add_number)))
losing++;
+ else if (s[1] == 'B'
+ && ! isvar (&opP->disp)
+ && (opP->disp.exp.X_op != O_constant
+ || ! issbyte (opP->disp.exp.X_add_number)))
+ losing++;
else if (s[1] == 'w'
&& ! isvar (&opP->disp)
&& (opP->disp.exp.X_op != O_constant
losing++;
break;
+ case 'E':
+ if (opP->reg != ACC)
+ losing++;
+ break;
+
case 'F':
if (opP->mode != FPREG)
losing++;
break;
+ case 'G':
+ if (opP->reg != MACSR)
+ losing++;
+ break;
+
+ case 'H':
+ if (opP->reg != MASK)
+ losing++;
+ break;
+
case 'I':
if (opP->mode != CONTROL
|| opP->reg < COP0
opP->mode = REGLST;
}
}
- else if (opP->mode == ABSL
- && opP->disp.size == SIZE_UNSPEC
- && opP->disp.exp.X_op == O_constant)
- {
- /* This is what the MRI REG pseudo-op generates. */
- opP->mode = REGLST;
- opP->mask = opP->disp.exp.X_add_number;
- }
else if (opP->mode != REGLST)
losing++;
else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
&& opP->reg != BC))
{
losing++;
- } /* not a cache specifier. */
+ } /* not a cache specifier. */
break;
case '_':
++losing;
break;
+ case 'u':
+ if (opP->reg < DATA0L || opP->reg > ADDR7U)
+ losing++;
+ /* FIXME: kludge instead of fixing parser:
+ upper/lower registers are *not* CONTROL
+ registers, but ordinary ones. */
+ if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
+ || (opP->reg >= DATA0U && opP->reg <= DATA7U))
+ opP->mode = DREG;
+ else
+ opP->mode = AREG;
+ break;
+
default:
abort ();
} /* switch on type of operand */
if (!losing)
{
break;
- } /* got it. */
+ } /* got it. */
opcode = opcode->m_next;
&& !(ok_arch & current_architecture))
{
char buf[200], *cp;
- int len;
+
strcpy (buf,
- "invalid instruction for this architecture; needs ");
+ _("invalid instruction for this architecture; needs "));
cp = buf + strlen (buf);
switch (ok_arch)
{
case mfloat:
- strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
+ strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
break;
case mmmu:
- strcpy (cp, "mmu (68030 or 68851)");
+ strcpy (cp, _("mmu (68030 or 68851)"));
break;
case m68020up:
- strcpy (cp, "68020 or higher");
+ strcpy (cp, _("68020 or higher"));
break;
case m68000up:
- strcpy (cp, "68000 or higher");
+ strcpy (cp, _("68000 or higher"));
break;
case m68010up:
- strcpy (cp, "68010 or higher");
+ strcpy (cp, _("68010 or higher"));
break;
default:
{
int got_one = 0, idx;
- for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
+ for (idx = 0;
+ idx < (int) (sizeof (archs) / sizeof (archs[0]));
idx++)
{
if ((archs[idx].arch & ok_arch)
}
}
}
- len = cp - buf + 1;
- cp = malloc (len);
+ cp = xmalloc (strlen (buf) + 1);
strcpy (cp, buf);
the_ins.error = cp;
}
else
- the_ins.error = "operands mismatch";
+ the_ins.error = _("operands mismatch");
return;
} /* Fell off the end */
case '$':
case '?':
case '/':
- case '`':
+ case '<':
+ case '>':
+ case 'm':
+ case 'n':
+ case 'o':
+ case 'p':
+ case 'q':
+ case 'v':
#ifndef NO_68851
case '|':
#endif
{
case 'b':
if (!isbyte (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
case 'w':
if (!isword (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
case 'W':
if (!issword (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
{
if (offs (&opP->disp) > baseo)
{
- as_warn ("Bignum too big for %c format; truncated",
+ as_warn (_("Bignum too big for %c format; truncated"),
s[1]);
offs (&opP->disp) = baseo;
}
|| (isvar (&opP->disp)
&& ((opP->disp.size == SIZE_UNSPEC
&& flag_short_refs == 0
- && cpu_of_arch (current_architecture) >= m68020)
+ && cpu_of_arch (current_architecture) >= m68020
+ && ! arch_coldfire_p (current_architecture))
|| opP->disp.size == SIZE_LONG)))
{
- if (cpu_of_arch (current_architecture) < m68020)
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
opP->error =
- "displacement too large for this architecture; needs 68020 or higher";
+ _("displacement too large for this architecture; needs 68020 or higher");
if (opP->reg == PC)
tmpreg = 0x3B; /* 7.3 */
else
{
add_frag (adds (&opP->disp),
offs (&opP->disp),
- TAB (PCLEA, SZ_UNDEF));
+ TAB (PCREL1632, SZ_UNDEF));
break;
}
}
{
nextword |= (opP->index.reg - DATA) << 12;
- if (opP->index.size == SIZE_UNSPEC
- || opP->index.size == SIZE_LONG)
+ if (opP->index.size == SIZE_LONG
+ || (opP->index.size == SIZE_UNSPEC
+ && m68k_index_width_default == SIZE_LONG))
nextword |= 0x800;
- if ((opP->index.scale != 1
+ if ((opP->index.scale != 1
&& cpu_of_arch (current_architecture) < m68020)
- || (opP->index.scale == 8
- && current_architecture == mcf5200))
+ || (opP->index.scale == 8
+ && arch_coldfire_p (current_architecture)))
{
opP->error =
- "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
+ _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
}
+ if (arch_coldfire_p (current_architecture)
+ && opP->index.size == SIZE_WORD)
+ opP->error = _("invalid index size for coldfire");
+
switch (opP->index.scale)
{
case 1:
{
if (siz1 == SIZE_BYTE
|| cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture)
|| (siz1 == SIZE_UNSPEC
&& ! isvar (&opP->disp)
&& issbyte (baseo)))
else if (siz1 != SIZE_BYTE)
{
if (siz1 != SIZE_UNSPEC)
- as_warn ("Forcing byte displacement");
+ as_warn (_("Forcing byte displacement"));
if (! issbyte (baseo))
- opP->error = "byte displacement out of range";
+ opP->error = _("byte displacement out of range");
}
break;
#endif
)
{
+ /* The code in md_convert_frag_1 needs to be
+ able to adjust nextword. Call frag_grow
+ to ensure that we have enough space in
+ the frag obstack to make all the bytes
+ contiguous. */
+ frag_grow (14);
nextword += baseo & 0xff;
addword (nextword);
add_frag (adds (&opP->disp), offs (&opP->disp),
/* It isn't simple. */
- if (cpu_of_arch (current_architecture) < m68020)
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
opP->error =
- "invalid operand mode for this architecture; needs 68020 or higher";
+ _("invalid operand mode for this architecture; needs 68020 or higher");
nextword |= 0x100;
/* If the guy specified a width, we assume that it is
}
break;
case SIZE_BYTE:
- as_warn (":b not permitted; defaulting to :w");
+ as_warn (_(":b not permitted; defaulting to :w"));
/* Fall through. */
case SIZE_WORD:
nextword |= 0x20;
if (opP->mode == POST || opP->mode == PRE)
{
if (cpu_of_arch (current_architecture) & cpu32)
- opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
+ opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
switch (siz2)
{
case SIZE_UNSPEC:
}
break;
case 1:
- as_warn (":b not permitted; defaulting to :w");
+ as_warn (_(":b not permitted; defaulting to :w"));
/* Fall through. */
case 2:
nextword |= 0x2;
addword (nextword);
break;
}
- /* Don't generate pc relative code on 68010 and
- 68000. */
if (isvar (&opP->disp)
&& !subs (&opP->disp)
&& adds (&opP->disp)
cannot be relaxed. */
&& opP->disp.pic_reloc == pic_none
#endif
- && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
- && cpu_of_arch (current_architecture) >= m68020
&& !flag_long_jumps
&& !strchr ("~%&$?", s[0]))
{
tmpreg = 0x3A; /* 7.2 */
add_frag (adds (&opP->disp),
offs (&opP->disp),
- TAB (PCREL, SZ_UNDEF));
+ TAB (ABSTOPCREL, SZ_UNDEF));
break;
}
/* Fall through into long */
addword (nextword);
break;
+ case SIZE_BYTE:
+ as_bad (_("unsupported byte value; use a different suffix"));
+ /* Fall through. */
case SIZE_WORD: /* Word */
if (isvar (&opP->disp))
add_fix ('w', &opP->disp, 0, 0);
case CONTROL:
case FPREG:
default:
- as_bad ("unknown/incorrect operand");
- /* abort(); */
+ as_bad (_("unknown/incorrect operand"));
+ /* abort (); */
}
install_gen_operand (s[1], tmpreg);
break;
certain types of overflow.
user beware! */
if (!isbyte (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
the_ins.reloc[the_ins.nrel - 1].n =
(opcode->m_codenum) * 2 + 1;
break;
+ case 'B':
+ if (!issbyte (tmpreg))
+ opP->error = _("out of range");
+ the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
+ if (isvar (&opP->disp))
+ the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
+ break;
case 'w':
if (!isword (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
break;
case 'W':
if (!issword (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
tmpreg &= 0xFF;
case '8':
case 'C':
+ case 'j':
install_operand (s[1], tmpreg);
break;
default:
break;
case 'L':
long_branch:
- if (cpu_of_arch (current_architecture) < m68020)
- as_warn ("Can't use long branches on 68000/68010");
- the_ins.opcode[the_ins.numo - 1] |= 0xff;
+ if (! HAVE_LONG_BRANCH (current_architecture))
+ as_warn (_("Can't use long branches on 68000/68010/5200"));
+ the_ins.opcode[0] |= 0xff;
add_fix ('l', &opP->disp, 1, 0);
addword (0);
addword (0);
if (opP->disp.pic_reloc != pic_none)
goto long_branch;
#endif
-
/* This could either be a symbol, or an absolute
- address. No matter, the frag hacking will finger it
- out. Not quite: it can't switch from BRANCH to
- BCC68000 for the case where opnd is absolute (it
- needs to use the 68000 hack since no conditional abs
- jumps). */
- if (((cpu_of_arch (current_architecture) < m68020)
- || (0 == adds (&opP->disp)))
- && (the_ins.opcode[0] >= 0x6200)
- && (the_ins.opcode[0] <= 0x6f00))
+ address. If it's an absolute address, turn it into
+ an absolute jump right here and keep it out of the
+ relaxer. */
+ if (adds (&opP->disp) == 0)
+ {
+ if (the_ins.opcode[0] == 0x6000) /* jbra */
+ the_ins.opcode[0] = 0x4EF1;
+ else if (the_ins.opcode[0] == 0x6100) /* jbsr */
+ the_ins.opcode[0] = 0x4EB1;
+ else /* jCC */
+ {
+ the_ins.opcode[0] ^= 0x0100;
+ the_ins.opcode[0] |= 0x0006;
+ addword (0x4EF1);
+ }
+ add_fix ('l', &opP->disp, 0, 0);
+ addword (0);
+ addword (0);
+ break;
+ }
+
+ /* Now we know it's going into the relaxer. Now figure
+ out which mode. We try in this order of preference:
+ long branch, absolute jump, byte/word branches only. */
+ if (HAVE_LONG_BRANCH (current_architecture))
add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (BCC68000, SZ_UNDEF));
+ TAB (BRANCHBWL, SZ_UNDEF));
+ else if (! flag_keep_pcrel)
+ {
+ if ((the_ins.opcode[0] == 0x6000)
+ || (the_ins.opcode[0] == 0x6100))
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (BRABSJUNC, SZ_UNDEF));
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (BRABSJCOND, SZ_UNDEF));
+ }
else
add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (ABRANCH, SZ_UNDEF));
+ TAB (BRANCHBW, SZ_UNDEF));
break;
case 'w':
if (isvar (&opP->disp))
{
-#if 1
- /* check for DBcc instruction */
- if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
+ /* Check for DBcc instructions. We can relax them,
+ but only if we have long branches and/or absolute
+ jumps. */
+ if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
+ && (HAVE_LONG_BRANCH (current_architecture)
+ || (! flag_keep_pcrel)))
{
- /* size varies if patch */
- /* needed for long form */
- add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (DBCC, SZ_UNDEF));
+ if (HAVE_LONG_BRANCH (current_architecture))
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (DBCCLBR, SZ_UNDEF));
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (DBCCABSJ, SZ_UNDEF));
break;
}
-#endif
add_fix ('w', &opP->disp, 1, 0);
}
addword (0);
addword (0);
break;
case 'c': /* Var size Coprocesssor branches */
- if (subs (&opP->disp))
- {
- add_fix ('l', &opP->disp, 1, 0);
- add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
- }
- else if (adds (&opP->disp))
- add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (FBRANCH, SZ_UNDEF));
- else
+ if (subs (&opP->disp) || (adds (&opP->disp) == 0))
{
- /* add_frag((symbolS *) 0, offs(&opP->disp),
- TAB(FBRANCH,SHORT)); */
the_ins.opcode[the_ins.numo - 1] |= 0x40;
add_fix ('l', &opP->disp, 1, 0);
addword (0);
addword (0);
}
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (FBRANCH, SZ_UNDEF));
break;
default:
abort ();
tmpreg = get_num (&opP->disp, 80);
if (!issword (tmpreg))
{
- as_warn ("Expression out of range, using 0");
+ as_warn (_("Expression out of range, using 0"));
tmpreg = 0;
}
addword (tmpreg);
install_operand (s[1], opP->reg - DATA);
break;
+ case 'E': /* Ignore it */
+ break;
+
case 'F':
install_operand (s[1], opP->reg - FP0);
break;
+ case 'G': /* Ignore it */
+ case 'H':
+ break;
+
case 'I':
tmpreg = opP->reg - COP0;
install_operand (s[1], tmpreg);
if (s[1] == 'w')
{
if (tmpreg & 0x7FF0000)
- as_bad ("Floating point register in register list");
+ as_bad (_("Floating point register in register list"));
insop (reverse_16_bits (tmpreg), opcode);
}
else
{
if (tmpreg & 0x700FFFF)
- as_bad ("Wrong register in floating-point reglist");
+ as_bad (_("Wrong register in floating-point reglist"));
install_operand (s[1], reverse_8_bits (tmpreg >> 16));
}
break;
if (s[1] == 'w')
{
if (tmpreg & 0x7FF0000)
- as_bad ("Floating point register in register list");
+ as_bad (_("Floating point register in register list"));
insop (tmpreg, opcode);
}
else if (s[1] == '8')
{
if (tmpreg & 0x0FFFFFF)
- as_bad ("incorrect register in reglist");
+ as_bad (_("incorrect register in reglist"));
install_operand (s[1], tmpreg >> 24);
}
else
{
if (tmpreg & 0x700FFFF)
- as_bad ("wrong register in floating-point reglist");
+ as_bad (_("wrong register in floating-point reglist"));
else
install_operand (s[1], tmpreg >> 16);
}
case 'O':
tmpreg = ((opP->mode == DREG)
- ? 0x20 + opP->reg - DATA
+ ? 0x20 + (int) (opP->reg - DATA)
: (get_num (&opP->disp, 40) & 0x1F));
install_operand (s[1], tmpreg);
break;
tmpreg = 3;
break;
default:
- as_fatal ("failed sanity check");
+ as_fatal (_("failed sanity check"));
} /* switch on cache token */
install_operand (s[1], tmpreg);
break;
#ifndef NO_68851
- /* JF: These are out of order, I fear. */
+ /* JF: These are out of order, I fear. */
case 'f':
switch (opP->reg)
{
install_operand (s[1], tmpreg);
break;
case '_': /* used only for move16 absolute 32-bit address */
+ if (isvar (&opP->disp))
+ add_fix ('l', &opP->disp, 0, 0);
tmpreg = get_num (&opP->disp, 80);
addword (tmpreg >> 16);
addword (tmpreg & 0xFFFF);
break;
+ case 'u':
+ install_operand (s[1], opP->reg - DATA0L);
+ opP->reg -= (DATA0L);
+ opP->reg &= 0x0F; /* remove upper/lower bit */
+ break;
default:
abort ();
}
}
/* By the time whe get here (FINALLY) the_ins contains the complete
- instruction, ready to be emitted. . . */
+ instruction, ready to be emitted. . . */
}
static int
the_ins.opcode[1] = (val >> 16);
the_ins.opcode[2] = val & 0xffff;
break;
+ case 'm':
+ the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
+ the_ins.opcode[0] |= ((val & 0x7) << 9);
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
+ break;
+ case 'n':
+ the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
+ the_ins.opcode[0] |= ((val & 0x7) << 9);
+ break;
+ case 'o':
+ the_ins.opcode[1] |= val << 12;
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
+ break;
+ case 'M':
+ the_ins.opcode[0] |= (val & 0xF);
+ the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
+ break;
+ case 'N':
+ the_ins.opcode[1] |= (val & 0xF);
+ the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
+ break;
+ case 'h':
+ the_ins.opcode[1] |= ((val != 1) << 10);
+ break;
case 'c':
default:
- as_fatal ("failed sanity check.");
+ as_fatal (_("failed sanity check."));
}
} /* install_operand() */
break;
/* more stuff goes here */
default:
- as_fatal ("failed sanity check.");
+ as_fatal (_("failed sanity check."));
}
} /* install_gen_operand() */
{
if (!parens)
{ /* ERROR */
- opP->error = "Extra )";
+ opP->error = _("Extra )");
return str;
}
--parens;
}
if (!*str && parens)
{ /* ERROR */
- opP->error = "Missing )";
+ opP->error = _("Missing )");
return str;
}
c = *str;
{
c = *++str;
if (!c)
- as_bad ("Missing operand");
+ as_bad (_("Missing operand"));
+ }
+
+ /* Detect MRI REG symbols and convert them to REGLSTs. */
+ if (opP->mode == CONTROL && (int)opP->reg < 0)
+ {
+ opP->mode = REGLST;
+ opP->mask = ~(int)opP->reg;
+ opP->reg = 0;
}
+
return str;
}
the frags/bytes it assembles to.
*/
-void
+static void
insert_reg (regname, regnum)
- char *regname;
+ const char *regname;
int regnum;
{
char buf[100];
{ "ccr", CCR },
{ "cc", CCR },
+ { "acc", ACC },
+ { "macsr", MACSR },
+ { "mask", MASK },
+
/* control registers */
{ "sfc", SFC }, /* Source Function Code */
{ "sfcr", SFC },
{ "dacr0", DTT0 }, /* Data Access Control Register 0 */
{ "dacr1", DTT1 }, /* Data Access Control Register 0 */
- /* mcf5200 versions of same */
- { "acr2", ITT0 }, /* Access Control Unit 2 */
- { "acr3", ITT1 }, /* Access Control Unit 3 */
- { "acr0", DTT0 }, /* Access Control Unit 0 */
- { "acr1", DTT1 }, /* Access Control Unit 1 */
+ /* mcf5200 versions of same. The ColdFire programmer's reference
+ manual indicated that the order is 2,3,0,1, but Ken Rose
+ <rose@netcom.com> says that 0,1,2,3 is the correct order. */
+ { "acr0", ITT0 }, /* Access Control Unit 0 */
+ { "acr1", ITT1 }, /* Access Control Unit 1 */
+ { "acr2", DTT0 }, /* Access Control Unit 2 */
+ { "acr3", DTT1 }, /* Access Control Unit 3 */
{ "tc", TC }, /* MMU Translation Control Register */
{ "tcr", TC },
{ "za6", ZADDR6 },
{ "za7", ZADDR7 },
+ /* Upper and lower data and address registers, used by macw and msacw. */
+ { "d0l", DATA0L },
+ { "d1l", DATA1L },
+ { "d2l", DATA2L },
+ { "d3l", DATA3L },
+ { "d4l", DATA4L },
+ { "d5l", DATA5L },
+ { "d6l", DATA6L },
+ { "d7l", DATA7L },
+
+ { "a0l", ADDR0L },
+ { "a1l", ADDR1L },
+ { "a2l", ADDR2L },
+ { "a3l", ADDR3L },
+ { "a4l", ADDR4L },
+ { "a5l", ADDR5L },
+ { "a6l", ADDR6L },
+ { "a7l", ADDR7L },
+
+ { "d0u", DATA0U },
+ { "d1u", DATA1U },
+ { "d2u", DATA2U },
+ { "d3u", DATA3U },
+ { "d4u", DATA4U },
+ { "d5u", DATA5U },
+ { "d6u", DATA6U },
+ { "d7u", DATA7U },
+
+ { "a0u", ADDR0U },
+ { "a1u", ADDR1U },
+ { "a2u", ADDR2U },
+ { "a3u", ADDR3U },
+ { "a4u", ADDR4U },
+ { "a5u", ADDR5U },
+ { "a6u", ADDR6U },
+ { "a7u", ADDR7U },
+
{ 0, 0 }
};
-void
+static void
init_regtable ()
{
int i;
}
if (er)
{
- as_bad ("%s -- statement `%s' ignored", er, str);
+ as_bad (_("%s -- statement `%s' ignored"), er, str);
return;
}
+ /* If there is a current label, record that it marks an instruction. */
+ if (current_label != NULL)
+ {
+ current_label->text = 1;
+ current_label = NULL;
+ }
+
if (the_ins.nfrag == 0)
{
/* No frag hacking involved; just put it out */
n = 1;
break;
case '3':
- n = 2;
+ n = 1;
break;
case 'w':
+ case 'W':
n = 2;
break;
case 'l':
n = 4;
break;
default:
- as_fatal ("Don't know how to figure width of %c in md_assemble()",
+ as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
the_ins.reloc[m].wid);
}
get_reloc_code (n, the_ins.reloc[m].pcrel,
the_ins.reloc[m].pic_reloc));
fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
+ if (the_ins.reloc[m].wid == 'B')
+ fixP->fx_signed = 1;
}
return;
}
register const struct m68k_opcode *ins;
register struct m68k_incant *hack, *slak;
register const char *retval = 0; /* empty string, or error msg text */
- register unsigned int i;
+ register int i;
register char c;
if (flag_mri)
{
flag_reg_prefix_optional = 1;
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
op_hash = hash_new ();
{
ins = &m68k_opcodes[i];
/* We *could* ignore insns that don't match our arch here
- but just leaving them out of the hash. */
+ but just leaving them out of the hash. */
slak->m_operands = ins->args;
slak->m_opnum = strlen (slak->m_operands) / 2;
slak->m_arch = ins->arch;
retval = hash_insert (op_hash, ins->name, (char *) hack);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
}
for (i = 0; i < m68k_numaliases; i++)
const char *alias = m68k_opcode_aliases[i].alias;
PTR val = hash_find (op_hash, name);
if (!val)
- as_fatal ("Internal Error: Can't find %s in hash table", name);
+ as_fatal (_("Internal Error: Can't find %s in hash table"), name);
retval = hash_insert (op_hash, alias, val);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
}
/* In MRI mode, all unsized branches are variable sized. Normally,
{ "bsr", "jbsr", },
};
- for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
+ for (i = 0;
+ i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
+ i++)
{
const char *name = mri_aliases[i].primary;
const char *alias = mri_aliases[i].alias;
PTR val = hash_find (op_hash, name);
if (!val)
- as_fatal ("Internal Error: Can't find %s in hash table", name);
+ as_fatal (_("Internal Error: Can't find %s in hash table"), name);
retval = hash_jam (op_hash, alias, val);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
}
}
- for (i = 0; i < sizeof (mklower_table); i++)
+ for (i = 0; i < (int) sizeof (mklower_table); i++)
mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
- for (i = 0; i < sizeof (notend_table); i++)
+ for (i = 0; i < (int) sizeof (notend_table); i++)
{
notend_table[i] = 0;
alt_notend_table[i] = 0;
#endif
}
-void
-m68k_init_after_args ()
+static void
+select_control_regs ()
{
- if (cpu_of_arch (current_architecture) == 0)
+ /* Note which set of "movec" control registers is available. */
+ switch (cpu_of_arch (current_architecture))
+ {
+ case m68000:
+ control_regs = m68000_control_regs;
+ break;
+ case m68010:
+ control_regs = m68010_control_regs;
+ break;
+ case m68020:
+ case m68030:
+ control_regs = m68020_control_regs;
+ break;
+ case m68040:
+ control_regs = m68040_control_regs;
+ break;
+ case m68060:
+ control_regs = m68060_control_regs;
+ break;
+ case cpu32:
+ control_regs = cpu32_control_regs;
+ break;
+ case mcf5200:
+ case mcf5206e:
+ case mcf5307:
+ case mcf5407:
+ control_regs = mcf_control_regs;
+ break;
+ default:
+ abort ();
+ }
+}
+
+void
+m68k_init_after_args ()
+{
+ if (cpu_of_arch (current_architecture) == 0)
{
int i;
const char *default_cpu = TARGET_CPU;
break;
if (i == n_archs)
{
- as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
+ as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
current_architecture |= m68020;
}
else
{
if (current_architecture & m68040)
{
- as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
+ as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
}
}
/* What other incompatibilities could we check for? */
current_architecture |= m68851;
}
if (no_68881 && (current_architecture & m68881))
- as_bad ("options for 68881 and no-68881 both given");
+ as_bad (_("options for 68881 and no-68881 both given"));
if (no_68851 && (current_architecture & m68851))
- as_bad ("options for 68851 and no-68851 both given");
+ as_bad (_("options for 68851 and no-68851 both given"));
#ifdef OBJ_AOUT
/* Work out the magic number. This isn't very general. */
#endif
/* Note which set of "movec" control registers is available. */
- switch (cpu_of_arch (current_architecture))
- {
- case m68000:
- control_regs = m68000_control_regs;
- break;
- case m68010:
- control_regs = m68010_control_regs;
- break;
- case m68020:
- case m68030:
- control_regs = m68020_control_regs;
- break;
- case m68040:
- control_regs = m68040_control_regs;
- break;
- case m68060:
- control_regs = m68060_control_regs;
- break;
- case cpu32:
- control_regs = cpu32_control_regs;
- break;
- case mcf5200:
- control_regs = mcf5200_control_regs;
- break;
- default:
- abort ();
- }
+ select_control_regs ();
- if (cpu_of_arch (current_architecture) < m68020)
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
}
+\f
+/* This is called when a label is defined. */
+
+void
+m68k_frob_label (sym)
+ symbolS *sym;
+{
+ struct label_line *n;
+
+ n = (struct label_line *) xmalloc (sizeof *n);
+ n->next = labels;
+ n->label = sym;
+ as_where (&n->file, &n->line);
+ n->text = 0;
+ labels = n;
+ current_label = n;
+}
+/* This is called when a value that is not an instruction is emitted. */
+
+void
+m68k_flush_pending_output ()
+{
+ current_label = NULL;
+}
+
+/* This is called at the end of the assembly, when the final value of
+ the label is known. We warn if this is a text symbol aligned at an
+ odd location. */
+
+void
+m68k_frob_symbol (sym)
+ symbolS *sym;
+{
+ if (S_GET_SEGMENT (sym) == reg_section
+ && (int) S_GET_VALUE (sym) < 0)
+ {
+ S_SET_SEGMENT (sym, absolute_section);
+ S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
+ }
+ else if ((S_GET_VALUE (sym) & 1) != 0)
+ {
+ struct label_line *l;
+
+ for (l = labels; l != NULL; l = l->next)
+ {
+ if (l->label == sym)
+ {
+ if (l->text)
+ as_warn_where (l->file, l->line,
+ _("text label `%s' aligned to odd boundary"),
+ S_GET_NAME (sym));
+ break;
+ }
+ }
+ }
+}
+\f
/* This is called if we go in or out of MRI mode because of the .mri
pseudo-op. */
#endif
}
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
else
{
#endif
}
m68k_abspcadd = 0;
- m68k_rel32 = 1;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 1;
}
}
#define MAX_LITTLENUMS 6
/* Turn a string in input_line_pointer into a floating point constant
- of type type, and store the appropriate bytes in *litP. The number
- of LITTLENUMS emitted is stored in *sizeP . An error message is
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
returned, or NULL on OK. */
char *
LITTLENUM_TYPE words[MAX_LITTLENUMS];
LITTLENUM_TYPE *wordP;
char *t;
- char *atof_ieee ();
switch (type)
{
default:
*sizeP = 0;
- return "Bad call to MD_ATOF()";
+ return _("Bad call to MD_ATOF()");
}
t = atof_ieee (input_line_pointer, type, words);
if (t)
{
memset (buf, 0, fixP->fx_size);
fixP->fx_addnumber = val; /* Remember value for emit_reloc */
+
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ && !S_IS_DEFINED (fixP->fx_addsy)
+ && !S_IS_WEAK (fixP->fx_addsy))
+ S_SET_WEAK (fixP->fx_addsy);
return;
}
#endif
+#ifdef BFD_ASSEMBLER
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ return;
+#endif
+
switch (fixP->fx_size)
{
/* The cast to offsetT below are necessary to make code correct for
like "0xff" for a byte field. So extend the upper part of the range
to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
so that we can do any range checking at all. */
- if (!fixP->fx_pcrel)
+ if (! fixP->fx_pcrel && ! fixP->fx_signed)
upper_limit = upper_limit * 2 + 1;
if ((addressT) val > upper_limit
&& (val > 0 || val < lower_limit))
- as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
+ as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
/* A one byte PC-relative reloc means a short branch. We can't use
a short branch with a value of 0 or -1, because those indicate
- different opcodes (branches with longer offsets). */
- if (fixP->fx_pcrel
+ different opcodes (branches with longer offsets). fixup_segment
+ in write.c may have clobbered fx_pcrel, so we need to examine the
+ reloc type. */
+ if ((fixP->fx_pcrel
+#ifdef BFD_ASSEMBLER
+ || fixP->fx_r_type == BFD_RELOC_8_PCREL
+#endif
+ )
&& fixP->fx_size == 1
&& (fixP->fx_addsy == NULL
|| S_IS_DEFINED (fixP->fx_addsy))
&& (val == 0 || val == -1))
- as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
+ as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
}
#ifdef BFD_ASSEMBLER
the bytes inside it modified to conform to the new size There is UGLY
MAGIC here. ..
*/
-void
+static void
md_convert_frag_1 (fragP)
register fragS *fragP;
{
long disp;
- long ext = 0;
fixS *fixP;
/* Address in object code of the displacement. */
/* Address in gas core of the place to store the displacement. */
/* This convinces the native rs6000 compiler to generate the code we
- want. */
+ want. */
register char *buffer_address = fragP->fr_literal;
buffer_address += fragP->fr_fix;
/* end ibm compiler workaround */
disp = (disp + fragP->fr_offset) - object_address;
#ifdef BFD_ASSEMBLER
- disp += fragP->fr_symbol->sy_frag->fr_address;
+ disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
#endif
switch (fragP->fr_subtype)
{
- case TAB (BCC68000, BYTE):
- case TAB (ABRANCH, BYTE):
+ case TAB (BRANCHBWL, BYTE):
+ case TAB (BRABSJUNC, BYTE):
+ case TAB (BRABSJCOND, BYTE):
+ case TAB (BRANCHBW, BYTE):
know (issbyte (disp));
if (disp == 0)
- as_bad ("short branch with zero offset: use :w");
- fragP->fr_opcode[1] = disp;
- ext = 0;
- break;
- case TAB (DBCC, SHORT):
- know (issword (disp));
- ext = 2;
+ as_bad (_("short branch with zero offset: use :w"));
+ fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC8);
+ fixP->fx_pcrel_adjust = -1;
break;
- case TAB (BCC68000, SHORT):
- case TAB (ABRANCH, SHORT):
- know (issword (disp));
+ case TAB (BRANCHBWL, SHORT):
+ case TAB (BRABSJUNC, SHORT):
+ case TAB (BRABSJCOND, SHORT):
+ case TAB (BRANCHBW, SHORT):
fragP->fr_opcode[1] = 0x00;
- ext = 2;
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (BRANCHBWL, LONG):
+ fragP->fr_opcode[1] = (char) 0xFF;
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC32);
+ fragP->fr_fix += 4;
break;
- case TAB (ABRANCH, LONG):
- if (cpu_of_arch (current_architecture) < m68020)
+ case TAB (BRABSJUNC, LONG):
+ if (fragP->fr_opcode[0] == 0x61) /* jbsr */
{
- if (fragP->fr_opcode[0] == 0x61)
- /* BSR */
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
-
- fix_new (fragP,
- fragP->fr_fix,
- 4,
- fragP->fr_symbol,
- fragP->fr_offset,
- 0,
- NO_RELOC);
-
- fragP->fr_fix += 4;
- ext = 0;
- }
- /* BRA */
- else if (fragP->fr_opcode[0] == 0x60)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- ext = 0;
- }
- else
- {
- as_bad ("Long branch offset not supported.");
- }
+ fragP->fr_opcode[0] = 0x4E;
+ fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
+ }
+ else if (fragP->fr_opcode[0] == 0x60) /* jbra */
+ {
+ fragP->fr_opcode[0] = 0x4E;
+ fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
}
else
{
- fragP->fr_opcode[1] = (char) 0xff;
- ext = 4;
+ /* This cannot happen, because jbsr and jbra are the only two
+ unconditional branches. */
+ abort ();
}
break;
- case TAB (BCC68000, LONG):
- /* only Bcc 68000 instructions can come here */
- /* change bcc into b!cc/jmp absl long */
+ case TAB (BRABSJCOND, LONG):
+ /* Only Bcc 68000 instructions can come here. */
+ /* Change bcc into b!cc/jmp absl long. */
+
fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
/* JF: these used to be fr_opcode[2,3], but they may be in a
different frag, in which case refering to them is a no-no.
- Only fr_opcode[0,1] are guaranteed to work. */
+ Only fr_opcode[0,1] are guaranteed to work. */
*buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address++ = (char) 0xf9;
fragP->fr_fix += 2; /* account for jmp instruction */
fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
+ fragP->fr_offset, 0, RELAX_RELOC_ABS32);
fragP->fr_fix += 4;
- ext = 0;
break;
- case TAB (DBCC, LONG):
- /* only DBcc 68000 instructions can come here */
- /* change dbcc into dbcc/jmp absl long */
+ case TAB (FBRANCH, SHORT):
+ know ((fragP->fr_opcode[1] & 0x40) == 0);
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (FBRANCH, LONG):
+ fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC32);
+ fragP->fr_fix += 4;
+ break;
+ case TAB (DBCCLBR, SHORT):
+ case TAB (DBCCABSJ, SHORT):
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (DBCCLBR, LONG):
+ /* only DBcc instructions can come here */
+ /* Change dbcc into dbcc/bral. */
+
/* JF: these used to be fr_opcode[2-7], but that's wrong */
*buffer_address++ = 0x00; /* branch offset = 4 */
*buffer_address++ = 0x04;
*buffer_address++ = 0x60; /* put in bra pc+6 */
*buffer_address++ = 0x06;
- *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
- *buffer_address++ = (char) 0xf9;
+ *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
+ *buffer_address++ = (char) 0xff;
fragP->fr_fix += 6; /* account for bra/jmp instructions */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
+ RELAX_RELOC_PC32);
fragP->fr_fix += 4;
- ext = 0;
break;
- case TAB (FBRANCH, SHORT):
- know ((fragP->fr_opcode[1] & 0x40) == 0);
- ext = 2;
- break;
- case TAB (FBRANCH, LONG):
- fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
- ext = 4;
- break;
- case TAB (PCREL, SHORT):
- ext = 2;
- break;
- case TAB (PCREL, LONG):
- /* The thing to do here is force it to ABSOLUTE LONG, since
- PCREL is really trying to shorten an ABSOLUTE address anyway */
- /* JF FOO This code has not been tested */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
- 0, NO_RELOC);
- if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
- as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
- (unsigned) fragP->fr_opcode[0],
- (unsigned long) fragP->fr_address);
- fragP->fr_opcode[1] &= ~0x3F;
- fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
+ case TAB (DBCCABSJ, LONG):
+ /* only DBcc instructions can come here */
+ /* Change dbcc into dbcc/jmp. */
+
+ /* JF: these used to be fr_opcode[2-7], but that's wrong */
+ *buffer_address++ = 0x00; /* branch offset = 4 */
+ *buffer_address++ = 0x04;
+ *buffer_address++ = 0x60; /* put in bra pc+6 */
+ *buffer_address++ = 0x06;
+ *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
+ *buffer_address++ = (char) 0xf9;
+
+ fragP->fr_fix += 6; /* account for bra/jmp instructions */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
+ RELAX_RELOC_ABS32);
fragP->fr_fix += 4;
- ext = 0;
break;
- case TAB (PCLEA, SHORT):
- fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
+ case TAB (PCREL1632, SHORT):
fragP->fr_opcode[1] &= ~0x3F;
fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
- ext = 2;
+ fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
break;
- case TAB (PCLEA, LONG):
- fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fixP->fx_pcrel_adjust = 2;
+ case TAB (PCREL1632, LONG):
/* Already set to mode 7.3; this indicates: PC indirect with
suppressed index, 32-bit displacement. */
*buffer_address++ = 0x01;
*buffer_address++ = 0x70;
fragP->fr_fix += 2;
- ext = 4;
+ fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC32);
+ fixP->fx_pcrel_adjust = 2;
+ fragP->fr_fix += 4;
break;
-
case TAB (PCINDEX, BYTE):
- disp += 2;
- if (!issbyte (disp))
- {
- as_bad ("displacement doesn't fit in one byte");
- disp = 0;
- }
assert (fragP->fr_fix >= 2);
buffer_address[-2] &= ~1;
- buffer_address[-1] = disp;
- ext = 0;
+ fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC8);
+ fixP->fx_pcrel_adjust = 1;
break;
case TAB (PCINDEX, SHORT):
- disp += 2;
- assert (issword (disp));
assert (fragP->fr_fix >= 2);
buffer_address[-2] |= 0x1;
buffer_address[-1] = 0x20;
fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
- fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
- NO_RELOC);
+ fragP->fr_offset, 1, RELAX_RELOC_PC16);
fixP->fx_pcrel_adjust = 2;
- ext = 2;
+ fragP->fr_fix += 2;
break;
case TAB (PCINDEX, LONG):
- disp += 2;
- fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
- fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
- NO_RELOC);
- fixP->fx_pcrel_adjust = 2;
assert (fragP->fr_fix >= 2);
buffer_address[-2] |= 0x1;
buffer_address[-1] = 0x30;
- ext = 4;
+ fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC32);
+ fixP->fx_pcrel_adjust = 2;
+ fragP->fr_fix += 4;
+ break;
+ case TAB (ABSTOPCREL, SHORT):
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (ABSTOPCREL, LONG):
+ /* The thing to do here is force it to ABSOLUTE LONG, since
+ ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
+ if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
+ abort ();
+ fragP->fr_opcode[1] &= ~0x3F;
+ fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
break;
- }
-
- if (ext)
- {
- md_number_to_chars (buffer_address, (long) disp, (int) ext);
- fragP->fr_fix += ext;
}
}
void
md_convert_frag (headers, sec, fragP)
- object_headers *headers;
- segT sec;
+ object_headers *headers ATTRIBUTE_UNUSED;
+ segT sec ATTRIBUTE_UNUSED;
fragS *fragP;
{
md_convert_frag_1 (fragP);
void
md_convert_frag (abfd, sec, fragP)
- bfd *abfd;
- segT sec;
+ bfd *abfd ATTRIBUTE_UNUSED;
+ segT sec ATTRIBUTE_UNUSED;
fragS *fragP;
{
md_convert_frag_1 (fragP);
segT segment;
{
int old_fix;
- register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
old_fix = fragP->fr_fix;
- /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
+ /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
switch (fragP->fr_subtype)
{
-
- case TAB (ABRANCH, SZ_UNDEF):
+ case TAB (BRANCHBWL, SZ_UNDEF):
+ case TAB (BRABSJUNC, SZ_UNDEF):
{
- if ((fragP->fr_symbol != NULL) /* Not absolute */
- && S_GET_SEGMENT (fragP->fr_symbol) == segment)
+ if (S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
{
fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
- break;
}
- else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
+ else if (flag_short_refs)
{
- /* On 68000, or for absolute value, switch to abs long */
- /* FIXME, we should check abs val, pick short or long */
- if (fragP->fr_opcode[0] == 0x61)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4,
- fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- frag_wane (fragP);
- }
- else if (fragP->fr_opcode[0] == 0x60)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4,
- fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- frag_wane (fragP);
- }
- else
- {
- as_warn ("Long branch offset to extern symbol not supported.");
- }
+ /* Symbol is undefined and we want short ref. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
+ fragP->fr_var += 2;
}
else
- { /* Symbol is still undefined. Make it simple */
- fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fragP->fr_fix += 4;
- fragP->fr_opcode[1] = (char) 0xff;
- frag_wane (fragP);
- break;
+ {
+ /* Symbol is still undefined. Make it LONG. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
+ fragP->fr_var += 4;
}
-
break;
- } /* case TAB(ABRANCH,SZ_UNDEF) */
+ }
- case TAB (FBRANCH, SZ_UNDEF):
+ case TAB (BRABSJCOND, SZ_UNDEF):
{
- if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
+ if (S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
{
- fragP->fr_subtype = TAB (FBRANCH, SHORT);
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
+ }
+ else if (flag_short_refs)
+ {
+ /* Symbol is undefined and we want short ref. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
fragP->fr_var += 2;
}
else
{
- fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fragP->fr_fix += 4;
- fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
- frag_wane (fragP);
+ /* Symbol is still undefined. Make it LONG. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
+ fragP->fr_var += 6;
}
break;
- } /* TAB(FBRANCH,SZ_UNDEF) */
+ }
- case TAB (PCREL, SZ_UNDEF):
+ case TAB (BRANCHBW, SZ_UNDEF):
{
if (S_GET_SEGMENT (fragP->fr_symbol) == segment
- || flag_short_refs
- || cpu_of_arch (current_architecture) < m68020)
+ && relaxable_symbol (fragP->fr_symbol))
{
- fragP->fr_subtype = TAB (PCREL, SHORT);
- fragP->fr_var += 2;
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
}
else
{
- fragP->fr_subtype = TAB (PCREL, LONG);
- fragP->fr_var += 4;
+ /* Symbol is undefined and we don't have long branches. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
+ fragP->fr_var += 2;
}
break;
- } /* TAB(PCREL,SZ_UNDEF) */
+ }
- case TAB (BCC68000, SZ_UNDEF):
+ case TAB (FBRANCH, SZ_UNDEF):
{
- if ((fragP->fr_symbol != NULL)
- && S_GET_SEGMENT (fragP->fr_symbol) == segment)
- {
- fragP->fr_subtype = TAB (BCC68000, BYTE);
- break;
- }
- /* only Bcc 68000 instructions can come here */
- /* change bcc into b!cc/jmp absl long */
- fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
- if (flag_short_refs)
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
+ || flag_short_refs)
{
- fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
- /* JF: these were fr_opcode[2,3] */
- buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[1] = (char) 0xf8;
- fragP->fr_fix += 2; /* account for jmp instruction */
- fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 2;
+ fragP->fr_subtype = TAB (FBRANCH, SHORT);
+ fragP->fr_var += 2;
}
else
{
- fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
- /* JF: these were fr_opcode[2,3] */
- buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[1] = (char) 0xf9;
- fragP->fr_fix += 2; /* account for jmp instruction */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
+ fragP->fr_subtype = TAB (FBRANCH, LONG);
+ fragP->fr_var += 4;
}
- frag_wane (fragP);
break;
- } /* case TAB(BCC68000,SZ_UNDEF) */
+ }
- case TAB (DBCC, SZ_UNDEF):
+ case TAB (DBCCLBR, SZ_UNDEF):
+ case TAB (DBCCABSJ, SZ_UNDEF):
{
- if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
+ || flag_short_refs)
{
- fragP->fr_subtype = TAB (DBCC, SHORT);
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
fragP->fr_var += 2;
- break;
- }
- /* only DBcc 68000 instructions can come here */
- /* change dbcc into dbcc/jmp absl long */
- /* JF: these used to be fr_opcode[2-4], which is wrong. */
- buffer_address[0] = 0x00; /* branch offset = 4 */
- buffer_address[1] = 0x04;
- buffer_address[2] = 0x60; /* put in bra pc + ... */
-
- if (flag_short_refs)
- {
- /* JF: these were fr_opcode[5-7] */
- buffer_address[3] = 0x04; /* plus 4 */
- buffer_address[4] = 0x4e; /* Put in Jump Word */
- buffer_address[5] = (char) 0xf8;
- fragP->fr_fix += 6; /* account for bra/jmp instruction */
- fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 2;
}
else
{
- /* JF: these were fr_opcode[5-7] */
- buffer_address[3] = 0x06; /* Plus 6 */
- buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[5] = (char) 0xf9;
- fragP->fr_fix += 6; /* account for bra/jmp instruction */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
+ fragP->fr_var += 10;
}
-
- frag_wane (fragP);
break;
- } /* case TAB(DBCC,SZ_UNDEF) */
+ }
- case TAB (PCLEA, SZ_UNDEF):
+ case TAB (PCREL1632, SZ_UNDEF):
{
- if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
- || flag_short_refs
- || cpu_of_arch (current_architecture) < m68020)
+ if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
+ && relaxable_symbol (fragP->fr_symbol))
+ || flag_short_refs)
{
- fragP->fr_subtype = TAB (PCLEA, SHORT);
+ fragP->fr_subtype = TAB (PCREL1632, SHORT);
fragP->fr_var += 2;
}
else
{
- fragP->fr_subtype = TAB (PCLEA, LONG);
+ fragP->fr_subtype = TAB (PCREL1632, LONG);
fragP->fr_var += 6;
}
break;
- } /* TAB(PCLEA,SZ_UNDEF) */
+ }
case TAB (PCINDEX, SZ_UNDEF):
- if (S_GET_SEGMENT (fragP->fr_symbol) == segment
- || cpu_of_arch (current_architecture) < m68020)
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol)))
{
fragP->fr_subtype = TAB (PCINDEX, BYTE);
}
}
break;
+ case TAB (ABSTOPCREL, SZ_UNDEF):
+ {
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol)))
+ {
+ fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
+ fragP->fr_var += 2;
+ }
+ else
+ {
+ fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
+ fragP->fr_var += 4;
+ }
+ break;
+ }
+
default:
break;
}
- /* now that SZ_UNDEF are taken care of, check others */
+ /* Now that SZ_UNDEF are taken care of, check others. */
switch (fragP->fr_subtype)
{
- case TAB (BCC68000, BYTE):
- case TAB (ABRANCH, BYTE):
+ case TAB (BRANCHBWL, BYTE):
+ case TAB (BRABSJUNC, BYTE):
+ case TAB (BRABSJCOND, BYTE):
+ case TAB (BRANCHBW, BYTE):
/* We can't do a short jump to the next instruction, so in that
case we force word mode. At this point S_GET_VALUE should
return the offset of the symbol within its frag. If the
word mode. */
if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
{
+ fragS *stop;
fragS *l;
- for (l = fragP->fr_next;
- l != fragP->fr_symbol->sy_frag;
- l = l->fr_next)
+ stop = symbol_get_frag (fragP->fr_symbol);
+ for (l = fragP->fr_next; l != stop; l = l->fr_next)
if (l->fr_fix + l->fr_var != 0)
break;
- if (l == fragP->fr_symbol->sy_frag)
+ if (l == stop)
{
fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
fragP->fr_var += 2;
bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
nibble as nuthin. (on Sun 3 at least) */
/* Translate the internal relocation information into target-specific
- format. */
+ format. */
#ifdef comment
void
md_ri_to_chars (the_bytes, ri)
md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
char *ptr;
addressT from_addr, to_addr;
- fragS *frag;
- symbolS *to_symbol;
+ fragS *frag ATTRIBUTE_UNUSED;
+ symbolS *to_symbol ATTRIBUTE_UNUSED;
{
valueT offset;
{
valueT offset;
- if (cpu_of_arch (current_architecture) < m68020)
+ if (!HAVE_LONG_BRANCH(current_architecture))
{
offset = to_addr - S_GET_VALUE (to_symbol);
md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
offs (exp) = 0;
if (ok == 10)
{
- as_warn ("expression out of range: defaulting to 1");
+ as_warn (_("expression out of range: defaulting to 1"));
offs (exp) = 1;
}
}
case 10:
if (offs (exp) < 1 || offs (exp) > 8)
{
- as_warn ("expression out of range: defaulting to 1");
+ as_warn (_("expression out of range: defaulting to 1"));
offs (exp) = 1;
}
break;
if (offs (exp) < 0 || offs (exp) > 4095)
{
outrange:
- as_warn ("expression out of range: defaulting to 0");
+ as_warn (_("expression out of range: defaulting to 0"));
offs (exp) = 0;
}
break;
adds (exp) = 0;
subs (exp) = 0;
offs (exp) = (ok == 10) ? 1 : 0;
- as_warn ("Can't deal with expression; defaulting to %ld",
+ as_warn (_("Can't deal with expression; defaulting to %ld"),
offs (exp));
}
}
adds (exp) = 0;
subs (exp) = 0;
offs (exp) = (ok == 10) ? 1 : 0;
- as_warn ("Can't deal with expression; defaulting to %ld",
+ as_warn (_("Can't deal with expression; defaulting to %ld"),
offs (exp));
}
}
break;
case SIZE_BYTE:
if (!isbyte (offs (exp)))
- as_warn ("expression doesn't fit in BYTE");
+ as_warn (_("expression doesn't fit in BYTE"));
break;
case SIZE_WORD:
if (!isword (offs (exp)))
- as_warn ("expression doesn't fit in WORD");
+ as_warn (_("expression doesn't fit in WORD"));
break;
}
}
}
/* These are the back-ends for the various machine dependent pseudo-ops. */
-void demand_empty_rest_of_line (); /* Hate those extra verbose names */
static void
s_data1 (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
subseg_set (data_section, 1);
demand_empty_rest_of_line ();
static void
s_data2 (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
subseg_set (data_section, 2);
demand_empty_rest_of_line ();
static void
s_bss (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
/* We don't support putting frags in the BSS segment, we fake it
by marking in_bss, then looking at s_skip for clues. */
static void
s_even (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
register int temp;
register long temp_fill;
temp = 1; /* JF should be 2? */
temp_fill = get_absolute_expression ();
- if (!need_pass_2) /* Never make frag if expect extra pass. */
- frag_align (temp, (int) temp_fill);
+ if (!need_pass_2) /* Never make frag if expect extra pass. */
+ frag_align (temp, (int) temp_fill, 0);
demand_empty_rest_of_line ();
+ record_alignment (now_seg, temp);
}
static void
s_proc (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
demand_empty_rest_of_line ();
}
\f
/* Pseudo-ops handled for MRI compatibility. */
+/* This function returns non-zero if the argument is a conditional
+ pseudo-op. This is called when checking whether a pending
+ alignment is needed. */
+
+int
+m68k_conditional_pseudoop (pop)
+ pseudo_typeS *pop;
+{
+ return (pop->poc_handler == s_mri_if
+ || pop->poc_handler == s_mri_else);
+}
+
/* Handle an MRI style chip specification. */
static void
int i;
s = input_line_pointer;
- c = get_symbol_end ();
+ /* We can't use get_symbol_end since the processor names are not proper
+ symbols. */
+ while (is_part_of_name (c = *input_line_pointer++))
+ ;
+ *--input_line_pointer = 0;
for (i = 0; i < n_archs; i++)
if (strcasecmp (s, archs[i].name) == 0)
break;
if (i >= n_archs)
{
- as_bad ("%s: unrecognized processor name", s);
+ as_bad (_("%s: unrecognized processor name"), s);
*input_line_pointer = c;
ignore_rest_of_line ();
return;
{
++input_line_pointer;
s = input_line_pointer;
- c = get_symbol_end ();
+ /* We can't use get_symbol_end since the processor names are not
+ proper symbols. */
+ while (is_part_of_name (c = *input_line_pointer++))
+ ;
+ *--input_line_pointer = 0;
if (strcmp (s, "68881") == 0)
current_architecture |= m68881;
else if (strcmp (s, "68851") == 0)
current_architecture |= m68851;
*input_line_pointer = c;
}
+
+ /* Update info about available control registers. */
+ select_control_regs ();
}
/* The MRI CHIP pseudo-op. */
static void
s_chip (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *stop = NULL;
char stopc;
static void
s_fopt (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
SKIP_WHITESPACE ();
input_line_pointer += 3;
temp = get_absolute_expression ();
if (temp < 0 || temp > 7)
- as_bad ("bad coprocessor id");
+ as_bad (_("bad coprocessor id"));
else
m68k_float_copnum = COP0 + temp;
}
else
{
- as_bad ("unrecognized fopt option");
+ as_bad (_("unrecognized fopt option"));
ignore_rest_of_line ();
return;
}
{ "x", 0, 0, 0, 0 }
};
-#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
+#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
/* The MRI OPT pseudo-op. */
static void
s_opt (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
do
{
else if (o->pvar != NULL)
{
if (! t && o->arg == o->notarg)
- as_bad ("option `%s' may not be negated", s);
+ as_bad (_("option `%s' may not be negated"), s);
*input_line_pointer = c;
*o->pvar = t ? o->arg : o->notarg;
}
}
if (i >= OPTCOUNT)
{
- as_bad ("option `%s' not recognized", s);
+ as_bad (_("option `%s' not recognized"), s);
*input_line_pointer = c;
}
}
static void
skip_to_comma (arg, on)
- int arg;
- int on;
+ int arg ATTRIBUTE_UNUSED;
+ int on ATTRIBUTE_UNUSED;
{
while (*input_line_pointer != ','
&& ! is_end_of_line[(unsigned char) *input_line_pointer])
static void
opt_nest (arg, on)
- int arg;
- int on;
+ int arg ATTRIBUTE_UNUSED;
+ int on ATTRIBUTE_UNUSED;
{
if (*input_line_pointer != '=')
{
- as_bad ("bad format of OPT NEST=depth");
+ as_bad (_("bad format of OPT NEST=depth"));
return;
}
static void
opt_chip (arg, on)
- int arg;
- int on;
+ int arg ATTRIBUTE_UNUSED;
+ int on ATTRIBUTE_UNUSED;
{
if (*input_line_pointer != '=')
{
static void
opt_list (arg, on)
- int arg;
+ int arg ATTRIBUTE_UNUSED;
int on;
{
listing_list (on);
static void
opt_list_symbols (arg, on)
- int arg;
+ int arg ATTRIBUTE_UNUSED;
int on;
{
if (on)
static void
s_reg (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *s;
int c;
struct m68k_op rop;
- unsigned long mask;
+ int mask;
char *stop = NULL;
char stopc;
if (line_label == NULL)
{
- as_bad ("missing label");
+ as_bad (_("missing label"));
ignore_rest_of_line ();
return;
}
if (m68k_ip_op (s, &rop) != 0)
{
if (rop.error == NULL)
- as_bad ("bad register list");
+ as_bad (_("bad register list"));
else
- as_bad ("bad register list: %s", rop.error);
+ as_bad (_("bad register list: %s"), rop.error);
*input_line_pointer = c;
ignore_rest_of_line ();
return;
mask = 1 << 26;
else
{
- as_bad ("bad register list");
+ as_bad (_("bad register list"));
ignore_rest_of_line ();
return;
}
- S_SET_SEGMENT (line_label, absolute_section);
- S_SET_VALUE (line_label, mask);
- line_label->sy_frag = &zero_address_frag;
+ S_SET_SEGMENT (line_label, reg_section);
+ S_SET_VALUE (line_label, ~mask);
+ symbol_set_frag (line_label, &zero_address_frag);
if (flag_mri)
mri_comment_end (stop, stopc);
static void
s_save (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
struct save_opts *s;
static void
s_restore (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
struct save_opts *s;
if (save_stack == NULL)
{
- as_bad ("restore without save");
+ as_bad (_("restore without save"));
ignore_rest_of_line ();
return;
}
/* Some function prototypes. */
+static void mri_assemble PARAMS ((char *));
static char *mri_control_label PARAMS ((void));
static struct mri_control_info *push_mri_control
PARAMS ((enum mri_control_type));
static void parse_mri_control_expression
PARAMS ((char *, int, const char *, const char *, int));
+/* Assemble an instruction for an MRI structured control directive. */
+
+static void
+mri_assemble (str)
+ char *str;
+{
+ char *s;
+
+ /* md_assemble expects the opcode to be in lower case. */
+ for (s = str; *s != ' ' && *s != '\0'; s++)
+ {
+ if (isupper ((unsigned char) *s))
+ *s = tolower ((unsigned char) *s);
+ }
+
+ md_assemble (str);
+}
+
/* Generate a new MRI label structured control directive label name. */
static char *
if (*input_line_pointer != '>')
{
- as_bad ("syntax error in structured control directive");
+ as_bad (_("syntax error in structured control directive"));
return 0;
}
}
if (*s == '\0')
{
- as_bad ("missing condition code in structured control directive");
+ as_bad (_("missing condition code in structured control directive"));
return 0;
}
cc = reverse_mri_condition (cc);
truelab = falselab;
}
-
+
if (leftstart != NULL)
{
buf = (char *) xmalloc (20
memcpy (s, rightstart, rightstop - rightstart);
s += rightstop - rightstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
}
-
+
buf = (char *) xmalloc (20 + strlen (truelab));
s = buf;
*s++ = 'b';
*s++ = extent;
*s++ = ' ';
strcpy (s, truelab);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
}
*stop = c;
if (input_line_pointer != stop)
- as_bad ("syntax error in structured control directive");
+ as_bad (_("syntax error in structured control directive"));
}
/* Handle the MRI IF pseudo-op. This may be a structured control
{
if (qual != '\0')
{
- as_bad ("missing then");
+ as_bad (_("missing then"));
ignore_rest_of_line ();
return;
}
|| mri_control_stack->type != mri_if
|| mri_control_stack->else_seen)
{
- as_bad ("else without matching if");
+ as_bad (_("else without matching if"));
ignore_rest_of_line ();
return;
}
q[0] = qual;
q[1] = '\0';
sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
colon (mri_control_stack->next);
static void
s_mri_endi (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_if)
{
- as_bad ("endi without matching if");
+ as_bad (_("endi without matching if"));
ignore_rest_of_line ();
return;
}
n = n->outer;
if (n == NULL)
{
- as_bad ("break outside of structured loop");
+ as_bad (_("break outside of structured loop"));
ignore_rest_of_line ();
return;
}
ex[0] = extent;
ex[1] = '\0';
sprintf (buf, "bra%s %s", ex, n->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
if (flag_mri)
n = n->outer;
if (n == NULL)
{
- as_bad ("next outside of structured loop");
+ as_bad (_("next outside of structured loop"));
ignore_rest_of_line ();
return;
}
ex[0] = extent;
ex[1] = '\0';
sprintf (buf, "bra%s %s", ex, n->next);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
if (flag_mri)
++input_line_pointer;
if (*input_line_pointer != '=')
{
- as_bad ("missing =");
+ as_bad (_("missing ="));
ignore_rest_of_line ();
return;
}
}
if (initstop == NULL)
{
- as_bad ("missing to or downto");
+ as_bad (_("missing to or downto"));
ignore_rest_of_line ();
return;
}
}
if (endstop == NULL)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
}
if (bystop == NULL)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
memcpy (s, varstart, varstop - varstart);
s += varstop - varstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
colon (n->top);
memcpy (s, varstart, varstop - varstart);
s += varstop - varstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
/* bcc bottom */
ex[0] = extent;
sprintf (buf, "blt%s %s", ex, n->bottom);
else
sprintf (buf, "bgt%s %s", ex, n->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
/* Put together the add or sub instruction used by ENDF. */
s = buf;
static void
s_mri_endf (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_for)
{
- as_bad ("endf without for");
+ as_bad (_("endf without for"));
ignore_rest_of_line ();
return;
}
colon (mri_control_stack->next);
- md_assemble (mri_control_stack->incr);
+ mri_assemble (mri_control_stack->incr);
sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
- md_assemble (mri_control_stack->incr);
+ mri_assemble (mri_control_stack->incr);
free (mri_control_stack->incr);
static void
s_mri_repeat (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
struct mri_control_info *n;
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_repeat)
{
- as_bad ("until without repeat");
+ as_bad (_("until without repeat"));
ignore_rest_of_line ();
return;
}
if (s - input_line_pointer < 2
|| strncasecmp (s - 1, "DO", 2) != 0)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
static void
s_mri_endw (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *buf;
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_while)
{
- as_bad ("endw without while");
+ as_bad (_("endw without while"));
ignore_rest_of_line ();
return;
}
buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
sprintf (buf, "bra %s", mri_control_stack->next);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
colon (mri_control_stack->bottom);
*
* -pic Indicates PIC.
* -k Indicates PIC. (Sun 3 only.)
+ * --pcrel Never turn PC-relative branches into absolute jumps.
*
* --bitwise-or
* Permit `|' to be used in expressions.
OPTION_REGISTER_PREFIX_OPTIONAL},
#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
{"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
+#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
+ {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
+#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
+ {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
+#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
+ {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
+#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
+ {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
+#define OPTION_PCREL (OPTION_MD_BASE + 7)
+ {"pcrel", no_argument, NULL, OPTION_PCREL},
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
flag_long_jumps = 1;
break;
+ case OPTION_PCREL: /* --pcrel means never turn PC-relative
+ branches into absolute jumps. */
+ flag_keep_pcrel = 1;
+ break;
+
case 'A':
if (*arg == 'm')
arg++;
if (i == n_archs)
{
unknown:
- as_bad ("unrecognized option `%s'", oarg);
+ as_bad (_("unrecognized option `%s'"), oarg);
return 0;
}
arch = archs[i].arch;
}
if (i == n_archs)
{
- as_bad ("unrecognized architecture specification `%s'", arg);
+ as_bad (_("unrecognized architecture specification `%s'"), arg);
return 0;
}
}
}
break;
+ case OPTION_BASE_SIZE_DEFAULT_16:
+ m68k_index_width_default = SIZE_WORD;
+ break;
+
+ case OPTION_BASE_SIZE_DEFAULT_32:
+ m68k_index_width_default = SIZE_LONG;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_16:
+ m68k_rel32 = 0;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_32:
+ m68k_rel32 = 1;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
default:
return 0;
}
md_show_usage (stream)
FILE *stream;
{
- fprintf(stream, "\
+ fprintf (stream, _("\
680X0 options:\n\
-l use 1 word for refs to undefined symbols [default 2]\n\
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
specify variant of 680X0 architecture [default 68020]\n\
-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
target has/lacks floating-point coprocessor\n\
- [default yes for 68020, 68030, and cpu32]\n");
- fprintf(stream, "\
+ [default yes for 68020, 68030, and cpu32]\n"));
+ fprintf (stream, _("\
-m68851 | -mno-68851\n\
target has/lacks memory-management unit coprocessor\n\
[default yes for 68020 and up]\n\
-pic, -k generate position independent code\n\
-S turn jbsr into jsr\n\
+--pcrel never turn PC-relative branches into absolute jumps\n\
--register-prefix-optional\n\
recognize register names without prefix character\n\
---bitwise-or do not treat `|' as a comment character\n");
+--bitwise-or do not treat `|' as a comment character\n"));
+ fprintf (stream, _("\
+--base-size-default-16 base reg without size is 16 bits\n\
+--base-size-default-32 base reg without size is 32 bits (default)\n\
+--disp-size-default-16 displacement with unknown size is 16 bits\n\
+--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
}
\f
#ifdef TEST2
m68k_ip (&the_ins, buf);
if (the_ins.error)
{
- printf ("Error %s in %s\n", the_ins.error, buf);
+ printf (_("Error %s in %s\n"), the_ins.error, buf);
}
else
{
- printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
+ printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
for (n = 0; n < the_ins.numo; n++)
printf (" 0x%x", the_ins.opcode[n] & 0xffff);
printf (" ");
/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
- char *name;
+ char *name ATTRIBUTE_UNUSED;
{
return 0;
}
/* Round up a section size to the appropriate boundary. */
valueT
md_section_align (segment, size)
- segT segment;
+ segT segment ATTRIBUTE_UNUSED;
valueT size;
{
- return size; /* Byte alignment is fine */
+#ifdef OBJ_AOUT
+#ifdef BFD_ASSEMBLER
+ /* For a.out, force the section size to be aligned. If we don't do
+ this, BFD will align it for us, but it will not write out the
+ final bytes of the section. This may be a bug in BFD, but it is
+ easier to fix it here since that is how the other a.out targets
+ work. */
+ int align;
+
+ align = bfd_get_section_alignment (stdoutput, segment);
+ size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
+#endif
+#endif
+
+ return size;
}
/* Exactly what point is a PC-relative offset relative TO?
On the 68k, it is relative to the address of the first extension
word. The difference between the addresses of the offset and the
- first extension word is stored in fx_pcrel_adjust. */
+ first extension word is stored in fx_pcrel_adjust. */
long
md_pcrel_from (fixP)
fixS *fixP;
}
#ifndef BFD_ASSEMBLER
-/*ARGSUSED*/
+#ifdef OBJ_COFF
+
void
tc_coff_symbol_emit_hook (ignore)
- symbolS *ignore;
+ symbolS *ignore ATTRIBUTE_UNUSED;
{
}
return 0;
}
}
-#endif
-/* end of tc-m68k.c */
+#endif
+#endif
+#ifdef OBJ_ELF
+void m68k_elf_final_processing()
+{
+ /* Set file-specific flags if this is a cpu32 processor */
+ if (cpu_of_arch (current_architecture) & cpu32)
+ elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
+}
+#endif
projects / deliverable / binutils-gdb.git / blobdiff