Merge branch 'master' into merge-job

[deliverable/binutils-gdb.git] / gas / config / tc-metag.c

diff --git a/gas/config/tc-metag.c b/gas/config/tc-metag.c
index 3aff54a71c5ddcd832b74f0e1a2fa59067ad8f1d..2816640b29e213eb48315aa728907f0b83ca9aa7 100644 (file)
--- a/gas/config/tc-metag.c
+++ b/gas/config/tc-metag.c
@@ -1,5 +1,5 @@
 /* tc-metag.c -- Assembler for the Imagination Technologies Meta.
-   Copyright (C) 2013-2017 Free Software Foundation, Inc.
+   Copyright (C) 2013-2020 Free Software Foundation, Inc.
    Contributed by Imagination Technologies Ltd.
 
    This file is part of GAS, the GNU Assembler.
@@ -635,7 +635,7 @@ parse_addr_op (const char *line, metag_addr *addr)
   return NULL;
 }
 
-/* Parse the immediate portion of an addrssing mode.  */
+/* Parse the immediate portion of an addressing mode.  */
 static const char *
 parse_imm_addr (const char *line, metag_addr *addr)
 {
@@ -4099,7 +4099,7 @@ __parse_dsp_reg (const char *line, const metag_reg **reg, htab_t dsp_regtab)
   /* We don't entirely strip the register name because we might
      actually want to match whole string in the register table,
      e.g. "D0AW.1++" not just "D0AW.1". The string length of the table
-     entry limits our comaprison to a reasonable bound anyway.  */
+     entry limits our comparison to a reasonable bound anyway.  */
   while (is_register_char (*l) || *l == PLUS)
     {
       name[len] = *l;
@@ -5340,7 +5340,7 @@ parse_dalu (const char *line, metag_insn *insn,
              /* Only MOV instructions have a DSP register as a
                 destination. Set the MOV DSPe.r opcode. The simple
                 OR'ing is OK because the usual MOV opcode is 0x00.  */
-             insn->bits = (0x91 << 24);
+             insn->bits = 0x91u << 24;
              du_shift = 0;
              l1_shift = 2;
              regs_shift[0] = 19;
@@ -5455,7 +5455,7 @@ parse_dalu (const char *line, metag_insn *insn,
                          du_shift = 0;
                          l1_shift = 2;
                          regs_shift[1] = 14;
-                         insn->bits = (0x92 << 24); /* Set opcode.  */
+                         insn->bits = 0x92u << 24; /* Set opcode.  */
                        }
                    }
                }
@@ -5506,7 +5506,7 @@ parse_dalu (const char *line, metag_insn *insn,
          insn->bits |= (1 << 2);
        }
 
-      /* Check for template definitons.  */
+      /* Check for template definitions.  */
       if (IS_TEMPLATE_DEF (insn))
        {
          l = interpret_template_regs(l, insn, regs, regs_shift, &load,
@@ -6705,9 +6705,6 @@ md_number_to_chars (char * buf, valueT val, int n)
    emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
 */
 
-/* Equal to MAX_PRECISION in atof-ieee.c */
-#define MAX_LITTLENUMS 6
-
 const char *
 md_atof (int type, char * litP, int * sizeP)
 {