/* tc-mt.c -- Assembler for the Morpho Technologies mt .
- Copyright (C) 2005, 2006, 2007 Free Software Foundation.
+ Copyright (C) 2005-2020 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#include "as.h"
#include "dwarf2dbg.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/mt-desc.h"
#include "opcodes/mt-opc.h"
#include "cgen.h"
#include "elf/common.h"
#include "elf/mt.h"
-#include "libbfd.h"
/* Structure to hold all of the different components
describing an individual instruction. */
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
/* The target specific pseudo-ops which we support. */
const pseudo_typeS md_pseudo_table[] =
{
- { "word", cons, 4 },
+ { "word", cons, 4 },
{ NULL, NULL, 0 }
};
static int no_scheduling_restrictions = 0;
-struct option md_longopts[] =
+struct option md_longopts[] =
{
#define OPTION_NO_SCHED_REST (OPTION_MD_BASE)
{ "nosched", no_argument, NULL, OPTION_NO_SCHED_REST },
static enum mt_architectures mt_arch = ms1_16_002;
int
-md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
+md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg)
{
switch (c)
{
mt_mach_bitmask = 1 << MACH_MS2;
mt_arch = ms2;
}
+ break;
case OPTION_NO_SCHED_REST:
no_scheduling_restrictions = 1;
break;
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask,
CGEN_CPU_OPEN_ENDIAN,
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
+
+ literal_prefix_dollar_hex = TRUE;
}
void
&& insn.fields.f_sr1 == delayed_load_register)
|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
&& insn.fields.f_sr2 == delayed_load_register))
- as_warn (_("operand references R%ld of previous instrutcion."),
+ as_warn (_("operand references R%ld of previous instruction."),
delayed_load_register);
else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
&& insn.fields.f_sr1 == prev_delayed_load_register)
|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
&& insn.fields.f_sr2 == prev_delayed_load_register))
- as_warn (_("operand references R%ld of instructcion before previous."),
+ as_warn (_("operand references R%ld of instruction before previous."),
prev_delayed_load_register);
}
-
+
/* Detect data dependency between conditional branch instruction
and an immediately preceding arithmetic or logical instruction. */
if (last_insn_was_arithmetic_or_logic
last_insn_had_delay_slot =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
+ (void) last_insn_had_delay_slot;
last_insn_has_load_delay =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY);
last_insn_was_branch_insn =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN);
-
+
last_insn_was_conditional_branch_insn =
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
-
+
prev_delayed_load_register = delayed_load_register;
-
+
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
- delayed_load_register = insn.fields.f_dr;
+ delayed_load_register = insn.fields.f_dr;
else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
- delayed_load_register = insn.fields.f_drrr;
+ delayed_load_register = insn.fields.f_drrr;
else /* Insns has no destination register. */
- delayed_load_register = 0;
+ delayed_load_register = 0;
/* Generate dwarf2 line numbers. */
- dwarf2_emit_insn (4);
+ dwarf2_emit_insn (4);
}
valueT
md_section_align (segT segment, valueT size)
{
- int align = bfd_get_section_alignment (stdoutput, segment);
+ int align = bfd_section_alignment (segment);
- return ((size + (1 << align) - 1) & (-1 << align));
+ return ((size + (1 << align) - 1) & -(1 << align));
}
symbolS *
{
as_fatal (_("md_estimate_size_before_relax\n"));
return 1;
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
number_to_chars_bigendian (buf, val, n);
}
-char *
+const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
bfd_boolean
mt_fix_adjustable (fixS * fixP)
{
- bfd_reloc_code_real_type reloc_type;
-
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
{
const CGEN_INSN *insn = NULL;
const CGEN_OPERAND *operand;
operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
- reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+ md_cgen_lookup_reloc (insn, operand, fixP);
}
- else
- reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
return TRUE;
-
+
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return FALSE;
-
+
if (S_IS_WEAK (fixP->fx_addsy))
return FALSE;
-
+
return 1;
}