/* tc-sparc.c -- Assemble for the SPARC
- Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc.
+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+ 1999, 2000, 2001
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
You should have received a copy of the GNU General Public
License along with GAS; see the file COPYING. If not, write
to the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include <ctype.h>
#ifdef OBJ_ELF
#include "elf/sparc.h"
+#include "dwarf2dbg.h"
#endif
static struct sparc_arch *lookup_arch PARAMS ((char *));
architecture, issue a warning. */
static enum sparc_opcode_arch_val warn_after_architecture;
+/* Non-zero if as should generate error if an undeclared g[23] register
+ has been used in -64. */
+static int no_undeclared_regs;
+
+/* Non-zero if we should try to relax jumps and calls. */
+static int sparc_relax;
+
/* Non-zero if we are generating PIC code. */
int sparc_pic_code;
static int target_little_endian_data;
+/* Symbols for global registers on v9. */
+static symbolS *globals[8];
+
/* V9 and 86x have big and little endian data, but instructions are always big
endian. The sparclet has bi-endian support but both data and insns have
the same endianness. Global `target_big_endian' is used for data.
|| SPARC_OPCODE_ARCH_V9_P (max_architecture))
#endif
-/* handle of the OPCODE hash table */
+/* Handle of the OPCODE hash table. */
static struct hash_control *op_hash;
static int log2 PARAMS ((int));
static void s_empty PARAMS ((int));
static void s_uacons PARAMS ((int));
static void s_ncons PARAMS ((int));
+static void s_register PARAMS ((int));
const pseudo_typeS md_pseudo_table[] =
{
- {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
+ {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
{"common", s_common, 0},
{"empty", s_empty, 0},
{"global", s_globl, 0},
{"uaword", s_uacons, 4},
{"uaxword", s_uacons, 8},
#ifdef OBJ_ELF
- /* these are specific to sparc/svr4 */
- {"pushsection", obj_elf_section, 0},
- {"popsection", obj_elf_previous, 0},
+ {"file", dwarf2_directive_file, 0},
+ {"loc", dwarf2_directive_loc, 0},
+ /* These are specific to sparc/svr4. */
{"2byte", s_uacons, 2},
{"4byte", s_uacons, 4},
{"8byte", s_uacons, 8},
+ {"register", s_register, 0},
#endif
{NULL, 0, 0},
};
-const int md_reloc_size = 12; /* Size of relocation record */
+/* Size of relocation record. */
+const int md_reloc_size = 12;
/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful */
-const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
+ pre-processor is disabled, these aren't very useful. */
+const char comment_chars[] = "!"; /* JF removed '|' from
+ comment_chars. */
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
- .line and .file directives will appear in the pre-processed output */
+ .line and .file directives will appear in the pre-processed output. */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
+ #NO_APP at the beginning of its output. */
/* Also note that comments started like this one will always
- work if '/' isn't otherwise defined. */
+ work if '/' isn't otherwise defined. */
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = ";";
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point
+ nums. */
const char EXP_CHARS[] = "eE";
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or 0d1.2345e12 */
+/* Chars that mean this number is a floating point constant.
+ As in 0f12.456
+ or 0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
changed in read.c. Ideally it shouldn't have to know about it at all,
but nothing is ideal around here. */
-#define isoctal(c) ((unsigned)((c) - '0') < '8')
+#define isoctal(c) ((unsigned) ((c) - '0') < '8')
struct sparc_it
{
and file formats. */
enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
- v8plusa, v9, v9a, v9_64};
+ v8plusa, v9, v9a, v9b, v9_64};
static struct sparc_arch {
char *name;
{ "sparc86x", "sparclite", sparc86x, 32, 1 },
{ "v8plus", "v9", v9, 0, 1 },
{ "v8plusa", "v9a", v9, 0, 1 },
+ { "v8plusb", "v9b", v9, 0, 1 },
{ "v9", "v9", v9, 0, 1 },
{ "v9a", "v9a", v9, 0, 1 },
+ { "v9b", "v9b", v9, 0, 1 },
/* This exists to allow configure.in/Makefile.in to pass one
value to specify both the default machine and default word size. */
{ "v9-64", "v9", v9, 64, 0 },
return "a.out-sunos-big";
else if (default_arch_type == sparc86x && target_little_endian_data)
return "a.out-sunos-big";
- else return "a.out-sparc-little";
+ else
+ return "a.out-sparc-little";
#else
return "a.out-sunos-big";
#endif
abort ();
}
\f
-/*
- * md_parse_option
+/* md_parse_option
* Invocation line includes a switch not recognized by the base assembler.
* See if it's a processor-specific option. These are:
*
*
* -Av6, -Av7, -Av8, -Asparclite, -Asparclet
* Standard 32 bit architectures.
- * -Av8plus, -Av8plusa
- * Sparc64 in a 32 bit world.
- * -Av9, -Av9a
+ * -Av9, -Av9a, -Av9b
* Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
* This used to only mean 64 bits, but properly specifying it
* complicated gcc's ASM_SPECs, so now opcode selection is
* specified orthogonally to word size (except when specifying
* the default, but that is an internal implementation detail).
- * -xarch=v8plus, -xarch=v8plusa
- * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
+ * -Av8plus, -Av8plusa, -Av8plusb
+ * Same as -Av9{,a,b}.
+ * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
+ * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
+ * assembler.
+ * -xarch=v9, -xarch=v9a, -xarch=v9b
+ * Same as -Av9{,a,b} -64, for compatibility with Sun's
+ * assembler.
*
* Select the architecture and possibly the file format.
* Instructions or features not supported by the selected
* The default is to start at v6, and bump the architecture up
* whenever an instruction is seen at a higher level. In 32 bit
* environments, v9 is not bumped up to, the user must pass
- * -Av8plus{,a}.
+ * -Av8plus{,a,b}.
*
* If -bump is specified, a warning is printing when bumping to
* higher levels.
{"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
{"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
+#ifdef OBJ_ELF
+#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
+ {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
+#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
+ {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
+#endif
+#define OPTION_RELAX (OPTION_MD_BASE + 14)
+ {"relax", no_argument, NULL, OPTION_RELAX},
+#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
+ {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+
+size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
break;
case OPTION_XARCH:
- /* This is for compatibility with Sun's assembler. */
- if (strcmp (arg, "v8plus") != 0
- && strcmp (arg, "v8plusa") != 0)
- {
- as_bad (_("invalid architecture -xarch=%s"), arg);
- return 0;
- }
-
- /* fall through */
+#ifdef OBJ_ELF
+ if (strncmp (arg, "v9", 2) != 0)
+ md_parse_option (OPTION_32, NULL);
+ else
+ md_parse_option (OPTION_64, NULL);
+#endif
+ /* Fall through. */
case 'A':
{
if (sa == NULL
|| ! sa->user_option_p)
{
- as_bad (_("invalid architecture -A%s"), arg);
+ if (c == OPTION_XARCH)
+ as_bad (_("invalid architecture -xarch=%s"), arg);
+ else
+ as_bad (_("invalid architecture -A%s"), arg);
return 0;
}
case 'Q':
/* Qy - do emit .comment
- Qn - do not emit .comment */
+ Qn - do not emit .comment. */
break;
case 's':
- /* use .stab instead of .stab.excl */
+ /* Use .stab instead of .stab.excl. */
break;
case 'q':
- /* quick -- native assembler does fewer checks */
+ /* quick -- Native assembler does fewer checks. */
break;
case 'K':
else
sparc_pic_code = 1;
break;
+
+ case OPTION_NO_UNDECLARED_REGS:
+ no_undeclared_regs = 1;
+ break;
+
+ case OPTION_UNDECLARED_REGS:
+ no_undeclared_regs = 0;
+ break;
#endif
+ case OPTION_RELAX:
+ sparc_relax = 1;
+ break;
+
+ case OPTION_NO_RELAX:
+ sparc_relax = 0;
+ break;
+
default:
return 0;
}
FILE *stream;
{
const struct sparc_arch *arch;
+ int column;
/* We don't get a chance to initialize anything before we're called,
so handle that now. */
if (! default_init_p)
init_default_arch ();
- fprintf(stream, _("SPARC options:\n"));
+ fprintf (stream, _("SPARC options:\n"));
+ column = 0;
for (arch = &sparc_arch_table[0]; arch->name; arch++)
{
+ if (!arch->user_option_p)
+ continue;
if (arch != &sparc_arch_table[0])
fprintf (stream, " | ");
- if (arch->user_option_p)
- fprintf (stream, "-A%s", arch->name);
+ if (column + strlen(arch->name) > 70)
+ {
+ column = 0;
+ fputc ('\n', stream);
+ }
+ column += 5 + 2 + strlen(arch->name);
+ fprintf (stream, "-A%s", arch->name);
}
- fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
- fprintf (stream, _("\
+ for (arch = &sparc_arch_table[0]; arch->name; arch++)
+ {
+ if (!arch->user_option_p)
+ continue;
+ fprintf (stream, " | ");
+ if (column + strlen(arch->name) > 65)
+ {
+ column = 0;
+ fputc ('\n', stream);
+ }
+ column += 5 + 7 + strlen(arch->name);
+ fprintf (stream, "-xarch=%s", arch->name);
+ }
+ fprintf (stream, _("\n\
specify variant of SPARC architecture\n\
-bump warn when assembler switches architectures\n\
-sparc ignored\n\
---enforce-aligned-data force .long, etc., to be aligned correctly\n"));
+--enforce-aligned-data force .long, etc., to be aligned correctly\n\
+-relax relax jumps and branches (default)\n\
+-no-relax avoid changing any jumps and branches\n"));
#ifdef OBJ_AOUT
fprintf (stream, _("\
-k generate PIC\n"));
fprintf (stream, _("\
-KPIC generate PIC\n\
-V print assembler version number\n\
+-undeclared-regs ignore application global register usage without\n\
+ appropriate .register directive (default)\n\
+-no-undeclared-regs force error on application global register usage\n\
+ without appropriate .register directive\n\
-q ignored\n\
-Qy, -Qn ignored\n\
-s ignored\n"));
-EL generate code for a little endian machine\n\
-EB generate code for a big endian machine\n\
--little-endian-data generate code for a machine having big endian\n\
- instructions and little endian data."));
+ instructions and little endian data.\n"));
#endif
}
\f
-/* native operand size opcode translation */
+/* Native operand size opcode translation. */
struct
{
char *name;
{NULL, NULL, NULL},
};
\f
-/* sparc64 priviledged registers */
+/* sparc64 priviledged registers. */
struct priv_reg_entry
- {
- char *name;
- int regnum;
- };
+{
+ char *name;
+ int regnum;
+};
struct priv_reg_entry priv_reg_table[] =
{
{"wstate", 14},
{"fq", 15},
{"ver", 31},
- {"", -1}, /* end marker */
+ {"", -1}, /* End marker. */
};
-/* v9a specific asrs */
+/* v9a specific asrs. */
struct priv_reg_entry v9a_asr_table[] =
{
{"tick_cmpr", 23},
+ {"sys_tick_cmpr", 25},
+ {"sys_tick", 24},
{"softint", 22},
{"set_softint", 20},
{"pic", 17},
{"gsr", 19},
{"dcr", 18},
{"clear_softint", 21},
- {"", -1}, /* end marker */
+ {"", -1}, /* End marker. */
};
static int
}
\f
/* This function is called once, at assembler startup time. It should
- set up all the tables, etc. that the MD part of the assembler will need. */
+ set up all the tables, etc. that the MD part of the assembler will
+ need. */
void
md_begin ()
for (i = 0; native_op_table[i].name; i++)
{
const struct sparc_opcode *insn;
- char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
- native_op_table[i].name64;
- insn = (struct sparc_opcode *)hash_find (op_hash, name);
+ char *name = ((sparc_arch_size == 32)
+ ? native_op_table[i].name32
+ : native_op_table[i].name64);
+ insn = (struct sparc_opcode *) hash_find (op_hash, name);
if (insn == NULL)
- {
- as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
- name, native_op_table[i].name);
- lose = 1;
- }
+ {
+ as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
+ name, native_op_table[i].name);
+ lose = 1;
+ }
else
{
retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
void
sparc_md_end ()
{
+ unsigned long mach = bfd_mach_sparc;
+
if (sparc_arch_size == 64)
- {
- if (current_architecture == SPARC_OPCODE_ARCH_V9A)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
- else
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
- }
+ switch (current_architecture)
+ {
+ case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
+ case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
+ default: mach = bfd_mach_sparc_v9; break;
+ }
else
- {
- if (current_architecture == SPARC_OPCODE_ARCH_V9)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
- else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
- else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
- else if (default_arch_type == sparc86x && target_little_endian_data)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
- else
- {
- /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
- be but for now it is (since that's the way it's always been
- treated). */
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
- }
- }
+ switch (current_architecture)
+ {
+ case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
+ case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
+ case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
+ case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
+ /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
+ be but for now it is (since that's the way it's always been
+ treated). */
+ default: break;
+ }
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
}
\f
/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
0xffffffff is always considered -1 on sparc32. */
if (sparc_arch_size == 32)
{
- bfd_signed_vma sign = (bfd_signed_vma)1 << 31;
+ bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
val = ((val & 0xffffffff) ^ sign) - sign;
}
if (val > max)
static unsigned long last_opcode;
\f
/* Handle the set and setuw synthetic instructions. */
+
static void
synthetize_setuw (insn)
const struct sparc_opcode *insn;
{
if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
{
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < 0
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("set: number not in 0..4294967295 range"));
}
else
{
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < -(offsetT) 0x80000000
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("set: number not in -2147483648..4294967295 range"));
- the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number;
+ the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
}
}
{
the_insn.opcode = (SETHI_INSN | RD (rd)
| ((the_insn.exp.X_add_number >> 10)
- & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0)));
+ & (the_insn.exp.X_op == O_constant
+ ? 0x3fffff : 0)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
- ? BFD_RELOC_HI22
- : BFD_RELOC_NONE);
+ ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
need_hi22_p = 1;
}
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
| RD (rd) | IMMED
| (the_insn.exp.X_add_number
- & (the_insn.exp.X_op != O_constant ? 0 :
- need_hi22_p ? 0x3ff : 0x1fff)));
+ & (the_insn.exp.X_op != O_constant
+ ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
- ? BFD_RELOC_LO10
- : BFD_RELOC_NONE);
+ ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
}
-
+
/* Handle the setsw synthetic instruction. */
+
static void
synthetize_setsw (insn)
const struct sparc_opcode *insn;
return;
}
- if (sizeof(offsetT) > 4
+ if (sizeof (offsetT) > 4
&& (the_insn.exp.X_add_number < -(offsetT) 0x80000000
|| the_insn.exp.X_add_number > (offsetT) 0xffffffff))
as_warn (_("setsw: number not in -2147483648..4294967295 range"));
- low32 = the_insn.exp.X_add_number;
-
+ low32 = the_insn.exp.X_add_number;
+
if (low32 >= 0)
{
synthetize_setuw (insn);
}
opc = OR_INSN;
-
+
the_insn.reloc = BFD_RELOC_NONE;
/* See if operand is absolute and small; skip sethi if so. */
if (low32 < -(1 << 12))
}
/* Handle the setsw synthetic instruction. */
+
static void
synthetize_setx (insn)
const struct sparc_opcode *insn;
int upper_dstreg;
int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
int need_xor10_p = 0;
-
+
#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
return;
}
need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
- lower32 = 0; upper32 = 0;
+ lower32 = 0;
+ upper32 = 0;
}
else
{
Otherwise fixup_segment will complain about not being able to
write an 8 byte number in a 4 byte field. */
the_insn.exp.X_add_number = 0;
-
+
/* Only need hh22 if `or' insn can't handle constant. */
if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
need_hh22_p = 1;
-
+
/* Does bottom part (after sethi) have bits? */
if ((need_hh22_p && (upper32 & 0x3ff) != 0)
/* No hh22, but does upper32 still have bits we can't set
from lower32? */
|| (! need_hh22_p && upper32 != 0 && upper32 != -1))
need_hm10_p = 1;
-
+
/* If the lower half is all zero, we build the upper half directly
into the dst reg. */
if (lower32 != 0
|| (lower32 < 0 && upper32 != -1)
|| (lower32 >= 0 && upper32 == -1))
need_hi22_p = 1;
-
+
if (need_hi22_p && upper32 == -1)
need_xor10_p = 1;
/* Output directly to dst reg if lower 32 bits are all zero. */
upper_dstreg = dstreg;
}
-
+
if (!upper_dstreg && dstreg)
as_warn (_("setx: illegal temporary register g0"));
? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
if (need_hi22_p)
{
the_insn.opcode = (SETHI_INSN | RD (dstreg)
| (((need_xor10_p ? ~lower32 : lower32)
- >> 10) & 0x3fffff));
+ >> 10) & 0x3fffff));
the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
if (need_lo10_p)
{
/* FIXME: One nice optimization to do here is to OR the low part
? BFD_RELOC_LO10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
-
+
/* If we needed to build the upper part, shift it into place. */
if (need_hh22_p || need_hm10_p)
{
the_insn.reloc = BFD_RELOC_NONE;
output_insn (insn, &the_insn);
}
-
+
/* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
if (need_xor10_p)
{
switch (special_case)
{
case SPECIAL_CASE_NONE:
- /* normal insn */
+ /* Normal insn. */
output_insn (insn, &the_insn);
break;
case SPECIAL_CASE_SETSW:
synthetize_setsw (insn);
break;
-
+
case SPECIAL_CASE_SET:
synthetize_setuw (insn);
break;
case SPECIAL_CASE_SETX:
synthetize_setx (insn);
break;
-
+
case SPECIAL_CASE_FDIV:
{
int rd = (the_insn.opcode >> 25) & 0x1f;
-
+
output_insn (insn, &the_insn);
-
+
/* According to information leaked from Sun, the "fdiv" instructions
on early SPARC machines would produce incorrect results sometimes.
The workaround is to add an fmovs of the destination register to
itself just after the instruction. This was true on machines
- with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
+ with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
assert (the_insn.reloc == BFD_RELOC_NONE);
the_insn.opcode = FMOVS_INSN | rd | RD (rd);
output_insn (insn, &the_insn);
return;
}
-
+
default:
as_fatal (_("failed special case insn sanity check"));
}
case ',':
comma = 1;
-
- /*FALLTHROUGH */
+ /* Fall through. */
case ' ':
*s++ = '\0';
the_insn.reloc = BFD_RELOC_NONE;
v9_arg_p = 0;
- /*
- * Build the opcode, checking as we go to make
- * sure that the operands match
- */
+ /* Build the opcode, checking as we go to make sure that the
+ operands match. */
for (args = insn->args;; ++args)
{
switch (*args)
goto error;
}
kmask |= mask;
- while (*s == ' ') { ++s; continue; }
+ while (*s == ' ')
+ ++s;
if (*s == '|' || *s == '+')
++s;
- while (*s == ' ') { ++s; continue; }
+ while (*s == ' ')
+ ++s;
}
}
else
continue;
}
+ case '3':
+ {
+ int smask = 0;
+
+ if (! parse_const_expr_arg (&s, &smask))
+ {
+ error_message = _(": invalid siam mode expression");
+ goto error;
+ }
+ if (smask < 0 || smask > 7)
+ {
+ error_message = _(": invalid siam mode number");
+ goto error;
+ }
+ opcode |= smask;
+ continue;
+ }
+
case '*':
{
int fcn = 0;
if (*s == '%')
{
struct priv_reg_entry *p = priv_reg_table;
- unsigned int len = 9999999; /* init to make gcc happy */
+ unsigned int len = 9999999; /* Init to make gcc happy. */
s += 1;
while (p->name[0] > s[0])
case '_':
case '/':
- /* Parse a v9a ancillary state register. */
+ /* Parse a v9a/v9b ancillary state register. */
if (*s == '%')
{
struct priv_reg_entry *p = v9a_asr_table;
- unsigned int len = 9999999; /* init to make gcc happy */
+ unsigned int len = 9999999; /* Init to make gcc happy. */
s += 1;
while (p->name[0] > s[0])
}
if (p->name[0] != s[0])
{
- error_message = _(": unrecognizable v9a ancillary state register");
+ error_message = _(": unrecognizable v9a or v9b ancillary state register");
goto error;
}
if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
{
error_message = _(": rd on write only ancillary state register");
goto error;
- }
+ }
+ if (p->regnum >= 24
+ && (insn->architecture
+ & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
+ {
+ /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
+ error_message = _(": unrecognizable v9a ancillary state register");
+ goto error;
+ }
if (*args == '/')
opcode |= (p->regnum << 14);
else
}
else
{
- error_message = _(": unrecognizable v9a ancillary state register");
+ error_message = _(": unrecognizable v9a or v9b ancillary state register");
goto error;
}
error_message = _(": expecting %asrN");
goto error;
}
- } /* if %asr */
+ } /* if %asr */
break;
case 'I':
}
break;
- case '\0': /* end of args */
+ case '\0': /* End of args. */
if (*s == '\0')
{
match = 1;
}
break;
- case '[': /* these must match exactly */
+ case '[': /* These must match exactly. */
case ']':
case ',':
case ' ':
continue;
break;
- case '#': /* must be at least one digit */
+ case '#': /* Must be at least one digit. */
if (isdigit ((unsigned char) *s++))
{
while (isdigit ((unsigned char) *s))
}
break;
- case 'C': /* coprocessor state register */
+ case 'C': /* Coprocessor state register. */
if (strncmp (s, "%csr", 4) == 0)
{
s += 4;
}
break;
- case 'b': /* next operand is a coprocessor register */
+ case 'b': /* Next operand is a coprocessor register. */
case 'c':
case 'D':
if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
goto error;
}
+ if ((mask & ~1) == 2 && sparc_arch_size == 64
+ && no_undeclared_regs && ! globals[mask])
+ as_bad (_("detected global register use not covered by .register pseudo-op"));
+
/* Got the register, now figure out where
it goes in the opcode. */
switch (*args)
else
{
break;
- } /* if not an 'f' register. */
+ } /* if not an 'f' register. */
switch (*args)
{
opcode |= RS1 (mask);
continue;
-
case 'f':
case 'B':
case 'R':
case 'J':
opcode |= RD (mask);
continue;
- } /* pack it in. */
+ } /* Pack it in. */
know (0);
break;
- } /* float arg */
+ } /* float arg */
case 'F':
if (strncmp (s, "%fsr", 4) == 0)
}
break;
- case '0': /* 64 bit immediate (set, setsw, setx insn) */
- the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
+ case '0': /* 64 bit immediate (set, setsw, setx insn) */
+ the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
goto immediate;
- case 'l': /* 22 bit PC relative immediate */
+ case 'l': /* 22 bit PC relative immediate */
the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
the_insn.pcrel = 1;
goto immediate;
- case 'L': /* 30 bit immediate */
+ case 'L': /* 30 bit immediate */
the_insn.reloc = BFD_RELOC_32_PCREL_S2;
the_insn.pcrel = 1;
goto immediate;
case 'h':
- case 'n': /* 22 bit immediate */
+ case 'n': /* 22 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC22;
goto immediate;
- case 'i': /* 13 bit immediate */
+ case 'i': /* 13 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC13;
/* fallthrough */
{ "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
{ "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
{ "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
- { NULL }
+ { NULL, 0, 0, 0, 0 }
};
const struct ops *o;
-
+
for (o = ops; o->name; o++)
if (strncmp (s + 1, o->name, o->len) == 0)
break;
if (o->name == NULL)
break;
-
+
if (s[o->len + 1] != '(')
{
as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
return special_case;
}
-
+
*s1 = '\0';
(void) get_expression (s);
*s1 = ')';
*s1 = '0';
s = s1;
op_exp = the_insn.exp;
- memset (&the_insn.exp, 0, sizeof(the_insn.exp));
+ memset (&the_insn.exp, 0, sizeof (the_insn.exp));
}
- for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
+ for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
+ ;
if (s1 != s && isdigit ((unsigned char) s1[-1]))
{
if (s1)
{
*s1 = '\0';
- (void) get_expression (s);
+ if (op_arg && s1 == s + 1)
+ the_insn.exp.X_op = O_absent;
+ else
+ (void) get_expression (s);
*s1 = '+';
if (op_arg)
*s = ')';
case BFD_RELOC_SPARC_HH22:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_SPARC_LM22:
case BFD_RELOC_HI22:
case BFD_RELOC_SPARC_HM10:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_LO10:
val &= 0x3ff;
break;
case BFD_RELOC_SPARC_HIX22:
- val = ~ val;
+ val = ~val;
val = (val >> 10) & 0x3fffff;
break;
}
else
{
- if (1 || old_reloc != BFD_RELOC_SPARC13
+ if (old_reloc != BFD_RELOC_SPARC13
|| the_insn.reloc != BFD_RELOC_LO10
|| sparc_arch_size != 64
|| sparc_pic_code)
}
opcode |= ASI (asi);
continue;
- } /* alternate space */
+ } /* Alternate space. */
case 'p':
if (strncmp (s, "%psr", 4) == 0)
}
break;
- case 'q': /* floating point queue */
+ case 'q': /* Floating point queue. */
if (strncmp (s, "%fq", 3) == 0)
{
s += 3;
}
break;
- case 'Q': /* coprocessor queue */
+ case 'Q': /* Coprocessor queue. */
if (strncmp (s, "%cq", 3) == 0)
{
s += 3;
default:
as_fatal (_("failed sanity check."));
- } /* switch on arg code */
+ } /* switch on arg code. */
/* Break out of for() loop. */
break;
- } /* for each arg that we expect */
+ } /* For each arg that we expect. */
error:
if (match == 0)
{
- /* Args don't match. */
+ /* Args don't match. */
if (&insn[1] - sparc_opcodes < sparc_num_opcodes
&& (insn->name == insn[1].name
|| !strcmp (insn->name, insn[1].name)))
}
else
{
- /* We have a match. Now see if the architecture is ok. */
+ /* We have a match. Now see if the architecture is OK. */
int needed_arch_mask = insn->architecture;
if (v9_arg_p)
{
- needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
- | (1 << SPARC_OPCODE_ARCH_V9A));
- needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
+ needed_arch_mask &=
+ ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
+ if (! needed_arch_mask)
+ needed_arch_mask =
+ SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
}
- if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
- ; /* ok */
+ if (needed_arch_mask
+ & SPARC_OPCODE_SUPPORTED (current_architecture))
+ /* OK. */
+ ;
/* Can we bump up the architecture? */
- else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
+ else if (needed_arch_mask
+ & SPARC_OPCODE_SUPPORTED (max_architecture))
{
enum sparc_opcode_arch_val needed_architecture =
sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
happen but what about tomorrow? */
else
{
- int arch,printed_one_p = 0;
+ int arch, printed_one_p = 0;
char *p;
char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
/* Create a list of the architectures that support the insn. */
- needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
+ needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
p = required_archs;
arch = sparc_ffs (needed_arch_mask);
while ((1 << arch) <= needed_arch_mask)
sparc_opcode_archs[max_architecture].name);
return special_case;
}
- } /* if no match */
+ } /* If no match. */
break;
- } /* forever looking for a match */
+ } /* Forever looking for a match. */
the_insn.opcode = opcode;
return special_case;
{
char *toP = frag_more (4);
- /* put out the opcode */
+ /* Put out the opcode. */
if (INSN_BIG_ENDIAN)
number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
else
number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
- /* put out the symbol-dependent stuff */
+ /* Put out the symbol-dependent stuff. */
if (the_insn->reloc != BFD_RELOC_NONE)
{
- fixS *fixP = fix_new_exp (frag_now, /* which frag */
- (toP - frag_now->fr_literal), /* where */
- 4, /* size */
+ fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
+ (toP - frag_now->fr_literal), /* Where. */
+ 4, /* Size. */
&the_insn->exp,
the_insn->pcrel,
the_insn->reloc);
the insn size is 4 and fixup_segment will signal an overflow for
large 8 byte quantities. */
fixP->fx_no_overflow = 1;
+ if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
+ fixP->tc_fix_data = the_insn->exp2.X_add_number;
}
last_insn = insn;
last_opcode = the_insn->opcode;
+
+#ifdef OBJ_ELF
+ dwarf2_emit_insn (4);
+#endif
}
\f
-/*
- This is identical to the md_atof in m68k.c. I think this is right,
- but I'm not sure.
+/* This is identical to the md_atof in m68k.c. I think this is right,
+ but I'm not sure.
- Turn a string in input_line_pointer into a floating point constant of type
- type, and store the appropriate bytes in *litP. The number of LITTLENUMS
- emitted is stored in *sizeP . An error message is returned, or NULL on OK.
- */
+ Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
char *
char *litP;
int *sizeP;
{
- int i,prec;
+ int i, prec;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
char *t;
{
for (i = 0; i < prec; i++)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
{
for (i = prec - 1; i >= 0; i--)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
-
+
return 0;
}
number_to_chars_bigendian (buf, val, n);
else if (target_little_endian_data
&& ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
- /* Output debug words, which are not in allocated sections, as big endian */
+ /* Output debug words, which are not in allocated sections, as big
+ endian. */
number_to_chars_bigendian (buf, val, n);
else if (target_little_endian_data || ! target_big_endian)
number_to_chars_littleendian (buf, val, n);
}
\f
/* Apply a fixS to the frags, now that we know the value it ought to
- hold. */
+ hold. */
int
md_apply_fix3 (fixP, value, segment)
assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
- fixP->fx_addnumber = val; /* Remember value for emit_reloc */
+ fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
#ifdef OBJ_ELF
/* FIXME: SPARC ELF relocations don't use an addend in the data
{
md_number_to_chars (buf, val, 8);
}
- else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
{
fixP->fx_done = 0;
insn = bfd_getb32 ((unsigned char *) buf);
else
insn = bfd_getl32 ((unsigned char *) buf);
-
+
switch (fixP->fx_r_type)
{
case BFD_RELOC_32_PCREL_S2:
|| fixP->fx_addsy == NULL
|| symbol_section_p (fixP->fx_addsy))
++val;
+
insn |= val & 0x3fffffff;
+
+ /* See if we have a delay slot. */
+ if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
+ {
+#define G0 0
+#define O7 15
+#define XCC (2 << 20)
+#define COND(x) (((x)&0xf)<<25)
+#define CONDA COND(0x8)
+#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
+#define INSN_BA (F2(0,2) | CONDA)
+#define INSN_OR F3(2, 0x2, 0)
+#define INSN_NOP F2(0,4)
+
+ long delay;
+
+ /* If the instruction is a call with either:
+ restore
+ arithmetic instruction with rd == %o7
+ where rs1 != %o7 and rs2 if it is register != %o7
+ then we can optimize if the call destination is near
+ by changing the call into a branch always. */
+ if (INSN_BIG_ENDIAN)
+ delay = bfd_getb32 ((unsigned char *) buf + 4);
+ else
+ delay = bfd_getl32 ((unsigned char *) buf + 4);
+ if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
+ break;
+ if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
+ && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
+ || ((delay & RD (~0)) != RD (O7))))
+ break;
+ if ((delay & RS1 (~0)) == RS1 (O7)
+ || ((delay & F3I (~0)) == 0
+ && (delay & RS2 (~0)) == RS2 (O7)))
+ break;
+ /* Ensure the branch will fit into simm22. */
+ if ((val & 0x3fe00000)
+ && (val & 0x3fe00000) != 0x3fe00000)
+ break;
+ /* Check if the arch is v9 and branch will fit
+ into simm19. */
+ if (((val & 0x3c0000) == 0
+ || (val & 0x3c0000) == 0x3c0000)
+ && (sparc_arch_size == 64
+ || current_architecture >= SPARC_OPCODE_ARCH_V9))
+ /* ba,pt %xcc */
+ insn = INSN_BPA | (val & 0x7ffff);
+ else
+ /* ba */
+ insn = INSN_BA | (val & 0x3fffff);
+ if (fixP->fx_where >= 4
+ && ((delay & (0xffffffff ^ RS1 (~0)))
+ == (INSN_OR | RD (O7) | RS2 (G0))))
+ {
+ long setter;
+ int reg;
+
+ if (INSN_BIG_ENDIAN)
+ setter = bfd_getb32 ((unsigned char *) buf - 4);
+ else
+ setter = bfd_getl32 ((unsigned char *) buf - 4);
+ if ((setter & (0xffffffff ^ RD (~0)))
+ != (INSN_OR | RS1 (O7) | RS2 (G0)))
+ break;
+ /* The sequence was
+ or %o7, %g0, %rN
+ call foo
+ or %rN, %g0, %o7
+
+ If call foo was replaced with ba, replace
+ or %rN, %g0, %o7 with nop. */
+ reg = (delay & RS1 (~0)) >> 14;
+ if (reg != ((setter & RD (~0)) >> 25)
+ || reg == G0 || reg == O7)
+ break;
+
+ if (INSN_BIG_ENDIAN)
+ bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
+ else
+ bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
+ }
+ }
break;
case BFD_RELOC_SPARC_11:
break;
case BFD_RELOC_SPARC_WDISP16:
- /* FIXME: simplify */
+ /* FIXME: simplify. */
if (((val > 0) && (val & ~0x3fffc))
|| ((val < 0) && (~(val - 1) & ~0x3fffc)))
as_bad_where (fixP->fx_file, fixP->fx_line,
break;
case BFD_RELOC_SPARC_WDISP19:
- /* FIXME: simplify */
+ /* FIXME: simplify. */
if (((val > 0) && (val & ~0x1ffffc))
|| ((val < 0) && (~(val - 1) & ~0x1ffffc)))
as_bad_where (fixP->fx_file, fixP->fx_line,
case BFD_RELOC_SPARC_HH22:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_SPARC_LM22:
case BFD_RELOC_HI22:
case BFD_RELOC_SPARC_HM10:
val = BSR (val, 32);
- /* intentional fallthrough */
+ /* Fall through. */
case BFD_RELOC_LO10:
if (!fixP->fx_addsy)
}
break;
+ case BFD_RELOC_SPARC_OLO10:
+ val &= 0x3ff;
+ val += fixP->tc_fix_data;
+ /* Fall through. */
+
case BFD_RELOC_SPARC13:
if (! in_signed_range (val, 0x1fff))
as_bad_where (fixP->fx_file, fixP->fx_line,
case BFD_RELOC_SPARC_WDISP22:
val = (val >> 2) + 1;
- /* FALLTHROUGH */
+ /* Fall through. */
case BFD_RELOC_SPARC_BASE22:
insn |= val & 0x3fffff;
break;
case BFD_RELOC_SPARC_HIX22:
if (!fixP->fx_addsy)
{
- val ^= ~ (offsetT) 0;
+ val ^= ~(offsetT) 0;
insn |= (val >> 10) & 0x3fffff;
}
break;
/* Translate internal representation of relocation info to BFD target
format. */
-arelent *
+
+arelent **
tc_gen_reloc (section, fixp)
asection *section;
fixS *fixp;
{
+ static arelent *relocs[3];
arelent *reloc;
bfd_reloc_code_real_type code;
- reloc = (arelent *) xmalloc (sizeof (arelent));
+ relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
+ relocs[1] = NULL;
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
case BFD_RELOC_SPARC_HIX22:
case BFD_RELOC_SPARC_LOX10:
case BFD_RELOC_SPARC_REV32:
+ case BFD_RELOC_SPARC_OLO10:
case BFD_RELOC_VTABLE_ENTRY:
case BFD_RELOC_VTABLE_INHERIT:
code = fixp->fx_r_type;
#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
#endif
+ /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
+
if (sparc_pic_code)
{
switch (code)
break;
}
}
-#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
+#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
- reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+ if (code == BFD_RELOC_SPARC_OLO10)
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
+ else
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
if (reloc->howto == 0)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
_("internal error: can't export reloc type %d (`%s')"),
fixp->fx_r_type, bfd_get_reloc_code_name (code));
- return 0;
+ xfree (reloc);
+ relocs[0] = NULL;
+ return relocs;
}
/* @@ Why fx_addnumber sometimes and fx_offset other times? */
else
reloc->addend = fixp->fx_offset - reloc->address;
-#else /* elf or coff */
+#else /* elf or coff */
if (reloc->howto->pc_relative == 0
|| code == BFD_RELOC_SPARC_PC10
reloc->addend = fixp->fx_offset;
#endif
- return reloc;
+ /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
+ on the same location. */
+ if (code == BFD_RELOC_SPARC_OLO10)
+ {
+ relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
+ relocs[2] = NULL;
+
+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr
+ = symbol_get_bfdsym (section_symbol (absolute_section));
+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
+ reloc->addend = fixp->tc_fix_data;
+ }
+
+ return relocs;
}
\f
-/* We have no need to default values of symbols. */
+/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
- char *name;
+ char *name ATTRIBUTE_UNUSED;
{
return 0;
-} /* md_undefined_symbol() */
+}
+
+/* Round up a section size to the appropriate boundary. */
-/* Round up a section size to the appropriate boundary. */
valueT
md_section_align (segment, size)
- segT segment;
+ segT segment ATTRIBUTE_UNUSED;
valueT size;
{
#ifndef OBJ_ELF
valueT align = ((valueT) 1
<< (valueT) bfd_get_section_alignment (stdoutput, segment));
valueT newsize;
- /* turn alignment value into a mask */
+
+ /* Turn alignment value into a mask. */
align--;
newsize = (size + align) & ~align;
return newsize;
/* Exactly what point is a PC-relative offset relative TO?
On the sparc, they're relative to the address of the offset, plus
its size. This gets us to the following instruction.
- (??? Is this right? FIXME-SOON) */
-long
+ (??? Is this right? FIXME-SOON) */
+long
md_pcrel_from (fixP)
fixS *fixP;
{
return (value == 1) ? shift : -1;
}
-/*
- * sort of like s_lcomm
- */
+/* Sort of like s_lcomm. */
#ifndef OBJ_ELF
static int max_alignment = 15;
static void
s_reserve (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *name;
char *p;
as_bad (_("BSS length (%d.) <0! Ignored."), size);
ignore_rest_of_line ();
return;
- } /* bad length */
+ } /* Bad length. */
*p = 0;
symbolP = symbol_find_or_make (name);
segT current_seg = now_seg;
subsegT current_subseg = now_subseg;
- subseg_set (bss_section, 1); /* switch to bss */
+ /* Switch to bss. */
+ subseg_set (bss_section, 1);
if (align)
- frag_align (align, 0, 0); /* do alignment */
+ /* Do alignment. */
+ frag_align (align, 0, 0);
- /* detach from old frag */
- if (S_GET_SEGMENT(symbolP) == bss_section)
+ /* Detach from old frag. */
+ if (S_GET_SEGMENT (symbolP) == bss_section)
symbol_get_frag (symbolP)->fr_symbol = NULL;
symbol_set_frag (symbolP, frag_now);
- pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
- (offsetT) size, (char *)0);
+ pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
+ (offsetT) size, (char *) 0);
*pfrag = 0;
S_SET_SEGMENT (symbolP, bss_section);
}
else
{
- as_warn("Ignoring attempt to re-define symbol %s",
- S_GET_NAME (symbolP));
- } /* if not redefining */
+ as_warn ("Ignoring attempt to re-define symbol %s",
+ S_GET_NAME (symbolP));
+ } /* if not redefining. */
demand_empty_rest_of_line ();
}
static void
s_common (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *name;
char c;
name = input_line_pointer;
c = get_symbol_end ();
- /* just after name is now '\0' */
+ /* Just after name is now '\0'. */
p = input_line_pointer;
*p = c;
SKIP_WHITESPACE ();
ignore_rest_of_line ();
return;
}
- input_line_pointer++; /* skip ',' */
+
+ /* Skip ','. */
+ input_line_pointer++;
+
if ((temp = get_absolute_expression ()) < 0)
{
as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
S_SET_EXTERNAL (symbolP);
#endif
}
- know (symbolP->sy_frag == &zero_address_frag);
+ know (symbol_get_frag (symbolP) == &zero_address_frag);
if (*input_line_pointer != ',')
{
as_bad (_("Expected comma after common length"));
subseg_set (old_sec, old_subsec);
}
else
-#endif /* OBJ_ELF */
+#endif /* OBJ_ELF */
{
allocate_common:
S_SET_VALUE (symbolP, (valueT) size);
static void
s_empty (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
/* The easy way to implement is to just forget about the last
instruction. */
static void
s_seg (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
input_line_pointer += 5;
/* We only support 2 segments -- text and data -- for now, so
things in the "bss segment" will have to go into data for now.
- You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
- subseg_set (data_section, 255); /* FIXME-SOMEDAY */
+ You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
+ subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
return;
}
as_bad (_("Unknown segment type"));
static void
s_proc (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
while (!is_end_of_line[(unsigned char) *input_line_pointer])
{
static void
s_ncons (bytes)
- int bytes;
+ int bytes ATTRIBUTE_UNUSED;
{
cons (sparc_arch_size == 32 ? 4 : 8);
}
+#ifdef OBJ_ELF
+/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
+ global register.
+ The syntax is:
+
+ .register %g[2367],{#scratch|symbolname|#ignore}
+*/
+
+static void
+s_register (ignore)
+ int ignore ATTRIBUTE_UNUSED;
+{
+ char c;
+ int reg;
+ int flags;
+ const char *regname;
+
+ if (input_line_pointer[0] != '%'
+ || input_line_pointer[1] != 'g'
+ || ((input_line_pointer[2] & ~1) != '2'
+ && (input_line_pointer[2] & ~1) != '6')
+ || input_line_pointer[3] != ',')
+ as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
+ reg = input_line_pointer[2] - '0';
+ input_line_pointer += 4;
+
+ if (*input_line_pointer == '#')
+ {
+ ++input_line_pointer;
+ regname = input_line_pointer;
+ c = get_symbol_end ();
+ if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
+ as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
+ if (regname[0] == 'i')
+ regname = NULL;
+ else
+ regname = "";
+ }
+ else
+ {
+ regname = input_line_pointer;
+ c = get_symbol_end ();
+ }
+ if (sparc_arch_size == 64)
+ {
+ if (globals[reg])
+ {
+ if ((regname && globals[reg] != (symbolS *) 1
+ && strcmp (S_GET_NAME (globals[reg]), regname))
+ || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
+ as_bad (_("redefinition of global register"));
+ }
+ else
+ {
+ if (regname == NULL)
+ globals[reg] = (symbolS *) 1;
+ else
+ {
+ if (*regname)
+ {
+ if (symbol_find (regname))
+ as_bad (_("Register symbol %s already defined."),
+ regname);
+ }
+ globals[reg] = symbol_make (regname);
+ flags = symbol_get_bfdsym (globals[reg])->flags;
+ if (! *regname)
+ flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
+ if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
+ flags |= BSF_GLOBAL;
+ symbol_get_bfdsym (globals[reg])->flags = flags;
+ S_SET_VALUE (globals[reg], (valueT) reg);
+ S_SET_ALIGN (globals[reg], reg);
+ S_SET_SIZE (globals[reg], 0);
+ /* Although we actually want undefined_section here,
+ we have to use absolute_section, because otherwise
+ generic as code will make it a COM section.
+ We fix this up in sparc_adjust_symtab. */
+ S_SET_SEGMENT (globals[reg], absolute_section);
+ S_SET_OTHER (globals[reg], 0);
+ elf_symbol (symbol_get_bfdsym (globals[reg]))
+ ->internal_elf_sym.st_info =
+ ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
+ elf_symbol (symbol_get_bfdsym (globals[reg]))
+ ->internal_elf_sym.st_shndx = SHN_UNDEF;
+ }
+ }
+ }
+
+ *input_line_pointer = c;
+
+ demand_empty_rest_of_line ();
+}
+
+/* Adjust the symbol table. We set undefined sections for STT_REGISTER
+ symbols which need it. */
+
+void
+sparc_adjust_symtab ()
+{
+ symbolS *sym;
+
+ for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
+ {
+ if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
+ ->internal_elf_sym.st_info) != STT_REGISTER)
+ continue;
+
+ if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
+ ->internal_elf_sym.st_shndx != SHN_UNDEF))
+ continue;
+
+ S_SET_SEGMENT (sym, undefined_section);
+ }
+}
+#endif
+
/* If the --enforce-aligned-data option is used, we require .word,
et. al., to be aligned correctly. We do it by setting up an
rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
return;
}
- p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
+ p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
(symbolS *) NULL, (offsetT) nalign, (char *) NULL);
record_alignment (now_seg, nalign);
}
-/* This is where we do the unexpected alignment check.
- This is called from HANDLE_ALIGN in tc-sparc.h. */
+/* This is called from HANDLE_ALIGN in tc-sparc.h. */
void
sparc_handle_align (fragp)
fragS *fragp;
{
- if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
- && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
- as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
- if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
- {
- int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
-
- if (count >= 4
- && !(count & 3)
- && count <= 1024
- && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
- {
- unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
- int i;
-
- for (i = 0; i < count; i += 4, p++)
- if (INSN_BIG_ENDIAN)
- number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
- else
- number_to_chars_littleendian ((char *)p, 0x10000000, 4);
-
- if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
- {
- char *waddr = &fragp->fr_literal[fragp->fr_fix];
- unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
- if (INSN_BIG_ENDIAN)
- number_to_chars_bigendian (waddr, wval, 4);
- else
- number_to_chars_littleendian (waddr, wval, 4);
- }
- fragp->fr_var = count;
- }
+ int count, fix;
+ char *p;
+
+ count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+
+ switch (fragp->fr_type)
+ {
+ case rs_align_test:
+ if (count != 0)
+ as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
+ break;
+
+ case rs_align_code:
+ p = fragp->fr_literal + fragp->fr_fix;
+ fix = 0;
+
+ if (count & 3)
+ {
+ fix = count & 3;
+ memset (p, 0, fix);
+ p += fix;
+ count -= fix;
+ }
+
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
+ {
+ unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
+ if (INSN_BIG_ENDIAN)
+ number_to_chars_bigendian (p, wval, 4);
+ else
+ number_to_chars_littleendian (p, wval, 4);
+ p += 4;
+ count -= 4;
+ fix += 4;
+ }
+
+ if (INSN_BIG_ENDIAN)
+ number_to_chars_bigendian (p, 0x01000000, 4);
+ else
+ number_to_chars_littleendian (p, 0x01000000, 4);
+
+ fragp->fr_fix += fix;
+ fragp->fr_var = 4;
+ break;
+
+ default:
+ break;
}
}
elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
if (current_architecture == SPARC_OPCODE_ARCH_V9A)
elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
+ else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
+ elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
}
#endif
(nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
if (target_little_endian_data && nbytes == 4
- && now_seg->flags & SEC_ALLOC)
+ && now_seg->flags & SEC_ALLOC)
r = BFD_RELOC_SPARC_REV32;
fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
}
#ifdef OBJ_ELF
int
elf32_sparc_force_relocation (fixp)
- struct fix *fixp;
+ struct fix *fixp;
{
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 1;
-
+
return 0;
}
#endif
-
projects / deliverable / binutils-gdb.git / blobdiff