\input texinfo @c -*-Texinfo-*-
-@c Copyright 1991-2013 Free Software Foundation, Inc.
+@c Copyright (C) 1991-2015 Free Software Foundation, Inc.
@c UPDATE!! On future updates--
@c (1) check for new machine-dep cmdline options in
@c md_parse_option definitions in config/tc-*.c
This file documents the GNU Assembler "@value{AS}".
@c man begin COPYRIGHT
-Copyright @copyright{} 1991-2013 Free Software Foundation, Inc.
+Copyright @copyright{} 1991-2015 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@end tex
@vskip 0pt plus 1filll
-Copyright @copyright{} 1991-2013 Free Software Foundation, Inc.
+Copyright @copyright{} 1991-2015 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@emph{Target AArch64 options:}
[@b{-EB}|@b{-EL}]
+ [@b{-mabi}=@var{ABI}]
@end ifset
@ifset ALPHA
[@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}]
[@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}]
[@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}]
+ [@b{-mfp64}] [@b{-mgp64}] [@b{-mfpxx}]
+ [@b{-modd-spreg}] [@b{-mno-odd-spreg}]
[@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}]
[@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}]
- [@b{-mips64}] [@b{-mips64r2}]
+ [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips32r6}] [@b{-mips64}] [@b{-mips64r2}]
+ [@b{-mips64r3}] [@b{-mips64r5}] [@b{-mips64r6}]
[@b{-construct-floats}] [@b{-no-construct-floats}]
+ [@b{-mnan=@var{encoding}}]
[@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
[@b{-mips16}] [@b{-no-mips16}]
[@b{-mmicromips}] [@b{-mno-micromips}]
[@b{-mdmx}] [@b{-no-mdmx}]
[@b{-mdsp}] [@b{-mno-dsp}]
[@b{-mdspr2}] [@b{-mno-dspr2}]
+ [@b{-mmsa}] [@b{-mno-msa}]
+ [@b{-mxpa}] [@b{-mno-xpa}]
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
+ [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
[@b{-mfix-vr4120}] [@b{-mno-fix-vr4120}]
[@b{-mfix-vr4130}] [@b{-mno-fix-vr4130}]
[@b{-mdebug}] [@b{-no-mdebug}]
[@b{-relax-all}] [@b{-relax-section}] [@b{-no-relax}]
[@b{-EB}] [@b{-EL}]
@end ifset
+@ifset NDS32
+
+@emph{Target NDS32 options:}
+ [@b{-EL}] [@b{-EB}] [@b{-O}] [@b{-Os}] [@b{-mcpu=@var{cpu}}]
+ [@b{-misa=@var{isa}}] [@b{-mabi=@var{abi}}] [@b{-mall-ext}]
+ [@b{-m[no-]16-bit}] [@b{-m[no-]perf-ext}] [@b{-m[no-]perf2-ext}]
+ [@b{-m[no-]string-ext}] [@b{-m[no-]dsp-ext}] [@b{-m[no-]mac}] [@b{-m[no-]div}]
+ [@b{-m[no-]audio-isa-ext}] [@b{-m[no-]fpu-sp-ext}] [@b{-m[no-]fpu-dp-ext}]
+ [@b{-m[no-]fpu-fma}] [@b{-mfpu-freg=@var{FREG}}] [@b{-mreduced-regs}]
+ [@b{-mfull-regs}] [@b{-m[no-]dx-regs}] [@b{-mpic}] [@b{-mno-relax}]
+ [@b{-mb2bb}]
+@end ifset
@ifset PDP11
@emph{Target PDP11 options:}
[@b{-msolaris}|@b{-mno-solaris}]
[@b{-nops=@var{count}}]
@end ifset
+@ifset RL78
+
+@emph{Target RL78 options:}
+ [@b{-mg10}]
+ [@b{-m32bit-doubles}|@b{-m64bit-doubles}]
+@end ifset
@ifset RX
@emph{Target RX options:}
[@b{-mcpu=54[123589]}|@b{-mcpu=54[56]lp}] [@b{-mfar-mode}|@b{-mf}]
[@b{-merrors-to-file} @var{<filename>}|@b{-me} @var{<filename>}]
@end ifset
-
@ifset TIC6X
@emph{Target TIC6X options:}
@ifset TILEPRO
@c TILEPro has no machine-dependent assembler options
@end ifset
+@ifset VISIUM
+@emph{Target Visium options:}
+ [@b{-mtune=@var{arch}}]
+@end ifset
@ifset XTENSA
@emph{Target Xtensa options:}
[@b{--[no-]target-align}] [@b{--[no-]longcalls}]
[@b{--[no-]transform}]
[@b{--rename-section} @var{oldname}=@var{newname}]
+ [@b{--[no-]trampolines}]
@end ifset
-
@ifset Z80
@emph{Target Z80 options:}
[@b{ -forbid-undocumented-instructions}] [@b{-Fud}]
[@b{ -forbid-unportable-instructions}] [@b{-Fup}]
@end ifset
-
@ifset Z8000
+
@c Z8000 has no machine-dependent assembler options
@end ifset
@item --compress-debug-sections
Compress DWARF debug sections using zlib. The debug sections are renamed
to begin with @samp{.zdebug}, and the resulting object file may not be
-compatible with older linkers and object file utilities.
+compatible with older linkers and object file utilities. Note if compression
+would make a given section @emph{larger} then it is not compressed or renamed.
+
+@ifset ELF
+@cindex @samp{--compress-debug-sections=} option
+@item --compress-debug-sections=none
+@itemx --compress-debug-sections=zlib
+@itemx --compress-debug-sections=zlib-gnu
+@itemx --compress-debug-sections=zlib-gabi
+These options control how DWARF debug sections are compressed.
+@option{--compress-debug-sections=none} is equivalent to
+@option{--nocompress-debug-sections}.
+@option{--compress-debug-sections=zlib} and
+@option{--compress-debug-sections=zlib-gnu} are equivalent to
+@option{--compress-debug-sections}.
+@option{--compress-debug-sections=zlib-gabi} compresses
+DWARF debug sections with SHF_COMPRESSED from the ELF ABI.
+@end ifset
@item --nocompress-debug-sections
Do not compress DWARF debug sections. This is the default.
@item -mthumb-interwork
Specify that the code has been generated with interworking between Thumb and
ARM code in mind.
+@item -mccs
+Turns on CodeComposer Studio assembly syntax compatibility mode.
@item -k
Specify that PIC code has been generated.
@end table
@itemx -mips5
@itemx -mips32
@itemx -mips32r2
+@itemx -mips32r3
+@itemx -mips32r5
+@itemx -mips32r6
@itemx -mips64
@itemx -mips64r2
+@itemx -mips64r3
+@itemx -mips64r5
+@itemx -mips64r6
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an
alias for @samp{-march=r6000}, @samp{-mips3} is an alias for
@samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}.
-@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
-@samp{-mips64r2}
-correspond to generic
-@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, @samp{MIPS64},
-and @samp{MIPS64 Release 2}
-ISA processors, respectively.
+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
+@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
+@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to generic
+MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32
+Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and
+MIPS64 Release 6 ISA processors, respectively.
@item -march=@var{cpu}
Generate code for a particular MIPS CPU.
Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.
+@item -mfix-rm7000
+@itemx -mno-fix-rm7000
+Cause nops to be inserted if a dmult or dmultu instruction is
+followed by a load instruction.
+
@item -mdebug
@itemx -no-mdebug
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
all times. @samp{-mgp32} controls the size of general-purpose registers
and @samp{-mfp32} controls the size of floating-point registers.
+@item -mgp64
+@itemx -mfp64
+The register sizes are normally inferred from the ISA and ABI, but these
+flags force a certain group of registers to be treated as 64 bits wide at
+all times. @samp{-mgp64} controls the size of general-purpose registers
+and @samp{-mfp64} controls the size of floating-point registers.
+
+@item -mfpxx
+The register sizes are normally inferred from the ISA and ABI, but using
+this flag in combination with @samp{-mabi=32} enables an ABI variant
+which will operate correctly with floating-point registers which are
+32 or 64 bits wide.
+
+@item -modd-spreg
+@itemx -mno-odd-spreg
+Enable use of floating-point operations on odd-numbered single-precision
+registers when supported by the ISA. @samp{-mfpxx} implies
+@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}.
+
@item -mips16
@itemx -no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting
This tells the assembler to accept DSP Release 2 instructions.
@samp{-mno-dspr2} turns off this option.
+@item -mmsa
+@itemx -mno-msa
+Generate code for the MIPS SIMD Architecture Extension.
+This tells the assembler to accept MSA instructions.
+@samp{-mno-msa} turns off this option.
+
+@item -mxpa
+@itemx -mno-xpa
+Generate code for the MIPS eXtended Physical Address (XPA) Extension.
+This tells the assembler to accept XPA instructions.
+@samp{-mno-xpa} turns off this option.
+
@item -mmt
@itemx -mno-mt
Generate code for the MT Application Specific Extension.
branches. By default @samp{--no-relax-branch} is selected, causing any
out-of-range branches to produce an error.
+@item -mnan=@var{encoding}
+Select between the IEEE 754-2008 (@option{-mnan=2008}) or the legacy
+(@option{-mnan=legacy}) NaN encoding format. The latter is the default.
+
@cindex emulation
@item --emulation=@var{name}
This option was formerly used to switch between ELF and ECOFF output
See the info pages for documentation of the MMIX-specific options.
@end ifset
+@ifset NDS32
+
+@ifclear man
+@xref{NDS32 Options}, for the options available when @value{AS} is configured
+for a NDS32 processor.
+@end ifclear
+@c ended inside the included file
+@end ifset
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for a
+NDS32 processor.
+@c man end
+@c man begin INCLUDE
+@include c-nds32.texi
+@c ended inside the included file
+@end ifset
+
@c man end
@ifset PPC
@item -march=@var{processor}
Specify which s390 processor variant is the target, @samp{g6}, @samp{g6},
@samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, @samp{z10},
-@samp{z196}, or @samp{zEC12}.
+@samp{z196}, @samp{zEC12}, or @samp{z13}.
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
@end ifset
+@ifset VISIUM
+
+@ifclear man
+@xref{Visium Options}, for the options available when @value{AS} is configured
+for a Visium processor.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following option is available when @value{AS} is configured for a Visium
+processor.
+@c man end
+@c man begin INCLUDE
+@include c-visium.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@ifset XTENSA
@ifclear man
Local symbols are defined and used within the assembler, but they are
normally not saved in object files. Thus, they are not visible when debugging.
-You may use the @samp{-L} option (@pxref{L, ,Include Local Symbols:
-@option{-L}}) to retain the local symbols in the object files.
+You may use the @samp{-L} option (@pxref{L, ,Include Local Symbols})
+to retain the local symbols in the object files.
@subheading Local Labels
* Ascii:: @code{.ascii "@var{string}"}@dots{}
* Asciz:: @code{.asciz "@var{string}"}@dots{}
* Balign:: @code{.balign @var{abs-expr} , @var{abs-expr}}
-* Bundle directives:: @code{.bundle_align_mode @var{abs-expr}}, @code{.bundle_lock}, @code{.bundle_unlock}
+* Bundle directives:: @code{.bundle_align_mode @var{abs-expr}}, etc
* Byte:: @code{.byte @var{expressions}}
* CFI directives:: @code{.cfi_startproc [simple]}, @code{.cfi_endproc}, etc.
* Comm:: @code{.comm @var{symbol} , @var{length} }
with no-op instructions when appropriate.
The way the required alignment is specified varies from system to system.
-For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
+For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
alignment request in bytes. For example @samp{.align 8} advances
the location counter until it is a multiple of 8. If the location counter
undefined.
@node Bundle directives
-@section @code{.bundle_align_mode @var{abs-expr}}
+@section Bundle directives
+@subsection @code{.bundle_align_mode @var{abs-expr}}
@cindex @code{bundle_align_mode} directive
@cindex bundle
@cindex instruction bundle
starts in the next bundle. As a corollary, it's an error if any single
instruction's encoding is longer than the bundle size.
-@section @code{.bundle_lock} and @code{.bundle_unlock}
+@subsection @code{.bundle_lock} and @code{.bundle_unlock}
@cindex @code{bundle_lock} directive
@cindex @code{bundle_unlock} directive
The @code{.bundle_lock} and directive @code{.bundle_unlock} directives
Each expression is assembled into the next byte.
@node CFI directives
-@section @code{.cfi_sections @var{section_list}}
+@section CFI directives
+@subsection @code{.cfi_sections @var{section_list}}
@cindex @code{cfi_sections} directive
@code{.cfi_sections} may be used to specify whether CFI directives
should emit @code{.eh_frame} section and/or @code{.debug_frame} section.
To emit both use @code{.eh_frame, .debug_frame}. The default if this
directive is not used is @code{.cfi_sections .eh_frame}.
-@section @code{.cfi_startproc [simple]}
+@subsection @code{.cfi_startproc [simple]}
@cindex @code{cfi_startproc} directive
@code{.cfi_startproc} is used at the beginning of each function that
should have an entry in @code{.eh_frame}. It initializes some internal
Unless @code{.cfi_startproc} is used along with parameter @code{simple}
it also emits some architecture dependent initial CFI instructions.
-@section @code{.cfi_endproc}
+@subsection @code{.cfi_endproc}
@cindex @code{cfi_endproc} directive
@code{.cfi_endproc} is used at the end of a function where it closes its
unwind entry previously opened by
@code{.cfi_startproc}, and emits it to @code{.eh_frame}.
-@section @code{.cfi_personality @var{encoding} [, @var{exp}]}
+@subsection @code{.cfi_personality @var{encoding} [, @var{exp}]}
@code{.cfi_personality} defines personality routine and its encoding.
@var{encoding} must be a constant determining how the personality
should be encoded. If it is 255 (@code{DW_EH_PE_omit}), second
The default after @code{.cfi_startproc} is @code{.cfi_personality 0xff},
no personality routine.
-@section @code{.cfi_lsda @var{encoding} [, @var{exp}]}
+@subsection @code{.cfi_lsda @var{encoding} [, @var{exp}]}
@code{.cfi_lsda} defines LSDA and its encoding.
@var{encoding} must be a constant determining how the LSDA
should be encoded. If it is 255 (@code{DW_EH_PE_omit}), second
or a symbol name. The default after @code{.cfi_startproc} is @code{.cfi_lsda 0xff},
no LSDA.
-@section @code{.cfi_def_cfa @var{register}, @var{offset}}
+@subsection @code{.cfi_def_cfa @var{register}, @var{offset}}
@code{.cfi_def_cfa} defines a rule for computing CFA as: @i{take
address from @var{register} and add @var{offset} to it}.
-@section @code{.cfi_def_cfa_register @var{register}}
+@subsection @code{.cfi_def_cfa_register @var{register}}
@code{.cfi_def_cfa_register} modifies a rule for computing CFA. From
now on @var{register} will be used instead of the old one. Offset
remains the same.
-@section @code{.cfi_def_cfa_offset @var{offset}}
+@subsection @code{.cfi_def_cfa_offset @var{offset}}
@code{.cfi_def_cfa_offset} modifies a rule for computing CFA. Register
remains the same, but @var{offset} is new. Note that it is the
absolute offset that will be added to a defined register to compute
CFA address.
-@section @code{.cfi_adjust_cfa_offset @var{offset}}
+@subsection @code{.cfi_adjust_cfa_offset @var{offset}}
Same as @code{.cfi_def_cfa_offset} but @var{offset} is a relative
value that is added/substracted from the previous offset.
-@section @code{.cfi_offset @var{register}, @var{offset}}
+@subsection @code{.cfi_offset @var{register}, @var{offset}}
Previous value of @var{register} is saved at offset @var{offset} from
CFA.
-@section @code{.cfi_rel_offset @var{register}, @var{offset}}
+@subsection @code{.cfi_rel_offset @var{register}, @var{offset}}
Previous value of @var{register} is saved at offset @var{offset} from
the current CFA register. This is transformed to @code{.cfi_offset}
using the known displacement of the CFA register from the CFA.
This is often easier to use, because the number will match the
code it's annotating.
-@section @code{.cfi_register @var{register1}, @var{register2}}
+@subsection @code{.cfi_register @var{register1}, @var{register2}}
Previous value of @var{register1} is saved in register @var{register2}.
-@section @code{.cfi_restore @var{register}}
+@subsection @code{.cfi_restore @var{register}}
@code{.cfi_restore} says that the rule for @var{register} is now the
same as it was at the beginning of the function, after all initial
instruction added by @code{.cfi_startproc} were executed.
-@section @code{.cfi_undefined @var{register}}
+@subsection @code{.cfi_undefined @var{register}}
From now on the previous value of @var{register} can't be restored anymore.
-@section @code{.cfi_same_value @var{register}}
+@subsection @code{.cfi_same_value @var{register}}
Current value of @var{register} is the same like in the previous frame,
i.e. no restoration needed.
-@section @code{.cfi_remember_state},
+@subsection @code{.cfi_remember_state},
First save all current rules for all registers by @code{.cfi_remember_state},
then totally screw them up by subsequent @code{.cfi_*} directives and when
everything is hopelessly bad, use @code{.cfi_restore_state} to restore
the previous saved state.
-@section @code{.cfi_return_column @var{register}}
+@subsection @code{.cfi_return_column @var{register}}
Change return column @var{register}, i.e. the return address is either
directly in @var{register} or can be accessed by rules for @var{register}.
-@section @code{.cfi_signal_frame}
+@subsection @code{.cfi_signal_frame}
Mark current function as signal trampoline.
-@section @code{.cfi_window_save}
+@subsection @code{.cfi_window_save}
SPARC register window has been saved.
-@section @code{.cfi_escape} @var{expression}[, @dots{}]
+@subsection @code{.cfi_escape} @var{expression}[, @dots{}]
Allows the user to add arbitrary bytes to the unwind info. One
might use this to add OS-specific CFI opcodes, or generic CFI
opcodes that GAS does not yet support.
-@section @code{.cfi_val_encoded_addr @var{register}, @var{encoding}, @var{label}}
+@subsection @code{.cfi_val_encoded_addr @var{register}, @var{encoding}, @var{label}}
The current value of @var{register} is @var{label}. The value of @var{label}
will be encoded in the output file according to @var{encoding}; see the
description of @code{.cfi_personality} for details on this encoding.
@item
0 for files not affected by the floating-point ABI.
@item
-1 for files using the hardware floating-point with a standard double-precision
-FPU.
+1 for files using the hardware floating-point ABI with a standard
+double-precision FPU.
@item
2 for files using the hardware floating-point ABI with a single-precision FPU.
@item
3 for files using the software floating-point ABI.
@item
-4 for files using the hardware floating-point ABI with 64-bit wide
-double-precision floating-point registers and 32-bit wide general
-purpose registers.
+4 for files using the deprecated hardware floating-point ABI which used 64-bit
+floating-point registers, 32-bit general-purpose registers and increased the
+number of callee-saved floating-point registers.
+@item
+5 for files using the hardware floating-point ABI with a double-precision FPU
+with either 32-bit or 64-bit floating-point registers and 32-bit
+general-purpose registers.
+@item
+6 for files using the hardware floating-point ABI with 64-bit floating-point
+registers and 32-bit general-purpose registers.
+@item
+7 for files using the hardware floating-point ABI with 64-bit floating-point
+registers, 32-bit general-purpose registers and a rule that forbids the
+direct use of odd-numbered single-precision floating-point registers.
@end itemize
@end table
@ifset MSP430
* MSP430-Dependent:: MSP430 Dependent Features
@end ifset
+@ifset NDS32
+* NDS32-Dependent:: Andes NDS32 Dependent Features
+@end ifset
@ifset NIOSII
* NiosII-Dependent:: Altera Nios II Dependent Features
@end ifset
@ifset NS32K
* NS32K-Dependent:: NS32K Dependent Features
@end ifset
-@ifset SH
-* SH-Dependent:: Renesas / SuperH SH Dependent Features
-* SH64-Dependent:: SuperH SH64 Dependent Features
-@end ifset
@ifset PDP11
* PDP-11-Dependent:: PDP-11 Dependent Features
@end ifset
@ifset SCORE
* SCORE-Dependent:: SCORE Dependent Features
@end ifset
+@ifset SH
+* SH-Dependent:: Renesas / SuperH SH Dependent Features
+* SH64-Dependent:: SuperH SH64 Dependent Features
+@end ifset
@ifset SPARC
* Sparc-Dependent:: SPARC Dependent Features
@end ifset
@ifset V850
* V850-Dependent:: V850 Dependent Features
@end ifset
+@ifset VAX
+* Vax-Dependent:: VAX Dependent Features
+@end ifset
+@ifset VISIUM
+* Visium-Dependent:: Visium Dependent Features
+@end ifset
@ifset XGATE
* XGATE-Dependent:: XGATE Features
@end ifset
@ifset Z8000
* Z8000-Dependent:: Z8000 Dependent Features
@end ifset
-@ifset VAX
-* Vax-Dependent:: VAX Dependent Features
-@end ifset
@end menu
@lowersections
@include c-msp430.texi
@end ifset
+@ifset NDS32
+@include c-nds32.texi
+@end ifset
+
@ifset NIOSII
@include c-nios2.texi
@end ifset
@include c-tilepro.texi
@end ifset
-@ifset Z80
-@include c-z80.texi
-@end ifset
-
-@ifset Z8000
-@include c-z8k.texi
+@ifset V850
+@include c-v850.texi
@end ifset
@ifset VAX
@include c-vax.texi
@end ifset
-@ifset V850
-@include c-v850.texi
+@ifset VISIUM
+@include c-visium.texi
@end ifset
@ifset XGATE
@include c-xtensa.texi
@end ifset
+@ifset Z80
+@include c-z80.texi
+@end ifset
+
+@ifset Z8000
+@include c-z8k.texi
+@end ifset
+
@ifset GENERIC
@c reverse effect of @down at top of generic Machine-Dep chapter
@raisesections
projects / deliverable / binutils-gdb.git / blobdiff