-@c Copyright (C) 2009-2015 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2018 Free Software Foundation, Inc.
@c Contributed by ARM Ltd.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man begin OPTIONS
@table @gcctabopt
-@cindex @option{-EB} command line option, AArch64
+@cindex @option{-EB} command-line option, AArch64
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
-@cindex @option{-EL} command line option, AArch64
+@cindex @option{-EL} command-line option, AArch64
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
-@cindex @option{-mabi=} command line option, AArch64
+@cindex @option{-mabi=} command-line option, AArch64
@item -mabi=@var{abi}
Specify which ABI the source code uses. The recognized arguments
are: @code{ilp32} and @code{lp64}, which decides the generated object
file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
-@cindex @option{-mcpu=} command line option, AArch64
+@cindex @option{-mcpu=} command-line option, AArch64
@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor. The following processor names are recognized:
+@code{cortex-a35},
@code{cortex-a53},
+@code{cortex-a55},
@code{cortex-a57},
@code{cortex-a72},
+@code{cortex-a73},
+@code{cortex-a75},
+@code{cortex-a76},
@code{exynos-m1},
+@code{falkor},
+@code{qdf24xx},
+@code{saphira},
@code{thunderx},
+@code{vulcan},
@code{xgene1}
and
@code{xgene2}.
Consequently, you will not normally have to specify any additional
extensions.
-@cindex @option{-march=} command line option, AArch64
+@cindex @option{-march=} command-line option, AArch64
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
-following architecture names are recognized: @code{armv8-a} and
-@code{armv8.1-a}.
+following architecture names are recognized: @code{armv8-a},
+@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are
@option{-mcpu}, extensions are not always enabled by default,
@xref{AArch64 Extensions}.
-@cindex @code{-mverbose-error} command line option, AArch64
+@cindex @code{-mverbose-error} command-line option, AArch64
@item -mverbose-error
This option enables verbose error messages for AArch64 gas. This option
is enabled by default.
-@cindex @code{-mno-verbose-error} command line option, AArch64
+@cindex @code{-mno-verbose-error} command-line option, AArch64
@item -mno-verbose-error
This option disables verbose error messages in AArch64 gas.
@multitable @columnfractions .12 .17 .17 .54
@headitem Extension @tab Minimum Architecture @tab Enabled by default
@tab Description
-@item @code{crc} @tab ARMv8-A @tab No
+@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
+ @tab Enable the complex number SIMD extensions. This implies
+ @code{fp16} and @code{simd}.
+@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
@tab Enable CRC instructions.
@item @code{crypto} @tab ARMv8-A @tab No
- @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
+ @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
+@item @code{aes} @tab ARMv8-A @tab No
+ @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha2} @tab ARMv8-A @tab No
+ @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha3} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
+@item @code{sm4} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable floating-point extensions.
-@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable Advanced SIMD extensions. This implies @code{fp}.
-@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable Privileged Access Never support.
-@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
+@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
+ @tab Enable ARMv8.2 16-bit floating-point support. This implies
+ @code{fp}.
+@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
@tab Enable Limited Ordering Regions extensions.
-@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
+@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Large System extensions.
+@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{profile} @tab ARMv8.2-A @tab No
+ @tab Enable statistical profiling extensions.
+@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
+ @tab Enable the Reliability, Availability and Serviceability
+ extension.
+@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
+ @tab Enable the weak release consistency extension.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
+@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Advanced SIMD extensions. This implies @code{fp}.
+@item @code{sve} @tab ARMv8.2-A @tab No
+ @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
+ @code{simd} and @code{compnum}.
+@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
+ @tab Enable the Dot Product extension. This implies @code{simd}.
+@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
+ @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
+ This implies @code{fp16}.
@end multitable
@node AArch64 Syntax
@cindex @code{.arch} directive, AArch64
@item .arch @var{name}
Select the target architecture. Valid values for @var{name} are the same as
-for the @option{-march} commandline option.
+for the @option{-march} command-line option.
Specifying @code{.arch} clears any previously selected architecture
extensions.
@item .arch_extension @var{name}
Add or remove an architecture extension to the target architecture. Valid
values for @var{name} are the same as those accepted as architectural
-extensions by the @option{-mcpu} commandline option.
+extensions by the @option{-mcpu} command-line option.
@code{.arch_extension} may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+
+@cindex @code{.cpu} directive, AArch64
+@item .cpu @var{name}
+Set the target processor. Valid values for @var{name} are the same as
+those accepted by the @option{-mcpu=} command-line option.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+
+@cindex @code{.dword} directive, AArch64
+@item .dword @var{expressions}
+The @code{.dword} directive produces 64 bit values.
+
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+
+@cindex @code{.even} directive, AArch64
+@item .even
+The @code{.even} directive aligns the output on the next even byte
+boundary.
+
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII
+
+@cindex @code{.inst} directive, AArch64
+@item .inst @var{expressions}
+Inserts the expressions into the output as if they were instructions,
+rather than data.
+
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
foo .req w0
@end smallexample
+ip0, ip1, lr and fp are automatically defined to
+alias to X16, X17, X30 and X29 respectively.
+
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+@cindex @code{.tlsdescadd} directive, AArch64
+@item @code{.tlsdescadd}
+Emits a TLSDESC_ADD reloc on the next instruction.
+
+@cindex @code{.tlsdesccall} directive, AArch64
+@item @code{.tlsdesccall}
+Emits a TLSDESC_CALL reloc on the next instruction.
+
+@cindex @code{.tlsdescldr} directive, AArch64
+@item @code{.tlsdescldr}
+Emits a TLSDESC_LDR reloc on the next instruction.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+
+@cindex @code{.xword} directive, AArch64
+@item .xword @var{expressions}
+The @code{.xword} directive produces 64 bit values. This is the same
+as the @code{.dword} directive.
+
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
projects / deliverable / binutils-gdb.git / blobdiff