[AArch64] Add support for Cortex-A35

[deliverable/binutils-gdb.git] / gas / doc / c-aarch64.texi

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index cce4f61e8cdbd9d6a495828108313c854c20f361..e7e6ba449bddab2d7f507101dbf96d40fc9abe47 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2009-2014 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2015 Free Software Foundation, Inc.
 @c Contributed by ARM Ltd.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -55,10 +55,16 @@ file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
 This option specifies the target processor.  The assembler will issue an error
 message if an attempt is made to assemble an instruction which will not execute
 on the target processor.  The following processor names are recognized:
+@code{cortex-a35},
 @code{cortex-a53},
 @code{cortex-a57},
+@code{cortex-a72},
+@code{exynos-m1},
+@code{qdf24xx},
+@code{thunderx},
+@code{xgene1}
 and
-@code{xgene-1}.
+@code{xgene2}.
 The special name @code{all} may be used to allow the assembler to accept
 instructions valid for any supported processor, including all optional
 extensions.
@@ -77,7 +83,8 @@ extensions.
 This option specifies the target architecture.  The assembler will
 issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
-only value for @var{architecture} is @code{armv8-a}.
+following architecture names are recognized: @code{armv8-a} and
+@code{armv8.1-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
@@ -129,6 +136,12 @@ automatically cause those extensions to be disabled.
  @tab Enable floating-point extensions.
 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
+@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Limited Ordering Regions extensions.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 @end multitable
 
 @node AArch64 Syntax
@@ -186,24 +199,24 @@ For example to load the 48-bit absolute address of @var{foo} into x0:
 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 instructions can be generated by prefixing the label with
-@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 
 For example to use 33-bit (+/-4GB) pc-relative addressing to
 load the address of @var{foo} into x0:
 
 @smallexample
-        adrp x0, #:pg_hi21:foo
+        adrp x0, :pg_hi21:foo
         add  x0, x0, #:lo12:foo
 @end smallexample
 
 Or to load the value of @var{foo} into x0:
 
 @smallexample
-        adrp x0, #:pg_hi21:foo
+        adrp x0, :pg_hi21:foo
         ldr  x0, [x0, #:lo12:foo]
 @end smallexample
 
-Note that @samp{#:pg_hi21:} is optional.
+Note that @samp{:pg_hi21:} is optional.
 
 @smallexample
         adrp x0, foo
@@ -212,7 +225,7 @@ Note that @samp{#:pg_hi21:} is optional.
 is equivalent to
 
 @smallexample
-        adrp x0, #:pg_hi21:foo
+        adrp x0, :pg_hi21:foo
 @end smallexample
 
 @node AArch64 Floating Point
@@ -230,6 +243,24 @@ The AArch64 architecture uses @sc{ieee} floating-point numbers.
 @table @code
 
 @c AAAAAAAAAAAAAAAAAAAAAAAAA
+
+@cindex @code{.arch} directive, AArch64
+@item .arch @var{name}
+Select the target architecture.  Valid values for @var{name} are the same as
+for the @option{-march} commandline option.
+
+Specifying @code{.arch} clears any previously selected architecture
+extensions.
+
+@cindex @code{.arch_extension} directive, AArch64
+@item .arch_extension @var{name}
+Add or remove an architecture extension to the target architecture.  Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} commandline option.
+
+@code{.arch_extension} may be used multiple times to add or remove extensions
+incrementally to the architecture being compiled for.
+
 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 
 @cindex @code{.bss} directive, AArch64
@@ -311,6 +342,10 @@ should only be done if it is really necessary.
 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 
+@cindex @code{.xword} directive, AArch64
+@item .xword
+The @code{.xword} directive produces 64 bit values.
+
 @end table
 
 @node AArch64 Opcodes