This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor. The following processor names are recognized:
+@code{cortex-a35},
@code{cortex-a53},
@code{cortex-a57},
@code{cortex-a72},
+@code{exynos-m1},
+@code{qdf24xx},
@code{thunderx},
@code{xgene1}
and
This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
-only value for @var{architecture} is @code{armv8-a}.
+following architecture names are recognized: @code{armv8-a} and
+@code{armv8.1-a}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are
@tab Enable floating-point extensions.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
+@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Limited Ordering Regions extensions.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@end multitable
@node AArch64 Syntax
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
+@cindex @code{.xword} directive, AArch64
+@item .xword
+The @code{.xword} directive produces 64 bit values.
+
@end table
@node AArch64 Opcodes