-@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
-@c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2015 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
-recognized:
+recognized:
@code{arm1},
@code{arm2},
@code{arm250},
@code{arm1020e},
@code{arm1022e},
@code{arm1026ej-s},
+@code{fa606te} (Faraday FA606TE processor),
+@code{fa616te} (Faraday FA616TE processor),
@code{fa626te} (Faraday FA626TE processor),
+@code{fmp626} (Faraday FMP626 processor),
@code{fa726te} (Faraday FA726TE processor),
@code{arm1136j-s},
@code{arm1136jf-s},
@code{arm1176jzf-s},
@code{mpcore},
@code{mpcorenovfp},
+@code{cortex-a5},
+@code{cortex-a7},
@code{cortex-a8},
@code{cortex-a9},
+@code{cortex-a15},
@code{cortex-r4},
@code{cortex-r4f},
+@code{cortex-r5},
+@code{cortex-r7},
+@code{cortex-m7},
+@code{cortex-m4},
@code{cortex-m3},
@code{cortex-m1},
@code{cortex-m0},
+@code{cortex-m0plus},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
-@code{xscale}.
+@code{xscale}.
The special name @code{all} may be used to allow the
assembler to accept instructions valid for any ARM processor.
-In addition to the basic instruction set, the assembler can be told to
-accept various extension mnemonics that extend the processor using the
+In addition to the basic instruction set, the assembler can be told to
+accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
-is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
-are currently supported:
-@code{+maverick}
-@code{+iwmmxt}
+is equivalent to specifying @code{-mcpu=ep9312}.
+
+Multiple extensions may be specified, separated by a @code{+}. The
+extensions should be specified in ascending alphabetical order.
+
+Some extensions may be restricted to particular architectures; this is
+documented in the list of extensions below.
+
+Extension mnemonics may also be removed from those the assembler accepts.
+This is done be prepending @code{no} to the option that adds the extension.
+Extensions that are removed should be listed after all extensions which have
+been added, again in ascending alphabetical order. For example,
+@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
+
+
+The following extensions are currently supported:
+@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
+@code{fp} (Floating Point Extensions for v8-A architecture),
+@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
+@code{iwmmxt},
+@code{iwmmxt2},
+@code{maverick},
+@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
+@code{os} (Operating System for v6M architecture),
+@code{sec} (Security Extensions for v6K and v7-A architectures),
+@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
+@code{virt} (Virtualization Extensions for v7-A architecture, implies
+@code{idiv}),
and
-@code{+xscale}.
+@code{xscale}.
@cindex @code{-march=} command line option, ARM
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
-will not execute on the target architecture. The following architecture
-names are recognized:
+will not execute on the target architecture. The following architecture
+names are recognized:
@code{armv1},
@code{armv2},
@code{armv2a},
@code{armv6k},
@code{armv6z},
@code{armv6zk},
+@code{armv6-m},
+@code{armv6s-m},
@code{armv7},
@code{armv7-a},
+@code{armv7ve},
@code{armv7-r},
@code{armv7-m},
+@code{armv7e-m},
+@code{armv8-a},
@code{iwmmxt}
and
@code{xscale}.
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
-an instruction which will not execute on the target floating point unit.
+an instruction which will not execute on the target floating point unit.
The following format options are recognized:
@code{softfpa},
@code{fpe},
@code{vfp10-r0},
@code{vfp9},
@code{vfpxd},
-@code{vfpv2}
-@code{vfpv3}
-@code{vfpv3-d16}
+@code{vfpv2},
+@code{vfpv3},
+@code{vfpv3-fp16},
+@code{vfpv3-d16},
+@code{vfpv3-d16-fp16},
+@code{vfpv3xd},
+@code{vfpv3xd-d16},
+@code{vfpv4},
+@code{vfpv4-d16},
+@code{fpv4-sp-d16},
+@code{fpv5-sp-d16},
+@code{fpv5-d16},
+@code{fp-armv8},
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
-@code{maverick}
+@code{maverick},
+@code{neon},
+@code{neon-vfpv4},
+@code{neon-fp-armv8},
and
-@code{neon}.
+@code{crypto-neon-fp-armv8}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
-The default is dependent on the processor selected. For Architecture 5 or
-later, the default is to assembler for VFP instructions; for earlier
+The default is dependent on the processor selected. For Architecture 5 or
+later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
@cindex @code{-mthumb} command line option, ARM
@item -mthumb
This option specifies that the assembler should start assembling Thumb
-instructions; that is, it should behave as though the file starts with a
+instructions; that is, it should behave as though the file starts with a
@code{.code 16} directive.
@cindex @code{-mthumb-interwork} command line option, ARM
@cindex @code{-matpcs} command line option, ARM
@item -matpcs
-This option specifies that the output generated by the assembler should
+This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
Enable or disable warnings about using deprecated options or
features. The default is to warn.
+@cindex @code{-mccs} command line option, ARM
+@item -mccs
+Turns on CodeComposer Studio assembly syntax compatibility mode.
+
@end table
* ARM-Chars:: Special Characters
* ARM-Regs:: Register Names
* ARM-Relocations:: Relocations
+* ARM-Neon-Alignment:: NEON Alignment Specifiers
@end menu
@node ARM-Instruction-Set
@code{unified} syntax, which can be selected via the @code{.syntax}
directive, and has the following main features:
-@table @bullet
+@itemize @bullet
@item
Immediate operands do not require a @code{#} prefix.
@item
All instructions set the flags if and only if they have an @code{s}
affix.
-@end table
+@end itemize
@node ARM-Chars
@subsection Special Characters
@cindex line comment character, ARM
@cindex ARM line comment character
-The presence of a @samp{@@} on a line indicates the start of a comment
-that extends to the end of the current line. If a @samp{#} appears as
-the first character of a line, the whole line is treated as a comment.
+The presence of a @samp{@@} anywhere on a line indicates the start of
+a comment that extends to the end of that line.
+
+If a @samp{#} appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be
+a logical line number directive (@pxref{Comments}) or a preprocessor
+control command (@pxref{Preprocessing}).
@cindex line separator, ARM
@cindex statement separator, ARM
@cindex register names, ARM
*TODO* Explain about ARM register naming, and the predefined names.
-@node ARM Floating Point
-@section Floating Point
-
-@cindex floating point, ARM (@sc{ieee})
-@cindex ARM floating point (@sc{ieee})
-The ARM family uses @sc{ieee} floating-point numbers.
-
@node ARM-Relocations
@subsection ARM relocation generation
@code{TLSGD},
@code{TLSLDM},
@code{TLSLDO},
-@code{GOTTPOFF}
+@code{TLSDESC},
+@code{TLSCALL},
+@code{GOTTPOFF},
+@code{GOT_PREL}
and
@code{TPOFF}.
For compatibility with older toolchains the assembler also accepts
-@code{(PLT)} after branch targets. This will generate the deprecated
-@samp{R_ARM_PLT32} relocation.
+@code{(PLT)} after branch targets. On legacy targets this will
+generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
+targets it will encode either the @samp{R_ARM_CALL} or
+@samp{R_ARM_JUMP24} relocation, as appropriate.
@cindex MOVW and MOVT relocations, ARM
Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
MOVT r0, #:upper16:foo
@end smallexample
+@node ARM-Neon-Alignment
+@subsection NEON Alignment Specifiers
+
+@cindex alignment for NEON instructions
+Some NEON load/store instructions allow an optional address
+alignment qualifier.
+The ARM documentation specifies that this is indicated by
+@samp{@@ @var{align}}. However GAS already interprets
+the @samp{@@} character as a "line comment" start,
+so @samp{: @var{align}} is used instead. For example:
+
+@smallexample
+ vld1.8 @{q0@}, [r0, :128]
+@end smallexample
+
+@node ARM Floating Point
+@section Floating Point
+
+@cindex floating point, ARM (@sc{ieee})
+@cindex ARM floating point (@sc{ieee})
+The ARM family uses @sc{ieee} floating-point numbers.
+
@node ARM Directives
@section ARM Machine Directives
Select the target architecture. Valid values for @var{name} are the same as
for the @option{-march} commandline option.
+Specifying @code{.arch} clears any previously selected architecture
+extensions.
+
+@cindex @code{.arch_extension} directive, ARM
+@item .arch_extension @var{name}
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} commandline option.
+
+@code{.arch_extension} may be used multiple times to add or remove extensions
+incrementally to the architecture being compiled for.
+
@cindex @code{.arm} directive, ARM
@item .arm
This performs the same action as @var{.code 32}.
-@anchor{arm_pad}
-@cindex @code{.pad} directive, ARM
-@item .pad #@var{count}
-Generate unwinder annotations for a stack adjustment of @var{count} bytes.
-A positive value indicates the function prologue allocated stack space by
-decrementing the stack pointer.
-
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, ARM
Select the target processor. Valid values for @var{name} are the same as
for the @option{-mcpu} commandline option.
+Specifying @code{.cpu} clears any previously selected architecture
+extensions.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
@cindex @code{.dn} and @code{.qn} directives, ARM
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
-@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
+@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
The @code{dn} and @code{qn} directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
The @var{tag} is either an attribute number, or one of the following:
@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
-@code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
+@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
@code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
@code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
-@code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
+@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
@code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
@code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
@code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
@code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
-@code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
+@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
+@code{Tag_MPextension_use}, @code{Tag_DIV_use},
@code{Tag_nodefaults}, @code{Tag_also_compatible_with},
@code{Tag_conformance}, @code{Tag_T2EE_use},
-@code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
+@code{Tag_Virtualization_use}
The @var{value} is either a @code{number}, @code{"string"}, or
@code{number, "string"} depending on the tag.
+Note - the following legacy values are also accepted by @var{tag}:
+@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
+@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
+
@cindex @code{.even} directive, ARM
@item .even
This directive aligns to an even-numbered address.
@cindex @code{.inst} directive, ARM
@item .inst @var{opcode} [ , @dots{} ]
-@item .inst.n @var{opcode} [ , @dots{} ]
-@item .inst.w @var{opcode} [ , @dots{} ]
+@itemx .inst.n @var{opcode} [ , @dots{} ]
+@itemx .inst.w @var{opcode} [ , @dots{} ]
Generates the instruction corresponding to the numerical value @var{opcode}.
@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
output section. These are not compatible with current ARM processors
or ABIs.
+@anchor{arm_pad}
@cindex @code{.pad} directive, ARM
@item .pad #@var{count}
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
Make all unwinder annotations relative to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
-The syntax of this directive is the same as the @code{sub} or @code{mov}
+The syntax of this directive is the same as the @code{add} or @code{mov}
instruction used to set the frame pointer. @var{spreg} must be either
@code{sp} or mentioned in a previous @code{.movsp} directive.
mov ip, sp
@dots{}
.setfp fp, ip, #4
-sub fp, ip, #4
+add fp, ip, #4
@end smallexample
@cindex @code{.secrel32} directive, ARM
the aliased symbol as being a thumb function entry point, in the same
way that the @code{.thumb_func} directive does.
+@cindex @code{.tlsdescseq} directive, ARM
+@item .tlsdescseq @var{tls-variable}
+This directive is used to annotate parts of an inlined TLS descriptor
+trampoline. Normally the trampoline is provided by the linker, and
+this directive is not needed.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, ARM
@cindex opcodes for ARM
@code{@value{AS}} implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
-instructions.
+instructions.
@table @code
nothing. Currently it will evaluate to MOV r0, r0.
@cindex @code{LDR reg,=<label>} pseudo op, ARM
-@item LDR
+@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
will not make use of the literal pool.
@cindex @code{ADRL reg,<label>} pseudo op, ARM
-@item ADRL
+@item ADRL
@smallexample
adrl <register> <label>
@end smallexample
@verbatim
void callee (int *);
-int
-caller ()
+int
+caller ()
{
int i;
callee (&i);
- return i;
+ return i;
}
@end verbatim
op appears immediately before the first instruction of the function
while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
op appears immediately after the last instruction of the function.
-These pseudo ops specify the range of the function.
+These pseudo ops specify the range of the function.
Only the order of the other pseudos ops (e.g., @code{.setfp} or
@code{.pad}) matters; their exact locations are irrelevant. In the
projects / deliverable / binutils-gdb.git / blobdiff