* dwarf_reader.cc (Sized_dwarf_line_info::read_header_prolog,

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 7fede6cf9f9eec74d1f75632ff71205cda782ff5..7ad4a34abb7df982ddfbb4fbf8397544f5c9f83d 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -108,6 +108,7 @@ recognized:
 @code{mpcore},
 @code{mpcorenovfp},
 @code{cortex-a8},
+@code{cortex-a9},
 @code{cortex-r4},
 @code{cortex-m3},
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@@ -155,9 +156,9 @@ names are recognized:
 @code{armv6z},
 @code{armv6zk},
 @code{armv7},
-@code{armv7a},
-@code{armv7r},
-@code{armv7m},
+@code{armv7-a},
+@code{armv7-r},
+@code{armv7-m},
 @code{iwmmxt}
 and
 @code{xscale}.
@@ -190,11 +191,15 @@ The following format options are recognized:
 @code{vfp10-r0},
 @code{vfp9},
 @code{vfpxd},
+@code{vfpv2}
+@code{vfpv3}
+@code{vfpv3-d16}
 @code{arm1020t},
 @code{arm1020e},
-@code{arm1136jf-s}
+@code{arm1136jf-s},
+@code{maverick}
 and
-@code{maverick}.
+@code{neon}.
 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves
@@ -276,6 +281,11 @@ be marked as being encoded for a little-endian processor.
 This option specifies that the output of the assembler should be marked
 as position-independent code (PIC).
 
+@cindex @code{--fix-v4bx} command line option, ARM
+@item --fix-v4bx
+Allow @code{BX} instructions in ARMv4 code.  This is intended for use with
+the linker option of the same name.
+
 @end table
 
 
@@ -391,7 +401,7 @@ example:
 @cindex @code{unreq} directive, ARM
 @item .unreq @var{alias-name}
 This undefines a register alias which was previously defined using the
-@code{req} directive.  For example:
+@code{req}, @code{dn} or @code{qn} directives.  For example:
 
 @smallexample
         foo .req r0
@@ -402,6 +412,36 @@ An error occurs if the name is undefined.  Note - this pseudo op can
 be used to delete builtin in register name aliases (eg 'r0').  This
 should only be done if it is really necessary.
 
+@cindex @code{dn} and @code{qn} directives, ARM
+@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
+@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
+
+The @code{dn} and @code{qn} directives are used to create typed
+and/or indexed register aliases for use in Advanced SIMD Extension
+(Neon) instructions.  The former should be used to create aliases
+of double-precision registers, and the latter to create aliases of
+quad-precision registers.
+
+If these directives are used to create typed aliases, those aliases can
+be used in Neon instructions instead of writing types after the mnemonic
+or after each operand.  For example:
+
+@smallexample
+        x .dn d2.f32
+        y .dn d3.f32
+        z .dn d4.f32[1]
+        vmul x,y,z
+@end smallexample
+
+This is equivalent to writing the following:
+
+@smallexample
+        vmul.f32 d2,d3,d4[1]
+@end smallexample
+
+Aliases created using @code{dn} or @code{qn} can be destroyed using
+@code{unreq}.
+
 @cindex @code{code} directive, ARM
 @item .code @code{[16|32]}
 This directive selects the instruction set being generated. The value 16
@@ -429,6 +469,9 @@ between Arm and Thumb instructions and should be used even if
 interworking is not going to be performed.  The presence of this
 directive also implies @code{.thumb}
 
+This directive is not neccessary when generating EABI objects.  On these
+targets the encoding is implicit when generating Thumb code.
+
 @cindex @code{thumb_set} directive, ARM
 @item .thumb_set
 This performs the equivalent of a @code{.set} directive in that it
@@ -585,6 +628,12 @@ for the @option{-mcpu} commandline option.
 Select the target architecture.  Valid values for @var{name} are the same as
 for the @option{-march} commandline option.
 
+@cindex @code{.object_arch} directive, ARM
+@item .object_arch @var{name}
+Override the architecture recorded in the EABI object attribute section.
+Valid values for @var{name} are the same as for the @code{.arch} directive.
+Typically this is useful when code uses runtime detection of CPU features.
+
 @cindex @code{.fpu} directive, ARM
 @item .fpu @var{name}
 Select the floating point unit to assemble for.  Valid values for @var{name}