PowerPC Rename powerxx to power10

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 481eddf0cfe6a4483717fab9dd21b3c185340fc0..91803605775418bcc795e163f42b0beaec880967 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1996-2019 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2020 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -129,6 +129,8 @@ recognized:
 @code{cortex-a73},
 @code{cortex-a75},
 @code{cortex-a76},
+@code{cortex-a76ae},
+@code{cortex-a77},
 @code{ares},
 @code{cortex-r4},
 @code{cortex-r4f},
@@ -136,6 +138,7 @@ recognized:
 @code{cortex-r7},
 @code{cortex-r8},
 @code{cortex-r52},
+@code{cortex-m35p},
 @code{cortex-m33},
 @code{cortex-m23},
 @code{cortex-m7},
@@ -177,6 +180,8 @@ been added, again in ascending alphabetical order.  For example,
 
 
 The following extensions are currently supported:
+@code{bf16} (BFloat16 extensions for v8.6-A architecture),
+@code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
 @code{crc}
 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
@@ -251,6 +256,7 @@ names are recognized:
 @code{armv8-m.base},
 @code{armv8-m.main},
 @code{armv8.1-m.main},
+@code{armv8.6-a},
 @code{iwmmxt},
 @code{iwmmxt2}
 and
@@ -353,6 +359,14 @@ For @code{armv8-m.main}:
 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
 double-word registers.
 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
+@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
+@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
+@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
+@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
+@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
+@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
+@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
 @code{+nofp}: Disables all FPU instructions.
 @code{+nodsp}: Disables DSP Extension.