Add .noavx512XX directives to x86 assembler

[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index eb6790cf80ba7a2e901931e3386056577b163b80..30e29f6202988544af50581844f89d1e923c8208 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1991-2015 Free Software Foundation, Inc.
+@c Copyright (C) 1991-2016 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c man end
@@ -110,6 +110,7 @@ processor names are recognized:
 @code{corei7},
 @code{l1om},
 @code{k1om},
+@code{iamcu},
 @code{k6},
 @code{k6_2},
 @code{athlon},
@@ -133,7 +134,11 @@ accept various extension mnemonics.  For example,
 @code{8087},
 @code{287},
 @code{387},
+@code{687},
 @code{no87},
+@code{no287},
+@code{no387},
+@code{no687},
 @code{mmx},
 @code{nommx},
 @code{sse},
@@ -144,14 +149,23 @@ accept various extension mnemonics.  For example,
 @code{sse4.2},
 @code{sse4},
 @code{nosse},
+@code{nosse2},
+@code{nosse3},
+@code{nossse3},
+@code{nosse4.1},
+@code{nosse4.2},
+@code{nosse4},
 @code{avx},
 @code{avx2},
+@code{noavx},
+@code{noavx2},
 @code{adx},
 @code{rdseed},
 @code{prfchw},
 @code{smap},
 @code{mpx},
 @code{sha},
+@code{rdpid},
 @code{prefetchwt1},
 @code{clflushopt},
 @code{se1},
@@ -166,7 +180,15 @@ accept various extension mnemonics.  For example,
 @code{avx512dq},
 @code{avx512ifma},
 @code{avx512vbmi},
-@code{noavx},
+@code{noavx512f},
+@code{noavx512cd},
+@code{noavx512er},
+@code{noavx512pf},
+@code{noavx512vl},
+@code{noavx512bw},
+@code{noavx512dq},
+@code{noavx512ifma},
+@code{noavx512vbmi},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -188,6 +210,7 @@ accept various extension mnemonics.  For example,
 @code{rtm},
 @code{invpcid},
 @code{clflush},
+@code{mwaitx},
 @code{clzero},
 @code{lwp},
 @code{fma4},
@@ -297,15 +320,16 @@ The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
 This option forces the assembler to add BND prefix to all branches, even
 if such prefix was not explicitly specified in the source code.
 
-@cindex @samp{-mno-shared} option, i386
-@cindex @samp{-mno-shared} option, x86-64
+@cindex @samp{-mshared} option, i386
+@cindex @samp{-mshared} option, x86-64
 @item -mno-shared
-On ELF target, the assembler normally generates code which can go into a
-shared library where non-weak symbols can be preempted.  The
-@samp{-mno-shared} option tells the assembler to generate code not for
-a shared library, where non-weak symbols won't be preempted.  The
-resulting code is slightly smaller.  This option mainly affects the
-handling of branch instructions.
+On ELF target, the assembler normally optimizes out non-PLT relocations
+against defined non-weak global branch targets with default visibility.
+The @samp{-mshared} option tells the assembler to generate code which
+may go into a shared library where all non-weak global branch targets
+with default visibility can be preempted.  The resulting code is
+slightly bigger.  This option only affects the handling of branch
+instructions.
 
 @cindex @samp{-mbig-obj} option, x86-64
 @item -mbig-obj
@@ -324,6 +348,30 @@ single-thread computers
 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
 which is the default.
 
+@cindex @samp{-mfence-as-lock-add=} option, i386
+@cindex @samp{-mfence-as-lock-add=} option, x86-64
+@item -mfence-as-lock-add=@var{no}
+@itemx -mfence-as-lock-add=@var{yes}
+These options control how the assembler should encode lfence, mfence and
+sfence.
+@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
+sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
+@samp{lock addl $0x0, (%esp)} in 32-bit mode.
+@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
+sfence as usual, which is the default.
+
+@cindex @samp{-mrelax-relocations=} option, i386
+@cindex @samp{-mrelax-relocations=} option, x86-64
+@item -mrelax-relocations=@var{no}
+@itemx -mrelax-relocations=@var{yes}
+These options control whether the assembler should generate relax
+relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
+R_X86_64_REX_GOTPCRELX, in 64-bit mode.
+@option{-mrelax-relocations=@var{yes}} will generate relax relocations.
+@option{-mrelax-relocations=@var{no}} will not generate relax
+relocations.  The default can be controlled by a configure option
+@option{--enable-x86-relax-relocations}.
+
 @cindex @samp{-mevexrcig=} option, i386
 @cindex @samp{-mevexrcig=} option, x86-64
 @item -mevexrcig=@var{rne}
@@ -337,6 +385,13 @@ of EVEX instruction with 00, which is the default.
 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
 with 01, 10 and 11 RC bits, respectively.
 
+@cindex @samp{-mamd64} option, x86-64
+@cindex @samp{-mintel64} option, x86-64
+@item -mamd64
+@itemx -mintel64
+This option specifies that the assembler should accept only AMD64 or
+Intel64 ISA in 64-bit mode.  The default is to accept both.
+
 @end table
 @c man end
 
@@ -629,8 +684,8 @@ the 6 section registers @samp{%cs} (code section), @samp{%ds}
 and @samp{%gs}.
 
 @item
-the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
-@samp{%cr3}.
+the 5 processor control registers @samp{%cr0}, @samp{%cr2},
+@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
 
 @item
 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
@@ -648,7 +703,7 @@ These registers are overloaded by 8 MMX registers @samp{%mm0},
 @samp{%mm6} and @samp{%mm7}.
 
 @item
-the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
+the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
 @end itemize
 
@@ -665,13 +720,13 @@ pointer)
 the 8 extended registers @samp{%r8}--@samp{%r15}.
 
 @item
-the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
+the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
 
 @item
-the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
+the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
 
 @item
-the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
+the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
 
 @item
 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
@@ -680,7 +735,43 @@ the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
 the 8 debug registers: @samp{%db8}--@samp{%db15}.
 
 @item
-the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
+the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
+@end itemize
+
+With the AVX extensions more registers were made available:
+
+@itemize @bullet
+
+@item
+the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
+available in 32-bit mode).  The bottom 128 bits are overlaid with the
+@samp{xmm0}--@samp{xmm15} registers.
+
+@end itemize
+
+The AVX2 extensions made in 64-bit mode more registers available:
+
+@itemize @bullet
+
+@item
+the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
+registers @samp{%ymm16}--@samp{%ymm31}.
+
+@end itemize
+
+The AVX512 extensions added the following registers:
+
+@itemize @bullet
+
+@item
+the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
+available in 32-bit mode).  The bottom 128 bits are overlaid with the
+@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
+overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
+
+@item
+the 8 mask registers @samp{%k0}--@samp{%k7}.
+
 @end itemize
 
 @node i386-Prefixes
@@ -1082,7 +1173,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
-@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
+@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
@@ -1103,7 +1194,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
-@item @samp{.padlock} @tab @samp{.clzero}
+@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpid}
 @end multitable
 
 Apart from the warning, there are only two other effects on