gdb: add target_ops::supports_displaced_step

[deliverable/binutils-gdb.git] / gas / doc / c-s390.texi

diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index e3277cb06e6511597e221f3b6a0328990a2ab115..e812c533d49946bdd0f3eb70632e14c6c53cba36 100644 (file)
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2009-2016 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2020 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -14,9 +14,11 @@
 @cindex s390 support
 
 The s390 version of @code{@value{AS}} supports two architectures modes
-and seven chip levels. The architecture modes are the Enterprise System
+and eleven chip levels. The architecture modes are the Enterprise System
 Architecture (ESA) and the newer z/Architecture mode. The chip levels
-are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, zEC12, and z13.
+are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
+(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
+(or arch11), z14 (or arch12), and z15 (or arch13).
 
 @menu
 * s390 Options::                Command-line Options.
@@ -58,19 +60,33 @@ message.
 @item -march=@var{CPU}
 This option specifies the target processor. The following processor names
 are recognized:
-@code{g5},
+@code{g5} (or @code{arch3}),
 @code{g6},
-@code{z900},
-@code{z990},
+@code{z900} (or @code{arch5}),
+@code{z990} (or @code{arch6}),
 @code{z9-109},
-@code{z9-ec},
-@code{z10},
-@code{z196},
-@code{zEC12}, and
-@code{z13}.
-Assembling an instruction that is not supported on the target processor
-results in an error message. Do not specify @code{g5} or @code{g6}
-with @samp{-mzarch}.
+@code{z9-ec} (or @code{arch7}),
+@code{z10} (or @code{arch8}),
+@code{z196} (or @code{arch9}),
+@code{zEC12} (or @code{arch10}),
+@code{z13} (or @code{arch11}),
+@code{z14} (or @code{arch12}), and
+@code{z15} (or @code{arch13}).
+
+Assembling an instruction that is not supported on the target
+processor results in an error message.
+
+The processor names starting with @code{arch} refer to the edition
+number in the Principle of Operations manual.  They can be used as
+alternate processor names and have been added for compatibility with
+the IBM XL compiler.
+
+@code{arch3}, @code{g5} and @code{g6} cannot be used with the
+@samp{-mzarch} option since the z/Architecture mode is not supported
+on these processor levels.
+
+There is no @code{arch4} option supported. @code{arch4} matches
+@code{-march=arch5 -mesa}.
 
 @cindex @samp{-mregnames} option, s390
 @item -mregnames
@@ -210,7 +226,7 @@ of the instruction:
 @end display
 
 There are many exceptions to the scheme outlined in the above lists, in
-particular for the priviledged instructions. For non-priviledged
+particular for the privileged instructions. For non-privileged
 instruction it works quite well, for example the instruction @samp{clgfr}
 c: compare instruction, l: unsigned operands, g: 64-bit operands,
 f: 32- to 64-bit extension, r: register operands. The instruction compares
@@ -272,7 +288,7 @@ register Xn called the index register, general register Bn called the
 base register and the displacement field Dn.
 @item Dn(Ln,Bn)
 the address for operand number n is formed from the content of general
-regiser Bn called the base register and the displacement field Dn.
+register Bn called the base register and the displacement field Dn.
 The length of the operand n is specified by the field Ln.
 @end table
 
@@ -875,7 +891,7 @@ push} saves the currently selected cpu, which may be restored with
 into double quotes in case it contains characters not appropriate
 for identifiers.  So you have to write @code{"z9-109"} instead of
 just @code{z9-109}.  Extensions can be specified after the cpu
-name, separated by plus charaters.  Valid extensions are:
+name, separated by plus characters.  Valid extensions are:
 @code{htm},
 @code{nohtm},
 @code{vx},