-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002
-@c Free Software Foundation, Inc.
+@c Copyright (C) 1991-2014 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@cindex SPARC options
@cindex architectures, SPARC
@cindex SPARC architectures
-The SPARC chip family includes several successive levels, using the same
+The SPARC chip family includes several successive versions, using the same
core instruction set, but including a few additional instructions at
-each level. There are exceptions to this however. For details on what
+each version. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
only exist in the higher levels.
If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
-passed sparclite by default, an option must be passed to enable the
+past sparclite by default, an option must be passed to enable the
v9 instructions.
GAS treats sparclite as being compatible with v8, unless an architecture
@table @code
@kindex -Av6
-@kindex Av7
+@kindex -Av7
@kindex -Av8
+@kindex -Aleon
@kindex -Asparclet
@kindex -Asparclite
@kindex -Av9
@kindex -Av9a
-@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-@itemx -Av8plus | -Av8plusa | -Av9 | -Av9a
+@kindex -Av9b
+@kindex -Av9c
+@kindex -Av9d
+@kindex -Av9v
+@kindex -Asparc
+@kindex -Asparcvis
+@kindex -Asparcvis2
+@kindex -Asparcfmaf
+@kindex -Asparcima
+@kindex -Asparcvis3
+@kindex -Asparcvis3r
+@item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
+@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
+@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
+@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
+@itemx -Asparcvis3 | -Asparcvis3r
Use one of the @samp{-A} options to select one of the SPARC
architectures explicitly. If you select an architecture explicitly,
@code{@value{AS}} reports a fatal error if it encounters an instruction
or feature requiring an incompatible or higher level.
-@samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment.
+@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
+@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
-@samp{-Av9} and @samp{-Av9a} select a 64 bit environment and are not
-available unless GAS is explicitly configured with 64 bit environment
-support.
+@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
+@samp{-Av9v} select a 64 bit environment and are not available unless GAS
+is explicitly configured with 64 bit environment support.
@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
-UltraSPARC extensions.
+UltraSPARC VIS 1.0 extensions.
-@item -xarch=v8plus | -xarch=v8plusa
-For compatibility with the Solaris v9 assembler. These options are
-equivalent to -Av8plus and -Av8plusa, respectively.
+@samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
+as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
+
+@samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
+as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
+
+@samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
+multiply-add, VIS 3.0, and HPC extension instructions, as well as the
+instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
+
+@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
+memory, floating point unfused multiply-add, integer multiply-add, and
+cache sparing store instructions, as well as the instructions enabled
+by @samp{-Av8plusd} and @samp{-Av9d}.
+
+@samp{-Asparc} specifies a v9 environment. It is equivalent to
+@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
+
+@samp{-Asparcvis} specifies a v9a environment. It is equivalent to
+@samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
+
+@samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
+@samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
+
+@samp{-Asparcfmaf} specifies a v9b environment with the floating point
+fused multiply-add instructions enabled.
+
+@samp{-Asparcima} specifies a v9b environment with the integer
+multiply-add instructions enabled.
+
+@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
+HPC , and floating point fused multiply-add instructions enabled.
+
+@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
+HPC, transactional memory, random, and floating point unfused multiply-add
+instructions enabled.
+
+@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
+@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
+@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
+@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
+@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
+@itemx -xarch=sparcvis3r
+For compatibility with the SunOS v9 assembler. These options are
+equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
+-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
+-Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
+respectively.
@item -bump
Warn whenever it is necessary to switch to another level.
@cindex SPARC data alignment
SPARC GAS normally permits data to be misaligned. For example, it
permits the @code{.long} pseudo-op to be used on a byte boundary.
-However, the native SunOS and Solaris assemblers issue an error when
-they see misaligned data.
+However, the native SunOS assemblers issue an error when they see
+misaligned data.
@kindex --enforce-aligned-data
You can use the @code{--enforce-aligned-data} option to make SPARC GAS
-also issue an error about misaligned data, just as the SunOS and Solaris
+also issue an error about misaligned data, just as the SunOS
assemblers do.
The @code{--enforce-aligned-data} option is not the default because gcc
* Sparc-Regs:: Register Names
* Sparc-Constants:: Constant Names
* Sparc-Relocs:: Relocations
+* Sparc-Size-Translations:: Size Translations
@end menu
@node Sparc-Chars
@cindex line comment character, Sparc
@cindex Sparc line comment character
-@samp{#} is the line comment character.
+A @samp{!} character appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+If a @samp{#} appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be
+a logical line number directive (@pxref{Comments}) or a preprocessor
+control command (@pxref{Preprocessing}).
@cindex line separator, Sparc
@cindex statement separator, Sparc
Certain V9 instructions allow access to ancillary state registers.
Most simply they can be referred to as @samp{%asr@var{n}} where
-@var{n} can be from 16 to 31. However, there are some aliased
+@var{n} can be from 16 to 31. However, there are some aliases
defined to reference ASR registers defined for various UltraSPARC
processors:
@item
The set software interrupt register is referred to as @samp{%set_softint}.
+The mnemonic @samp{%softint_set} is provided as an alias.
@item
The clear software interrupt register is referred to as
-@samp{%clear_softint}.
+@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
+as an alias.
@item
The performance instrumentation counters register is referred to as
The graphics status register is referred to as @samp{%gsr}.
@item
-The dispatch control register is referred to as @samp{%dcr}.
+The V9 dispatch control register is referred to as @samp{%dcr}.
@end itemize
Various V9 branch and conditional move instructions allow
The floating-point queue register is referred to as @samp{%fq}.
@item
-The co-processor queue register is referred to as @samp{%cq}.
+The V8 co-processor queue register is referred to as @samp{%cq}.
@item
The floating point status register is referred to as @samp{%fsr}.
The V8 processor state register is referred to as @samp{%psr}.
@item
-The global register level register is referred to as @samp{%gl}.
+The V9 global register level register is referred to as @samp{%gl}.
@end itemize
Several special register names exist for hypervisor mode code:
@item
@code{R_SPARC_M44} is requested using @samp{%m44}.
@item
-@code{R_SPARC_L44} is requested using @samp{%l44}.
+@code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
+@item
+@code{R_SPARC_H34} is requested using @samp{%h34}.
@end itemize
+The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
+calculates the necessary value, and therefore no explicit
+@code{R_SPARC_L34} relocation needed to be created for this purpose.
+
+The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
+model. Here is an example abs34 address generation sequence:
+
+@example
+sethi %h34(symbol), %g1
+sllx %g1, 2, %g1
+or %g1, %l34(symbol), %g1
+@end example
+
The PC relative relocation @code{R_SPARC_PC22} can be obtained by
enclosing an operand inside of @samp{%pc22}. Likewise, the
@code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
an @code{R_SPARC_LO10} relocation, the assembler will emit an
@code{R_SPARC_OLO10} instead.
+@node Sparc-Size-Translations
+@subsection Size Translations
+@cindex Sparc size translations
+@cindex size, translations, Sparc
+
+Often it is desirable to write code in an operand size agnostic
+manner. @code{@value{AS}} provides support for this via
+operand size opcode translations. Translations are supported
+for loads, stores, shifts, compare-and-swap atomics, and the
+@samp{clr} synthetic instruction.
+
+If generating 32-bit code, @code{@value{AS}} will generate the
+32-bit opcode. Whereas if 64-bit code is being generated,
+the 64-bit opcode will be emitted. For example @code{ldn}
+will be transformed into @code{ld} for 32-bit code and
+@code{ldx} for 64-bit code.
+
+Here is an example meant to demonstrate all the supported
+opcode translations:
+
+@example
+ldn [%o0], %o1
+ldna [%o0] %asi, %o2
+stn %o1, [%o0]
+stna %o2, [%o0] %asi
+slln %o3, 3, %o3
+srln %o4, 8, %o4
+sran %o5, 12, %o5
+casn [%o0], %o1, %o2
+casna [%o0] %asi, %o1, %o2
+clrn %g1
+@end example
+
+In 32-bit mode @code{@value{AS}} will emit:
+
+@example
+ld [%o0], %o1
+lda [%o0] %asi, %o2
+st %o1, [%o0]
+sta %o2, [%o0] %asi
+sll %o3, 3, %o3
+srl %o4, 8, %o4
+sra %o5, 12, %o5
+cas [%o0], %o1, %o2
+casa [%o0] %asi, %o1, %o2
+clr %g1
+@end example
+
+And in 64-bit mode @code{@value{AS}} will emit:
+
+@example
+ldx [%o0], %o1
+ldxa [%o0] %asi, %o2
+stx %o1, [%o0]
+stxa %o2, [%o0] %asi
+sllx %o3, 3, %o3
+srlx %o4, 8, %o4
+srax %o5, 12, %o5
+casx [%o0], %o1, %o2
+casxa [%o0] %asi, %o1, %o2
+clrx %g1
+@end example
+
+Finally, the @samp{.nword} translating directive is supported
+as well. It is documented in the section on Sparc machine
+directives.
+
@node Sparc-Float
@section Floating Point
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