-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@cindex SPARC options
@cindex architectures, SPARC
@cindex SPARC architectures
-The SPARC chip family includes several successive levels, using the same
+The SPARC chip family includes several successive versions, using the same
core instruction set, but including a few additional instructions at
-each level. There are exceptions to this however. For details on what
+each version. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
only exist in the higher levels.
If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
-passed sparclite by default, an option must be passed to enable the
+past sparclite by default, an option must be passed to enable the
v9 instructions.
GAS treats sparclite as being compatible with v8, unless an architecture
UltraSPARC extensions.
@item -xarch=v8plus | -xarch=v8plusa
-For compatibility with the Solaris v9 assembler. These options are
+For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus and -Av8plusa, respectively.
@item -bump
@cindex SPARC data alignment
SPARC GAS normally permits data to be misaligned. For example, it
permits the @code{.long} pseudo-op to be used on a byte boundary.
-However, the native SunOS and Solaris assemblers issue an error when
-they see misaligned data.
+However, the native SunOS assemblers issue an error when they see
+misaligned data.
@kindex --enforce-aligned-data
You can use the @code{--enforce-aligned-data} option to make SPARC GAS
-also issue an error about misaligned data, just as the SunOS and Solaris
+also issue an error about misaligned data, just as the SunOS
assemblers do.
The @code{--enforce-aligned-data} option is not the default because gcc
@menu
* Sparc-Chars:: Special Characters
* Sparc-Regs:: Register Names
+* Sparc-Constants:: Constant Names
* Sparc-Relocs:: Relocations
+* Sparc-Size-Translations:: Size Translations
@end menu
@node Sparc-Chars
Certain V9 instructions allow access to ancillary state registers.
Most simply they can be referred to as @samp{%asr@var{n}} where
-@var{n} can be from 16 to 31. However, there are some aliased
+@var{n} can be from 16 to 31. However, there are some aliases
defined to reference ASR registers defined for various UltraSPARC
processors:
The tick compare register is referred to as @samp{%tick_cmpr}.
@item
-The system tick register is referred to as @samp{%sys_tick}.
+The system tick register is referred to as @samp{%stick}. An alias,
+@samp{%sys_tick}, exists but is deprecated and should not be used
+by new software.
@item
-The system tick compare register is referred to as @samp{%sys_tick_cmpr}.
+The system tick compare register is referred to as @samp{%stick_cmpr}.
+An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
+not be used by new software.
@item
The software interrupt register is referred to as @samp{%softint}.
@item
The set software interrupt register is referred to as @samp{%set_softint}.
+The mnemonic @samp{%softint_set} is provided as an alias.
@item
The clear software interrupt register is referred to as
-@samp{%clear_softint}.
+@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
+as an alias.
@item
The performance instrumentation counters register is referred to as
The graphics status register is referred to as @samp{%gsr}.
@item
-The dispatch control register is referred to as @samp{%dcr}.
+The V9 dispatch control register is referred to as @samp{%dcr}.
@end itemize
Various V9 branch and conditional move instructions allow
The floating-point queue register is referred to as @samp{%fq}.
@item
-The co-processor queue register is referred to as @samp{%cq}.
+The V8 co-processor queue register is referred to as @samp{%cq}.
@item
The floating point status register is referred to as @samp{%fsr}.
The V8 processor state register is referred to as @samp{%psr}.
@item
-The global register level register is referred to as @samp{%gl}.
+The V9 global register level register is referred to as @samp{%gl}.
@end itemize
Several special register names exist for hypervisor mode code:
@item
The hyperprivileged system tick compare register is referred
-to as @samp{%hstick_cmpr}.
+to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
+register, the normal @samp{%stick} is used.
+@end itemize
+
+@node Sparc-Constants
+@subsection Constants
+@cindex Sparc constants
+@cindex constants, Sparc
+
+Several Sparc instructions take an immediate operand field for
+which mnemonic names exist. Two such examples are @samp{membar}
+and @samp{prefetch}. Another example are the set of V9
+memory access instruction that allow specification of an
+address space identifier.
+
+The @samp{membar} instruction specifies a memory barrier that is
+the defined by the operand which is a bitmask. The supported
+mask mnemonics are:
+
+@itemize @bullet
+@item
+@samp{#Sync} requests that all operations (including nonmemory
+reference operations) appearing prior to the @code{membar} must have
+been performed and the effects of any exceptions become visible before
+any instructions after the @code{membar} may be initiated. This
+corresponds to @code{membar} cmask field bit 2.
+
+@item
+@samp{#MemIssue} requests that all memory reference operations
+appearing prior to the @code{membar} must have been performed before
+any memory operation after the @code{membar} may be initiated. This
+corresponds to @code{membar} cmask field bit 1.
+
+@item
+@samp{#Lookaside} requests that a store appearing prior to the
+@code{membar} must complete before any load following the
+@code{membar} referencing the same address can be initiated. This
+corresponds to @code{membar} cmask field bit 0.
+
+@item
+@samp{#StoreStore} defines that the effects of all stores appearing
+prior to the @code{membar} instruction must be visible to all
+processors before the effect of any stores following the
+@code{membar}. Equivalent to the deprecated @code{stbar} instruction.
+This corresponds to @code{membar} mmask field bit 3.
+
+@item
+@samp{#LoadStore} defines all loads appearing prior to the
+@code{membar} instruction must have been performed before the effect
+of any stores following the @code{membar} is visible to any other
+processor. This corresponds to @code{membar} mmask field bit 2.
+
+@item
+@samp{#StoreLoad} defines that the effects of all stores appearing
+prior to the @code{membar} instruction must be visible to all
+processors before loads following the @code{membar} may be performed.
+This corresponds to @code{membar} mmask field bit 1.
+
+@item
+@samp{#LoadLoad} defines that all loads appearing prior to the
+@code{membar} instruction must have been performed before any loads
+following the @code{membar} may be performed. This corresponds to
+@code{membar} mmask field bit 0.
+
+@end itemize
+
+These values can be ored together, for example:
+
+@example
+membar #Sync
+membar #StoreLoad | #LoadLoad
+membar #StoreLoad | #StoreStore
+@end example
+
+The @code{prefetch} and @code{prefetcha} instructions take a prefetch
+function code. The following prefetch function code constant
+mnemonics are available:
+
+@itemize @bullet
+@item
+@samp{#n_reads} requests a prefetch for several reads, and corresponds
+to a prefetch function code of 0.
+
+@samp{#one_read} requests a prefetch for one read, and corresponds
+to a prefetch function code of 1.
+
+@samp{#n_writes} requests a prefetch for several writes (and possibly
+reads), and corresponds to a prefetch function code of 2.
+
+@samp{#one_write} requests a prefetch for one write, and corresponds
+to a prefetch function code of 3.
+
+@samp{#page} requests a prefetch page, and corresponds to a prefetch
+function code of 4.
+
+@samp{#invalidate} requests a prefetch invalidate, and corresponds to
+a prefetch function code of 16.
+
+@samp{#unified} requests a prefetch to the nearest unified cache, and
+corresponds to a prefetch function code of 17.
+
+@samp{#n_reads_strong} requests a strong prefetch for several reads,
+and corresponds to a prefetch function code of 20.
+
+@samp{#one_read_strong} requests a strong prefetch for one read,
+and corresponds to a prefetch function code of 21.
+
+@samp{#n_writes_strong} requests a strong prefetch for several writes,
+and corresponds to a prefetch function code of 22.
+
+@samp{#one_write_strong} requests a strong prefetch for one write,
+and corresponds to a prefetch function code of 23.
+
+Onle one prefetch code may be specified. Here are some examples:
+
+@example
+prefetch [%l0 + %l2], #one_read
+prefetch [%g2 + 8], #n_writes
+prefetcha [%g1] 0x8, #unified
+prefetcha [%o0 + 0x10] %asi, #n_reads
+@end example
+
+The actual behavior of a given prefetch function code is processor
+specific. If a processor does not implement a given prefetch
+function code, it will treat the prefetch instruction as a nop.
+
+For instructions that accept an immediate address space identifier,
+@code{@value{AS}} provides many mnemonics corresponding to
+V9 defined as well as UltraSPARC and Niagara extended values.
+For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
+See the V9 and processor specific manuals for details.
+
@end itemize
@node Sparc-Relocs
an @code{R_SPARC_LO10} relocation, the assembler will emit an
@code{R_SPARC_OLO10} instead.
+@node Sparc-Size-Translations
+@subsection Size Translations
+@cindex Sparc size translations
+@cindex size, translations, Sparc
+
+Often it is desirable to write code in an operand size agnostic
+manner. @code{@value{AS}} provides support for this via
+operand size opcode translations. Translations are supported
+for loads, stores, shifts, compare-and-swap atomics, and the
+@samp{clr} synthetic instruction.
+
+If generating 32-bit code, @code{@value{AS}} will generate the
+32-bit opcode. Whereas if 64-bit code is being generated,
+the 64-bit opcode will be emitted. For example @code{ldn}
+will be transformed into @code{ld} for 32-bit code and
+@code{ldx} for 64-bit code.
+
+Here is an example meant to demonstrate all the supported
+opcode translations:
+
+@example
+ldn [%o0], %o1
+ldna [%o0] %asi, %o2
+stn %o1, [%o0]
+stna %o2, [%o0] %asi
+slln %o3, 3, %o3
+srln %o4, 8, %o4
+sran %o5, 12, %o5
+casn [%o0], %o1, %o2
+casna [%o0] %asi, %o1, %o2
+clrn %g1
+@end example
+
+In 32-bit mode @code{@value{AS}} will emit:
+
+@example
+ld [%o0], %o1
+lda [%o0] %asi, %o2
+st %o1, [%o0]
+sta %o2, [%o0] %asi
+sll %o3, 3, %o3
+srl %o4, 8, %o4
+sra %o5, 12, %o5
+cas [%o0], %o1, %o2
+casa [%o0] %asi, %o1, %o2
+clr %g1
+@end example
+
+And in 64-bit mode @code{@value{AS}} will emit:
+
+@example
+ldx [%o0], %o1
+ldxa [%o0] %asi, %o2
+stx %o1, [%o0]
+stxa %o2, [%o0] %asi
+sllx %o3, 3, %o3
+srlx %o4, 8, %o4
+srax %o5, 12, %o5
+casx [%o0], %o1, %o2
+casxa [%o0] %asi, %o1, %o2
+clrx %g1
+@end example
+
+Finally, the @samp{.nword} translating directive is supported
+as well. It is documented in the section on Sparc machine
+directives.
+
@node Sparc-Float
@section Floating Point
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