Add support for .extCondCode, .extCoreRegister and .extAuxRegister.

[deliverable/binutils-gdb.git] / gas / testsuite / gas / arc / ld2.d

diff --git a/gas/testsuite/gas/arc/ld2.d b/gas/testsuite/gas/arc/ld2.d
index 1f1df97b5db7d569524b222e83deb658fb9583f1..0a7874ce33d87e6a22c1b1cfe454bf859730fb2a 100644 (file)
--- a/gas/testsuite/gas/arc/ld2.d
+++ b/gas/testsuite/gas/arc/ld2.d
@@ -1,21 +1,19 @@
-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=arc700
+#objdump: -dr --show-raw-insn
 
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
 
 Disassembly of section .text:
 
-00000000 <.text>:
-   0:  00 80 00 08     08008000     ld         r0,\[r1\]
-   4:  01 00 a3 08     08a30001     ld         r5,\[r6,1\]
-   8:  00 00 7f 0a     0a7f0000     ld         r19,\[0\]
-   c:  00 00 00 00 
-                       c: R_ARC_32     foo
-  10:  0a 10 81 08     0881100a     ld.a       r4,\[r2,10\]
-  14:  00 00 3f 08     083f0000     ld         r1,\[0x384\]
-  18:  84 03 00 00 
-  1c:  0f 84 41 08     0841840f     ldb        r2,\[r3,15\]
-  20:  fe 09 62 08     086209fe     ldw        r3,\[r4,-2\]
-  24:  00 20 21 08     08212000     lr         r1,\[r2\]
-  28:  14 a0 3f 08     083fa014     lr         r1,\[0x14\]
-  2c:  00 a0 1f 08     081fa000     lr         r0,\[status\]
+[0-9a-f]+ <.text>:
+   0:  1100 0000               ld      r0,\[r1\]
+   4:  1601 0005               ld      r5,\[r6,1\]
+   8:  1600 7013 0000 0000     ld      r19,\[0\]
+                       c: R_ARC_32_ME  foo
+  10:  120a 0204               ld.aw   r4,\[r2,10\]
+  14:  1600 7001 0000 0384     ld      r1,\[0x384\]
+  1c:  130f 0082               ldb     r2,\[r3,15\]
+  20:  14fe 8103               ld[hw]+ r3,\[r4,-2\]
+  24:  212a 0080               lr      r1,\[r2\]
+  28:  216a 0500               lr      r1,\[dmc_code_ram\]
+  2c:  206a 0000               lr      r0,\[status\]