-#as: -EL
-#objdump: -dr -EL
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
Disassembly of section .text:
-00000000 <.text>:
- 0: 00 02 01 10 10010200 st r1,\[r2\]
- 4: 0e 02 01 10 1001020e st r1,\[r2,14\]
- 8: 00 02 41 10 10410200 stb r1,\[r2\]
- c: 0e 82 01 11 1101820e st.a r1,\[r3,14\]
- 10: 02 02 81 11 11810202 stw.a r1,\[r2,2\]
- 14: 00 02 1f 10 101f0200 st r1,\[0x384\]
- 18: 84 03 00 00
- 1c: 00 7e 41 10 10417e00 stb 0,\[r2\]
- 20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\]
- 24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\]
- 28: 9e 02 00 00
- 2c: 00 04 1f 10 101f0400 st r2,\[0\]
- 30: 00 00 00 00
- 30: R_ARC_32 foo
- 34: 02 02 01 14 14010202 st.di r1,\[r2,2\]
- 38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\]
- 3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\]
- 40: 04 7c 06 10 10067c04 st 80,\[r12,4\]
- 44: 50 00 00 00
- 44: R_ARC_32 .text
- 48: 04 7c 06 10 10067c04 st 20,\[r12,4\]
- 4c: 14 00 00 00
- 4c: R_ARC_B26 .text
- 50: 00 02 01 12 12010200 sr r1,\[r2\]
- 54: 0e 82 1f 12 121f820e sr r1,\[0xe\]
+[0-9a-f]+ <.text>:
+ 0: 1a00 0040 st r1,\[r2\]
+ 4: 1a0e 0040 st r1,\[r2,14\]
+ 8: 1a00 0042 stb r1,\[r2\]
+ c: 1b0e 0048 st.aw r1,\[r3,14\]
+ 10: 1a02 004c st[hw]+.aw r1,\[r2,2\]
+ 14: 1e00 7040 0000 0384 st r1,\[0x384\]
+ 1c: 1a00 0003 stb 0,\[r2\]
+ 20: 1af8 8e01 st 56,\[r2,-8\]
+ 24: 1e00 7080 0000 0000 st r2,\[0\]
+ 28: R_ARC_32_ME foo
+ 2c: 1a02 0060 st.di r1,\[r2,2\]
+ 30: 1a03 0068 st.di.aw r1,\[r2,3\]
+ 34: 1a04 006c st[hw]+.di.aw r1,\[r2,4\]
+ 38: 1c04 1f80 0000 0000 st 0,\[r12,4\]
+ 3c: R_ARC_32_ME .text\+0x40
+ 40: 212b 0080 sr r1,\[r2\]
+ 44: 216b 0380 sr r1,\[0xe\]
+ 48: 262b 7040 0000 03e8 sr 0x3e8,\[r1\]
+ 50: 262b 7080 0000 0064 sr 0x64,\[r2\]
+ 58: 212b 0f80 0000 2710 sr r1,\[0x2710\]
+ 60: 266b 7fc0 0000 0064 sr 0x64,\[0x3f\]
+ 68: 26ab 7901 0000 2710 sr 0x2710,\[vbfdw_build\]