-#objdump: -dr
-#name: st/sr
+#as: -mcpu=archs
+#objdump: -dr --show-raw-insn
-# Test the st/sr insn.
-
-.*: +file format elf32-.*arc
+.*: +file format .*arc.*
Disassembly of section .text:
-00000000 10008000 st r0,\[r1\]
-00000004 10030a01 st r5,\[r6,1\]
-00000008 10040fff st r7,\[r8,-1\]
-0000000c 100512ff st r9,\[r10,255\]
-00000010 10061700 st r11,\[r12,-256\]
-00000014 101f2600 st r19,\[0\]
- RELOC: 00000018 R_ARC_32 foo
-0000001c 101f2800 st r20,\[4\]
- RELOC: 00000020 R_ARC_32 foo
-00000024 105f0000 stb r0,\[0\]
-0000002c 109f0000 stw r0,\[0\]
-00000034 111f0000 st.a r0,\[0\]
-0000003c 141f0000 st.di r0,\[0\]
-00000044 15400000 stb.a.di r0,\[r0\]
-00000048 12008000 sr r0,\[r1\]
-0000004c 121f8400 sr r2,\[status\]
-00000050 121f0600 sr r3,\[305419896\]
+
+[0-9a-f]+ <.text>:
+ 0: 1a00 0040 st r1,\[r2\]
+ 4: 1a0e 0040 st r1,\[r2,14\]
+ 8: 1a00 0042 stb r1,\[r2\]
+ c: 1b0e 0048 st.aw r1,\[r3,14\]
+ 10: 1a02 004c st[hw]+.aw r1,\[r2,2\]
+ 14: 1e00 7040 0000 0384 st r1,\[0x384\]
+ 1c: 1a00 0003 stb 0,\[r2\]
+ 20: 1af8 8e01 st 56,\[r2,-8\]
+ 24: 1e00 7080 0000 0000 st r2,\[0\]
+ 28: R_ARC_32_ME foo
+ 2c: 1a02 0060 st.di r1,\[r2,2\]
+ 30: 1a03 0068 st.di.aw r1,\[r2,3\]
+ 34: 1a04 006c st[hw]+.di.aw r1,\[r2,4\]
+ 38: 1c04 1f80 0000 0000 st 0,\[r12,4\]
+ 3c: R_ARC_32_ME .text\+0x40
+ 40: 212b 0080 sr r1,\[r2\]
+ 44: 216b 0380 sr r1,\[0xe\]
+ 48: 262b 7040 0000 03e8 sr 0x3e8,\[r1\]
+ 50: 262b 7080 0000 0064 sr 0x64,\[r2\]
+ 58: 212b 0f80 0000 2710 sr r1,\[0x2710\]
+ 60: 266b 7fc0 0000 0064 sr 0x64,\[0x3f\]
+ 68: 26ab 7901 0000 2710 sr 0x2710,\[vbfdw_build\]