x86: add missing pseudo ops for VPCLMULQDQ ISA extension

[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / vpclmulqdq-intel.d

diff --git a/gas/testsuite/gas/i386/vpclmulqdq-intel.d b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
index fa8ba5b2f12d9f9ca60369577a12461b74b1d184..7713fc06939d183888610834ed655df46ef4f82d 100644 (file)
--- a/gas/testsuite/gas/i386/vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 f4 ab[    ]*vpclmulqdq ymm6,ymm5,ymm4,0xab
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[     ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 b2 e0 0f 00 00 7b[        ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[      ]*[a-f0-9]+:[   ]*c4 e3 6d 44 d9 11[    ]*vpclmulhqhqdq ymm3,ymm2,ymm1
+[      ]*[a-f0-9]+:[   ]*c4 e3 65 44 e2 01[    ]*vpclmulhqlqdq ymm4,ymm3,ymm2
+[      ]*[a-f0-9]+:[   ]*c4 e3 5d 44 eb 10[    ]*vpclmullqhqdq ymm5,ymm4,ymm3
+[      ]*[a-f0-9]+:[   ]*c4 e3 55 44 f4 00[    ]*vpclmullqlqdq ymm6,ymm5,ymm4
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 f4 ab[    ]*vpclmulqdq ymm6,ymm5,ymm4,0xab
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[     ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [      ]*[a-f0-9]+:[   ]*c4 e3 55 44 b2 e0 0f 00 00 7b[        ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b