x86: Correct EVEX vector load/store optimization

[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-optimize-2b.d

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2b.d b/gas/testsuite/gas/i386/x86-64-optimize-2b.d
index 09474a1016c88e61f9d99200a0235a320f3adc05..3eb3a59eaccf4c16092bec1e36b55c863e997d66 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-2b.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2b.d
@@ -124,12 +124,12 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
- +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7d 08 7f 48 08    vmovdqa32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fd 08 7f 48 08    vmovdqa64 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7f 08 7f 48 08    vmovdqu8 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 ff 08 7f 48 08    vmovdqu16 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7e 08 7f 48 08    vmovdqu32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fe 08 7f 48 08    vmovdqu64 %xmm1,0x80\(%rax\)
  +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
  +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
  +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
@@ -148,10 +148,11 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
- +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7d 28 7f 48 04    vmovdqa32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fd 28 7f 48 04    vmovdqa64 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7f 28 7f 48 04    vmovdqu8 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 ff 28 7f 48 04    vmovdqu16 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7e 28 7f 48 04    vmovdqu32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fe 28 7f 48 04    vmovdqu64 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7d 48 6f 10       vmovdqa32 \(%rax\),%zmm2
 #pass