x86: optimize EVEX packed integer logical instructions

[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-optimize-3.d

diff --git a/gas/testsuite/gas/i386/x86-64-optimize-3.d b/gas/testsuite/gas/i386/x86-64-optimize-3.d
index 74336a4fe2297bff68a3427188fb8448c74f7329..fb73b1eab31933795b12a756a9efdd7eb2946ac4 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.d
@@ -43,12 +43,12 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
  +[a-f0-9]+:   c5 fa 6f 50 7f          vmovdqu 0x7f\(%rax\),%xmm2
- +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 f9 7f 88 80 00 00 00         vmovdqa %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fa 7f 88 80 00 00 00         vmovdqu %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7d 08 7f 48 08    vmovdqa32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fd 08 7f 48 08    vmovdqa64 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7f 08 7f 48 08    vmovdqu8 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 ff 08 7f 48 08    vmovdqu16 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7e 08 7f 48 08    vmovdqu32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fe 08 7f 48 08    vmovdqu64 %xmm1,0x80\(%rax\)
  +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
  +[a-f0-9]+:   c5 fd 6f d1             vmovdqa %ymm1,%ymm2
  +[a-f0-9]+:   c5 fe 6f d1             vmovdqu %ymm1,%ymm2
@@ -67,12 +67,12 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
  +[a-f0-9]+:   c5 fe 6f 50 7f          vmovdqu 0x7f\(%rax\),%ymm2
- +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fd 7f 88 80 00 00 00         vmovdqa %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
- +[a-f0-9]+:   c5 fe 7f 88 80 00 00 00         vmovdqu %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7d 28 7f 48 04    vmovdqa32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fd 28 7f 48 04    vmovdqa64 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7f 28 7f 48 04    vmovdqu8 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 ff 28 7f 48 04    vmovdqu16 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 7e 28 7f 48 04    vmovdqu32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+:   62 f1 fe 28 7f 48 04    vmovdqu64 %ymm1,0x80\(%rax\)
  +[a-f0-9]+:   62 b1 7d 08 6f d5       vmovdqa32 %xmm21,%xmm2
  +[a-f0-9]+:   62 b1 fd 08 6f d5       vmovdqa64 %xmm21,%xmm2
  +[a-f0-9]+:   62 b1 7f 08 6f d5       vmovdqu8 %xmm21,%xmm2
@@ -115,4 +115,76 @@ Disassembly of section .text:
  +[a-f0-9]+:   62 f1 ff 89 6f d1       vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
  +[a-f0-9]+:   62 f1 7e 89 6f d1       vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
  +[a-f0-9]+:   62 f1 fe 89 6f d1       vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
+ +[a-f0-9]+:   c5 .*   vpand  %xmm2,%xmm3,%xmm4
+ +[a-f0-9]+:   c4 .*   vpand  %xmm12,%xmm3,%xmm4
+ +[a-f0-9]+:   c5 .*   vpandn %xmm2,%xmm13,%xmm4
+ +[a-f0-9]+:   c5 .*   vpandn %xmm2,%xmm3,%xmm14
+ +[a-f0-9]+:   c5 .*   vpor   %xmm2,%xmm3,%xmm4
+ +[a-f0-9]+:   c4 .*   vpor   %xmm12,%xmm3,%xmm4
+ +[a-f0-9]+:   c5 .*   vpxor  %xmm2,%xmm13,%xmm4
+ +[a-f0-9]+:   c5 .*   vpxor  %xmm2,%xmm3,%xmm14
+ +[a-f0-9]+:   c5 .*   vpand  %ymm2,%ymm3,%ymm4
+ +[a-f0-9]+:   c4 .*   vpand  %ymm12,%ymm3,%ymm4
+ +[a-f0-9]+:   c5 .*   vpandn %ymm2,%ymm13,%ymm4
+ +[a-f0-9]+:   c5 .*   vpandn %ymm2,%ymm3,%ymm14
+ +[a-f0-9]+:   c5 .*   vpor   %ymm2,%ymm3,%ymm4
+ +[a-f0-9]+:   c4 .*   vpor   %ymm12,%ymm3,%ymm4
+ +[a-f0-9]+:   c5 .*   vpxor  %ymm2,%ymm13,%ymm4
+ +[a-f0-9]+:   c5 .*   vpxor  %ymm2,%ymm3,%ymm14
+ +[a-f0-9]+:   c5 .*   vpand  0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpand  0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpandn 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpandn 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpor   0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpor   0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpxor  0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpxor  0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandd 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandnd 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandnq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpord  0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vporq  0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpxord 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpxorq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+:   c5 .*   vpand  0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpand  0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpandn 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpandn 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpor   0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpor   0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpxor  0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   c5 .*   vpxor  0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandd 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandnd 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandnq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpord  0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vporq  0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpxord 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandd %xmm22,%xmm23,%xmm24
+ +[a-f0-9]+:   62 .*   vpandq %ymm22,%ymm3,%ymm4
+ +[a-f0-9]+:   62 .*   vpandnd %ymm2,%ymm23,%ymm4
+ +[a-f0-9]+:   62 .*   vpandnq %xmm2,%xmm3,%xmm24
+ +[a-f0-9]+:   62 .*   vpord  %xmm22,%xmm23,%xmm24
+ +[a-f0-9]+:   62 .*   vporq  %ymm22,%ymm3,%ymm4
+ +[a-f0-9]+:   62 .*   vpxord %ymm2,%ymm23,%ymm4
+ +[a-f0-9]+:   62 .*   vpxorq %xmm2,%xmm3,%xmm24
+ +[a-f0-9]+:   62 .*   vpandd %xmm2,%xmm3,%xmm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vpandq %ymm12,%ymm3,%ymm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vpandnd %ymm2,%ymm13,%ymm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vpandnq %xmm2,%xmm3,%xmm14\{%k5\}
+ +[a-f0-9]+:   62 .*   vpord  %xmm2,%xmm3,%xmm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vporq  %ymm12,%ymm3,%ymm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vpxord %ymm2,%ymm13,%ymm4\{%k5\}
+ +[a-f0-9]+:   62 .*   vpxorq %xmm2,%xmm3,%xmm14\{%k5\}
+ +[a-f0-9]+:   62 .*   vpandd \(%rax\)\{1to8\},%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpandq \(%rax\)\{1to2\},%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandnd \(%rax\)\{1to4\},%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpandnq \(%rax\)\{1to4\},%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vpord  \(%rax\)\{1to8\},%ymm2,%ymm3
+ +[a-f0-9]+:   62 .*   vporq  \(%rax\)\{1to2\},%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpxord \(%rax\)\{1to4\},%xmm2,%xmm3
+ +[a-f0-9]+:   62 .*   vpxorq \(%rax\)\{1to4\},%ymm2,%ymm3
 #pass