Add support for MIPS R6.

[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mips32.s

diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s
index b3fb6fe13bf6d3ae4e21c1dc6ad035369cd16982..35f7d4244889c5446fdb55c769d2089c360322ff 100644 (file)
--- a/gas/testsuite/gas/mips/mips32.s
+++ b/gas/testsuite/gas/mips/mips32.s
@@ -10,45 +10,34 @@ text_label:
 
       clo     $1, $2
       clz     $3, $4
+       .ifndef r6
       madd    $5, $6
       maddu   $7, $8
       msub    $9, $10
       msubu   $11, $12
+       .endif
       mul     $13, $14, $15
       pref    4, ($16)
-      pref    4, 32767($17)
-      pref    4, -32768($18)
+       .ifndef r6
+      pref    4, 2047($17)
+      pref    4, -2048($18)
+       .endif
       ssnop
 
 
-      # unprivileged coprocessor instructions.
-      # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
-
-      bc2f    text_label
-      nop
-      bc2fl   text_label
-      nop
-      bc2t    text_label
-      nop
-      bc2tl   text_label
-      nop
-      # XXX other BCzCond encodings not currently expressable
-      cfc2    $1, $2
-      cop2    0x1234567               # disassembles as c2 ...
-      ctc2    $2, $3
-      mfc2    $3, $4
-      mfc2    $4, $5, 0               # disassembles without sel
-      mfc2    $5, $6, 7
-      mtc2    $6, $7
-      mtc2    $7, $8, 0               # disassembles without sel
-      mtc2    $8, $9, 7
-
-      
       # privileged instructions
 
       cache   5, ($1)
-      cache   5, 32767($2)
-      cache   5, -32768($3)
+       .ifndef r6
+      cache   5, 2047($2)
+      cache   5, -2048($3)
+      .set at
+      cache   5, 32768($4)
+      cache   5, -32769($5)
+      cache   5, 32768
+      cache   5, -32769
+      .set noat
+       .endif
       eret
       tlbp
       tlbr
@@ -56,7 +45,7 @@ text_label:
       tlbwr
       wait
       wait    0                       # disassembles without code
-      wait    0x56789
+      wait    0x345
 
       # For a while break for the mips32 ISA interpreted a single argument
       # as a 20-bit code, placing it in the opcode differently to
@@ -71,7 +60,7 @@ text_label:
       # different.
       sdbbp
       sdbbp   0                       # disassembles without code
-      sdbbp   0x56789
+      sdbbp   0x345
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
       .space  8