/* Native-dependent code for GNU/Linux AArch64.
- Copyright (C) 2011-2018 Free Software Foundation, Inc.
+ Copyright (C) 2011-2019 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "aarch32-linux-nat.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
+#include "nat/aarch64-sve-linux-ptrace.h"
#include "elf/external.h"
#include "elf/common.h"
/* Override the GNU/Linux inferior startup hook. */
void post_startup_inferior (ptid_t) override;
+ /* Override the GNU/Linux post attach hook. */
+ void post_attach (int pid) override;
+
/* These three defer to common nat/ code. */
void low_new_thread (struct lwp_info *lp) override
{ aarch64_linux_new_thread (lp); }
and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
int regno;
for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
- regcache_raw_supply (regcache, regno, ®s[regno - AARCH64_X0_REGNUM]);
+ regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]);
}
}
/* Make sure REGS can hold all registers contents on both aarch64
and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
int regno;
for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
- if (REG_VALID == regcache_register_status (regcache, regno))
- regcache_raw_collect (regcache, regno,
- ®s[regno - AARCH64_X0_REGNUM]);
+ if (REG_VALID == regcache->get_register_status (regno))
+ regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]);
}
ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
and arm. */
gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
perror_with_name (_("Unable to fetch vFP/SIMD registers."));
for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
- regcache_raw_supply (regcache, regno,
- ®s.vregs[regno - AARCH64_V0_REGNUM]);
+ regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]);
- regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, ®s.fpsr);
- regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, ®s.fpcr);
+ regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr);
+ regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr);
}
}
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
perror_with_name (_("Unable to fetch FP/SIMD registers."));
for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
- if (REG_VALID == regcache_register_status (regcache, regno))
- regcache_raw_collect (regcache, regno,
- (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
-
- if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
- regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM,
- (char *) ®s.fpsr);
- if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
- regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM,
- (char *) ®s.fpcr);
+ if (REG_VALID == regcache->get_register_status (regno))
+ regcache->raw_collect
+ (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
+
+ if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
+ regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
+ if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
+ regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
}
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
}
}
+/* Fill GDB's register array with the sve register values
+ from the current thread. */
+
+static void
+fetch_sveregs_from_thread (struct regcache *regcache)
+{
+ std::unique_ptr<gdb_byte[]> base
+ = aarch64_sve_get_sveregs (regcache->ptid ().lwp ());
+ aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ());
+}
+
+/* Store to the current thread the valid sve register
+ values in the GDB's register array. */
+
+static void
+store_sveregs_to_thread (struct regcache *regcache)
+{
+ int ret;
+ struct iovec iovec;
+ int tid = regcache->ptid ().lwp ();
+
+ /* Obtain a dump of SVE registers from ptrace. */
+ std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid);
+
+ /* Overwrite with regcache state. */
+ aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ());
+
+ /* Write back to the kernel. */
+ iovec.iov_base = base.get ();
+ iovec.iov_len = ((struct user_sve_header *) base.get ())->size;
+ ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec);
+
+ if (ret < 0)
+ perror_with_name (_("Unable to store sve registers"));
+}
+
/* Implement the "fetch_registers" target_ops method. */
void
aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
int regno)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
+
if (regno == -1)
{
fetch_gregs_from_thread (regcache);
- fetch_fpregs_from_thread (regcache);
+ if (tdep->has_sve ())
+ fetch_sveregs_from_thread (regcache);
+ else
+ fetch_fpregs_from_thread (regcache);
}
else if (regno < AARCH64_V0_REGNUM)
fetch_gregs_from_thread (regcache);
+ else if (tdep->has_sve ())
+ fetch_sveregs_from_thread (regcache);
else
fetch_fpregs_from_thread (regcache);
}
aarch64_linux_nat_target::store_registers (struct regcache *regcache,
int regno)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
+
if (regno == -1)
{
store_gregs_to_thread (regcache);
- store_fpregs_to_thread (regcache);
+ if (tdep->has_sve ())
+ store_sveregs_to_thread (regcache);
+ else
+ store_fpregs_to_thread (regcache);
}
else if (regno < AARCH64_V0_REGNUM)
store_gregs_to_thread (regcache);
+ else if (tdep->has_sve ())
+ store_sveregs_to_thread (regcache);
else
store_fpregs_to_thread (regcache);
}
new process so that all breakpoints and watchpoints can be
removed together. */
- parent_pid = ptid_get_pid (parent->ptid);
+ parent_pid = parent->ptid.pid ();
parent_state = aarch64_get_debug_reg_state (parent_pid);
child_state = aarch64_get_debug_reg_state (child_pid);
*child_state = *parent_state;
void
aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
{
- low_forget_process (ptid_get_pid (ptid));
- aarch64_linux_get_debug_reg_capacity (ptid_get_pid (ptid));
+ low_forget_process (ptid.pid ());
+ aarch64_linux_get_debug_reg_capacity (ptid.pid ());
linux_nat_target::post_startup_inferior (ptid);
}
+/* Implement the "post_attach" target_ops method. */
+
+void
+aarch64_linux_nat_target::post_attach (int pid)
+{
+ low_forget_process (pid);
+ /* Set the hardware debug register capacity. If
+ aarch64_linux_get_debug_reg_capacity is not called
+ (as it is in aarch64_linux_child_post_startup_inferior) then
+ software watchpoints will be used instead of hardware
+ watchpoints when attaching to a target. */
+ aarch64_linux_get_debug_reg_capacity (pid);
+ linux_nat_target::post_attach (pid);
+}
+
extern struct target_desc *tdesc_arm_with_neon;
/* Implement the "read_description" target_ops method. */
gdb_byte regbuf[VFP_REGS_SIZE];
struct iovec iovec;
- tid = ptid_get_lwp (inferior_ptid);
+ tid = inferior_ptid.lwp ();
iovec.iov_base = regbuf;
iovec.iov_len = VFP_REGS_SIZE;
if (ret == 0)
return tdesc_arm_with_neon;
else
- return aarch64_read_description ();
+ return aarch64_read_description (aarch64_sve_get_vq (tid));
}
/* Convert a native/host siginfo object, into/from the siginfo in the
int len;
const enum target_hw_bp_type type = hw_execute;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
int len = 4;
const enum target_hw_bp_type type = hw_execute;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
{
int ret;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
if (show_debug_regs)
fprintf_unfiltered (gdb_stdlog,
{
int ret;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
if (show_debug_regs)
fprintf_unfiltered (gdb_stdlog,
aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
{
siginfo_t siginfo;
- int i, tid;
+ int i;
struct aarch64_debug_reg_state *state;
if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
return false;
/* Check if the address matches any watched address. */
- state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
{
const unsigned int offset
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