/* Target-dependent code for GNU/Linux AArch64.
- Copyright (C) 2009-2019 Free Software Foundation, Inc.
+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "defs.h"
#include "gdbarch.h"
-#include "arch-utils.h"
#include "glibc-tdep.h"
#include "linux-tdep.h"
#include "aarch64-tdep.h"
#include "symtab.h"
#include "tramp-frame.h"
#include "trad-frame.h"
+#include "target/target.h"
-#include "inferior.h"
#include "regcache.h"
#include "regset.h"
-#include "cli/cli-utils.h"
#include "stap-probe.h"
#include "parser-defs.h"
#include "user-regs.h"
#include "record-full.h"
#include "linux-record.h"
-#include "auxv.h"
-#include "elf/common.h"
/* Signal frame handling.
return magic;
}
+/* Given CACHE, use the trad_frame* functions to restore the FPSIMD
+ registers from a signal frame.
+
+ VREG_NUM is the number of the V register being restored, OFFSET is the
+ address containing the register value, BYTE_ORDER is the endianness and
+ HAS_SVE tells us if we have a valid SVE context or not. */
+
+static void
+aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs,
+ int vreg_num, CORE_ADDR offset,
+ enum bfd_endian byte_order, bool has_sve)
+{
+ /* WARNING: SIMD state is laid out in memory in target-endian format.
+
+ So we have a couple cases to consider:
+
+ 1 - If the target is big endian, then SIMD state is big endian,
+ requiring a byteswap.
+
+ 2 - If the target is little endian, then SIMD state is little endian, so
+ no byteswap is needed. */
+
+ if (byte_order == BFD_ENDIAN_BIG)
+ {
+ gdb_byte buf[V_REGISTER_SIZE];
+
+ if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0)
+ {
+ size_t size = V_REGISTER_SIZE/2;
+
+ /* Read the two halves of the V register in reverse byte order. */
+ CORE_ADDR u64 = extract_unsigned_integer (buf, size,
+ byte_order);
+ CORE_ADDR l64 = extract_unsigned_integer (buf + size, size,
+ byte_order);
+
+ /* Copy the reversed bytes to the buffer. */
+ store_unsigned_integer (buf, size, BFD_ENDIAN_LITTLE, l64);
+ store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64);
+
+ /* Now we can store the correct bytes for the V register. */
+ trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num,
+ {buf, V_REGISTER_SIZE});
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_Q0_REGNUM
+ + vreg_num, {buf, Q_REGISTER_SIZE});
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_D0_REGNUM
+ + vreg_num, {buf, D_REGISTER_SIZE});
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_S0_REGNUM
+ + vreg_num, {buf, S_REGISTER_SIZE});
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_H0_REGNUM
+ + vreg_num, {buf, H_REGISTER_SIZE});
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_B0_REGNUM
+ + vreg_num, {buf, B_REGISTER_SIZE});
+
+ if (has_sve)
+ trad_frame_set_reg_value_bytes (cache,
+ num_regs + AARCH64_SVE_V0_REGNUM
+ + vreg_num, {buf, V_REGISTER_SIZE});
+ }
+ return;
+ }
+
+ /* Little endian, just point at the address containing the register
+ value. */
+ trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num,
+ offset);
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num,
+ offset);
+
+ if (has_sve)
+ trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM
+ + vreg_num, offset);
+
+}
+
/* Implement the "init" method of struct tramp_frame. */
static void
/* If there was no SVE section then set up the V registers. */
if (sve_regs == 0)
- for (int i = 0; i < 32; i++)
- {
- CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET
+ {
+ for (int i = 0; i < 32; i++)
+ {
+ CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET
+ (i * AARCH64_FPSIMD_VREG_SIZE));
- trad_frame_set_reg_addr (this_cache, AARCH64_V0_REGNUM + i, offset);
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_Q0_REGNUM + i, offset);
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_D0_REGNUM + i, offset);
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_S0_REGNUM + i, offset);
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_H0_REGNUM + i, offset);
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_B0_REGNUM + i, offset);
- if (tdep->has_sve ())
- trad_frame_set_reg_addr (this_cache,
- num_regs + AARCH64_SVE_V0_REGNUM + i,
- offset);
- }
+ aarch64_linux_restore_vreg (this_cache, num_regs, i, offset,
+ byte_order, tdep->has_sve ());
+ }
+ }
}
trad_frame_set_id (this_cache, frame_id_build (sp, func));
return 0;
}
- size_t size = bfd_section_size (abfd, sve_section);
+ size_t size = bfd_section_size (sve_section);
/* Check extended state size. */
if (size < SVE_HEADER_SIZE)
size - SVE_HEADER_SIZE);
}
-/* Implement the "regset_from_core_section" gdbarch method. */
+/* Implement the "iterate_over_regset_sections" gdbarch method. */
static void
aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
else
cb (".reg2", AARCH64_LINUX_SIZEOF_FPREGSET, AARCH64_LINUX_SIZEOF_FPREGSET,
&aarch64_linux_fpregset, NULL, cb_data);
+
+
+ if (tdep->has_pauth ())
+ {
+ /* Create this on the fly in order to handle the variable location. */
+ const struct regcache_map_entry pauth_regmap[] =
+ {
+ { 2, AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), 8},
+ { 0 }
+ };
+
+ const struct regset aarch64_linux_pauth_regset =
+ {
+ pauth_regmap, regcache_supply_regset, regcache_collect_regset
+ };
+
+ cb (".reg-aarch-pauth", AARCH64_LINUX_SIZEOF_PAUTH,
+ AARCH64_LINUX_SIZEOF_PAUTH, &aarch64_linux_pauth_regset,
+ "pauth registers", cb_data);
+ }
}
/* Implement the "core_read_description" gdbarch method. */
aarch64_linux_core_read_description (struct gdbarch *gdbarch,
struct target_ops *target, bfd *abfd)
{
- CORE_ADDR aarch64_hwcap = 0;
-
- if (target_auxv_search (target, AT_HWCAP, &aarch64_hwcap) != 1)
- return NULL;
+ CORE_ADDR hwcap = linux_get_hwcap (target);
- return aarch64_read_description (aarch64_linux_core_read_vq (gdbarch, abfd));
+ return aarch64_read_description (aarch64_linux_core_read_vq (gdbarch, abfd),
+ hwcap & AARCH64_HWCAP_PACA);
}
/* Implementation of `gdbarch_stap_is_single_operand', as defined in
return 1;
}
-/* Implement the "get_syscall_number" gdbarch method. */
-
-static LONGEST
-aarch64_linux_get_syscall_number (struct gdbarch *gdbarch,
- thread_info *thread)
-{
- struct regcache *regs = get_thread_regcache (thread);
- enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
-
- /* The content of register x8. */
- gdb_byte buf[X_REGISTER_SIZE];
- /* The result. */
- LONGEST ret;
-
- /* Getting the system call number from the register x8. */
- regs->cooked_read (AARCH64_DWARF_X0 + 8, buf);
-
- ret = extract_signed_integer (buf, X_REGISTER_SIZE, byte_order);
-
- return ret;
-}
-
/* AArch64 process record-replay constructs: syscall, signal etc. */
-struct linux_record_tdep aarch64_linux_record_tdep;
+static linux_record_tdep aarch64_linux_record_tdep;
/* Enum that defines the AArch64 linux specific syscall identifiers used for
process record/replay. */
}
}
+/* Retrieve the syscall number at a ptrace syscall-stop, either on syscall entry
+ or exit. Return -1 upon error. */
+
+static LONGEST
+aarch64_linux_get_syscall_number (struct gdbarch *gdbarch, thread_info *thread)
+{
+ struct regcache *regs = get_thread_regcache (thread);
+ LONGEST ret;
+
+ /* Get the system call number from register x8. */
+ regs->cooked_read (AARCH64_X0_REGNUM + 8, &ret);
+
+ /* On exit from a successful execve, we will be in a new process and all the
+ registers will be cleared - x0 to x30 will be 0, except for a 1 in x7.
+ This function will only ever get called when stopped at the entry or exit
+ of a syscall, so by checking for 0 in x0 (arg0/retval), x1 (arg1), x8
+ (syscall), x29 (FP) and x30 (LR) we can infer:
+ 1) Either inferior is at exit from successful execve.
+ 2) Or inferior is at entry to a call to io_setup with invalid arguments and
+ a corrupted FP and LR.
+ It should be safe enough to assume case 1. */
+ if (ret == 0)
+ {
+ LONGEST x1 = -1, fp = -1, lr = -1;
+ regs->cooked_read (AARCH64_X0_REGNUM + 1, &x1);
+ regs->cooked_read (AARCH64_FP_REGNUM, &fp);
+ regs->cooked_read (AARCH64_LR_REGNUM, &lr);
+ if (x1 == 0 && fp ==0 && lr == 0)
+ return aarch64_sys_execve;
+ }
+
+ return ret;
+}
+
/* Record all registers but PC register for process-record. */
static int
/* Implement the "gcc_target_options" gdbarch method. */
-static char *
+static std::string
aarch64_linux_gcc_target_options (struct gdbarch *gdbarch)
{
/* GCC doesn't know "-m64". */
- return NULL;
+ return {};
}
static void
tdep->lowest_pc = 0x8000;
- linux_init_abi (info, gdbarch);
+ linux_init_abi (info, gdbarch, 1);
set_solib_svr4_fetch_link_map_offsets (gdbarch,
svr4_lp64_fetch_link_map_offsets);
/* Enable TLS support. */
set_gdbarch_fetch_tls_load_module_address (gdbarch,
- svr4_fetch_objfile_link_map);
+ svr4_fetch_objfile_link_map);
/* Shared library handling. */
set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
set_gdbarch_get_syscall_number (gdbarch, aarch64_linux_get_syscall_number);
/* Displaced stepping. */
- set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
+ set_gdbarch_max_insn_length (gdbarch, 4 * AARCH64_DISPLACED_MODIFIED_INSNS);
set_gdbarch_displaced_step_copy_insn (gdbarch,
aarch64_displaced_step_copy_insn);
set_gdbarch_displaced_step_fixup (gdbarch, aarch64_displaced_step_fixup);
- set_gdbarch_displaced_step_location (gdbarch, linux_displaced_step_location);
set_gdbarch_displaced_step_hw_singlestep (gdbarch,
aarch64_displaced_step_hw_singlestep);
set_gdbarch_gcc_target_options (gdbarch, aarch64_linux_gcc_target_options);
}
+void _initialize_aarch64_linux_tdep ();
void
-_initialize_aarch64_linux_tdep (void)
+_initialize_aarch64_linux_tdep ()
{
gdbarch_register_osabi (bfd_arch_aarch64, 0, GDB_OSABI_LINUX,
aarch64_linux_init_abi);
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