/* Common target dependent code for GDB on AArch64 systems.
- Copyright (C) 2009-2019 Free Software Foundation, Inc.
+ Copyright (C) 2009-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "defs.h"
#include "frame.h"
-#include "inferior.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h"
#include "trad-frame.h"
#include "objfiles.h"
#include "dwarf2.h"
-#include "dwarf2-frame.h"
+#include "dwarf2/frame.h"
#include "gdbtypes.h"
#include "prologue-value.h"
#include "target-descriptions.h"
#include "user-regs.h"
-#include "language.h"
-#include "infcall.h"
-#include "ax.h"
#include "ax-gdb.h"
-#include "common/selftest.h"
+#include "gdbsupport/selftest.h"
#include "aarch64-tdep.h"
#include "aarch64-ravenscar-thread.h"
-#include "elf-bfd.h"
-#include "elf/aarch64.h"
-
-#include "common/vec.h"
-
#include "record.h"
#include "record-full.h"
#include "arch/aarch64-insn.h"
+#include "gdbarch.h"
#include "opcode/aarch64.h"
#include <algorithm>
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
- struct cmd_list_element *c, const char *value)
+ struct cmd_list_element *c, const char *value)
{
fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
}
} // namespace
-/* If address signing is enabled, mask off the signature bits from ADDR, using
- the register values in THIS_FRAME. */
+/* If address signing is enabled, mask off the signature bits from the link
+ register, which is passed by value in ADDR, using the register values in
+ THIS_FRAME. */
static CORE_ADDR
-aarch64_frame_unmask_address (struct gdbarch_tdep *tdep,
- struct frame_info *this_frame,
- CORE_ADDR addr)
+aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
+ struct frame_info *this_frame, CORE_ADDR addr)
{
if (tdep->has_pauth ()
&& frame_unwind_register_unsigned (this_frame,
int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
addr = addr & ~cmask;
+
+ /* Record in the frame that the link register required unmasking. */
+ set_frame_previous_pc_masked (this_frame);
}
return addr;
}
+/* Implement the "get_pc_address_flags" gdbarch method. */
+
+static std::string
+aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
+{
+ if (pc != 0 && get_frame_pc_masked (frame))
+ return "PAC";
+
+ return "";
+}
+
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
+
+ /* Whether the stack has been set. This should be true when we notice a SP
+ to FP move or if we are using the SP as the base register for storing
+ data, in case the FP is ommitted. */
+ bool seen_stack_set = false;
+
/* Track X registers and D registers in prologue. */
pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
regs[rd] = pv_add_constant (regs[rn],
-inst.operands[2].imm.value);
}
+
+ /* Did we move SP to FP? */
+ if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM)
+ seen_stack_set = true;
}
else if (inst.opcode->iclass == pcreladdr
&& inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
else if (inst.opcode->op == OP_MOVZ)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
+
+ /* If this shows up before we set the stack, keep going. Otherwise
+ stop the analysis. */
+ if (seen_stack_set)
+ break;
+
regs[inst.operands[0].reg.regno] = pv_unknown ();
}
else if (inst.opcode->iclass == log_shift
{
unsigned rt = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].addr.base_regno;
- int is64
- = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
+ int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
gdb_assert (!inst.operands[1].addr.offset.is_reg);
- stack.store (pv_add_constant (regs[rn],
- inst.operands[1].addr.offset.imm),
- is64 ? 8 : 4, regs[rt]);
+ stack.store
+ (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
+ size, regs[rt]);
+
+ /* Are we storing with SP as a base? */
+ if (rn == AARCH64_SP_REGNUM)
+ seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldstpair_off
|| (inst.opcode->iclass == ldstpair_indexed
unsigned rt2;
unsigned rn = inst.operands[2].addr.base_regno;
int32_t imm = inst.operands[2].addr.offset.imm;
+ int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
rt2 = inst.operands[1].reg.regno;
if (inst.operands[0].type == AARCH64_OPND_Ft)
{
- /* Only bottom 64-bit of each V register (D register) need
- to be preserved. */
- gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
rt1 += AARCH64_X_REGISTER_COUNT;
rt2 += AARCH64_X_REGISTER_COUNT;
}
- stack.store (pv_add_constant (regs[rn], imm), 8,
- regs[rt1]);
- stack.store (pv_add_constant (regs[rn], imm + 8), 8,
- regs[rt2]);
+ stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
+ stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
if (inst.operands[2].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
+ /* Ignore the instruction that allocates stack space and sets
+ the SP. */
+ if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback)
+ seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
|| (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
unsigned int rt = inst.operands[0].reg.regno;
int32_t imm = inst.operands[1].addr.offset.imm;
unsigned int rn = inst.operands[1].addr.base_regno;
- bool is64
- = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
+ int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
if (inst.operands[0].type == AARCH64_OPND_Ft)
- {
- /* Only bottom 64-bit of each V register (D register) need
- to be preserved. */
- gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
- rt += AARCH64_X_REGISTER_COUNT;
- }
+ rt += AARCH64_X_REGISTER_COUNT;
- stack.store (pv_add_constant (regs[rn], imm),
- is64 ? 8 : 4, regs[rt]);
+ stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
if (inst.operands[1].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
+
+ /* Are we storing with SP as a base? */
+ if (rn == AARCH64_SP_REGNUM)
+ seen_stack_set = true;
}
else if (inst.opcode->iclass == testbranch)
{
}
}
+ /* Test handling of movz before setting the frame pointer. */
+ {
+ static const uint32_t insns[] = {
+ 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
+ 0x52800020, /* mov w0, #0x1 */
+ 0x910003fd, /* mov x29, sp */
+ 0x528000a2, /* mov w2, #0x5 */
+ 0x97fffff8, /* bl 6e4 */
+ };
+
+ instruction_reader_test reader (insns);
+
+ trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ /* We should stop at the 4th instruction. */
+ SELF_CHECK (end == (4 - 1) * 4);
+ SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
+ SELF_CHECK (cache.framesize == 16);
+ }
+
+ /* Test handling of movz/stp when using the stack pointer as frame
+ pointer. */
+ {
+ static const uint32_t insns[] = {
+ 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
+ 0x52800020, /* mov w0, #0x1 */
+ 0x290207e0, /* stp w0, w1, [sp, #16] */
+ 0xa9018fe2, /* stp x2, x3, [sp, #24] */
+ 0x528000a2, /* mov w2, #0x5 */
+ 0x97fffff8, /* bl 6e4 */
+ };
+
+ instruction_reader_test reader (insns);
+
+ trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ /* We should stop at the 5th instruction. */
+ SELF_CHECK (end == (5 - 1) * 4);
+ SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
+ SELF_CHECK (cache.framesize == 64);
+ }
+
+ /* Test handling of movz/str when using the stack pointer as frame
+ pointer */
+ {
+ static const uint32_t insns[] = {
+ 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
+ 0x52800020, /* mov w0, #0x1 */
+ 0xb9002be4, /* str w4, [sp, #40] */
+ 0xf9001be5, /* str x5, [sp, #48] */
+ 0x528000a2, /* mov w2, #0x5 */
+ 0x97fffff8, /* bl 6e4 */
+ };
+
+ instruction_reader_test reader (insns);
+
+ trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ /* We should stop at the 5th instruction. */
+ SELF_CHECK (end == (5 - 1) * 4);
+ SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
+ SELF_CHECK (cache.framesize == 64);
+ }
+
+ /* Test handling of movz/stur when using the stack pointer as frame
+ pointer. */
+ {
+ static const uint32_t insns[] = {
+ 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
+ 0x52800020, /* mov w0, #0x1 */
+ 0xb80343e6, /* stur w6, [sp, #52] */
+ 0xf80383e7, /* stur x7, [sp, #56] */
+ 0x528000a2, /* mov w2, #0x5 */
+ 0x97fffff8, /* bl 6e4 */
+ };
+
+ instruction_reader_test reader (insns);
+
+ trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ /* We should stop at the 5th instruction. */
+ SELF_CHECK (end == (5 - 1) * 4);
+ SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
+ SELF_CHECK (cache.framesize == 64);
+ }
+
+ /* Test handling of movz when there is no frame pointer set or no stack
+ pointer used. */
+ {
+ static const uint32_t insns[] = {
+ 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
+ 0x52800020, /* mov w0, #0x1 */
+ 0x528000a2, /* mov w2, #0x5 */
+ 0x97fffff8, /* bl 6e4 */
+ };
+
+ instruction_reader_test reader (insns);
+
+ trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ /* We should stop at the 4th instruction. */
+ SELF_CHECK (end == (4 - 1) * 4);
+ SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
+ SELF_CHECK (cache.framesize == 16);
+ }
+
/* Test a prologue in which there is a return address signing instruction. */
if (tdep->has_pauth ())
{
if (tdep->has_pauth ()
&& trad_frame_value_p (cache->saved_regs,
tdep->pauth_ra_state_regnum))
- lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
+ lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
return frame_unwind_got_constant (this_frame, prev_regnum, lr);
}
identified by the next frame's stack pointer at the time of the
call. The value was already reconstructed into PREV_SP. */
/*
- +----------+ ^
- | saved lr | |
+ +----------+ ^
+ | saved lr | |
+->| saved fp |--+
| | |
| | | <- Previous SP
| +----------+
| | saved lr |
+--| saved fp |<- FP
- | |
- | |<- SP
- +----------+ */
+ | |
+ | |<- SP
+ +----------+ */
if (prev_regnum == AARCH64_SP_REGNUM)
return frame_unwind_got_constant (this_frame, prev_regnum,
cache->prev_sp);
{
case AARCH64_PC_REGNUM:
lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
- lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
+ lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
return frame_unwind_got_constant (this_frame, regnum, lr);
default:
return false;
}
+/* Used for matching BRK instructions for AArch64. */
+static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f;
+static constexpr uint32_t BRK_INSN_BASE = 0xd4200000;
+
+/* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
+
+static bool
+aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
+{
+ const uint32_t insn_len = 4;
+ gdb_byte target_mem[4];
+
+ /* Enable the automatic memory restoration from breakpoints while
+ we read the memory. Otherwise we may find temporary breakpoints, ones
+ inserted by GDB, and flag them as permanent breakpoints. */
+ scoped_restore restore_memory
+ = make_scoped_restore_show_memory_breakpoints (0);
+
+ if (target_read_memory (address, target_mem, insn_len) == 0)
+ {
+ uint32_t insn =
+ (uint32_t) extract_unsigned_integer (target_mem, insn_len,
+ gdbarch_byte_order_for_code (gdbarch));
+
+ /* Check if INSN is a BRK instruction pattern. There are multiple choices
+ of such instructions with different immediate values. Different OS'
+ may use a different variation, but they have the same outcome. */
+ return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE);
+ }
+
+ return false;
+}
+
/* When arguments must be pushed onto the stack, they go on in reverse
order. The code below implements a FILO (stack) to do this. */
aarch64_type_align (gdbarch *gdbarch, struct type *t)
{
t = check_typedef (t);
- if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
+ if (t->code () == TYPE_CODE_ARRAY && t->is_vector ())
{
/* Use the natural alignment for vector types (the same for
scalar type), but the maximum alignment is 128-bit. */
if (type == nullptr)
return -1;
- switch (TYPE_CODE (type))
+ switch (type->code ())
{
case TYPE_CODE_FLT:
if (TYPE_LENGTH (type) > 16)
if (*fundamental_type == nullptr)
*fundamental_type = type;
else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
- || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
+ || type->code () != (*fundamental_type)->code ())
return -1;
return 1;
if (*fundamental_type == nullptr)
*fundamental_type = target_type;
else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
- || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
+ || target_type->code () != (*fundamental_type)->code ())
return -1;
return 2;
case TYPE_CODE_ARRAY:
{
- if (TYPE_VECTOR (type))
+ if (type->is_vector ())
{
if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
return -1;
if (*fundamental_type == nullptr)
*fundamental_type = type;
else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
- || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
+ || type->code () != (*fundamental_type)->code ())
return -1;
return 1;
{
int count = 0;
- for (int i = 0; i < TYPE_NFIELDS (type); i++)
+ for (int i = 0; i < type->num_fields (); i++)
{
/* Ignore any static fields. */
- if (field_is_static (&TYPE_FIELD (type, i)))
+ if (field_is_static (&type->field (i)))
continue;
- struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
+ struct type *member = check_typedef (type->field (i).type ());
int sub_count = aapcs_is_vfp_call_or_return_candidate_1
(member, fundamental_type);
};
/* Pass a value in a sequence of consecutive X registers. The caller
- is responsbile for ensuring sufficient registers are available. */
+ is responsible for ensuring sufficient registers are available. */
static void
pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int len = TYPE_LENGTH (type);
- enum type_code typecode = TYPE_CODE (type);
+ enum type_code typecode = type->code ();
int regnum = AARCH64_X0_REGNUM + info->ngrn;
const bfd_byte *buf = value_contents (arg);
struct aarch64_call_info *info, struct type *arg_type,
struct value *arg)
{
- switch (TYPE_CODE (arg_type))
+ switch (arg_type->code ())
{
case TYPE_CODE_FLT:
return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
}
case TYPE_CODE_ARRAY:
- if (TYPE_VECTOR (arg_type))
+ if (arg_type->is_vector ())
return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
value_contents (arg));
/* fall through. */
case TYPE_CODE_STRUCT:
case TYPE_CODE_UNION:
- for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
+ for (int i = 0; i < arg_type->num_fields (); i++)
{
/* Don't include static fields. */
- if (field_is_static (&TYPE_FIELD (arg_type, i)))
+ if (field_is_static (&arg_type->field (i)))
continue;
struct value *field = value_primitive_field (arg, 0, i, arg_type);
continue;
}
- switch (TYPE_CODE (arg_type))
+ switch (arg_type->code ())
{
case TYPE_CODE_INT:
case TYPE_CODE_BOOL:
if (len < 4)
{
/* Promote to 32 bit integer. */
- if (TYPE_UNSIGNED (arg_type))
+ if (arg_type->is_unsigned ())
arg_type = builtin_type (gdbarch)->builtin_uint32;
else
arg_type = builtin_type (gdbarch)->builtin_int32;
if (tdep->vnv_type == NULL)
{
- /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
+ /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
slice from the non-pseudo vector registers. However NEON V registers
are always vector registers, and need constructing as such. */
const struct builtin_type *bt = builtin_type (gdbarch);
valbuf += len;
}
}
- else if (TYPE_CODE (type) == TYPE_CODE_INT
- || TYPE_CODE (type) == TYPE_CODE_CHAR
- || TYPE_CODE (type) == TYPE_CODE_BOOL
- || TYPE_CODE (type) == TYPE_CODE_PTR
+ else if (type->code () == TYPE_CODE_INT
+ || type->code () == TYPE_CODE_CHAR
+ || type->code () == TYPE_CODE_BOOL
+ || type->code () == TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type)
- || TYPE_CODE (type) == TYPE_CODE_ENUM)
+ || type->code () == TYPE_CODE_ENUM)
{
/* If the type is a plain integer, then the access is
straight-forward. Otherwise we have to play around a bit
else
{
/* For a structure or union the behaviour is as if the value had
- been stored to word-aligned memory and then loaded into
- registers with 64-bit load instruction(s). */
+ been stored to word-aligned memory and then loaded into
+ registers with 64-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = AARCH64_X0_REGNUM;
bfd_byte buf[X_REGISTER_SIZE];
if (TYPE_LENGTH (type) > 16)
{
/* PCS B.6 Aggregates larger than 16 bytes are passed by
- invisible reference. */
+ invisible reference. */
return 1;
}
valbuf += len;
}
}
- else if (TYPE_CODE (type) == TYPE_CODE_INT
- || TYPE_CODE (type) == TYPE_CODE_CHAR
- || TYPE_CODE (type) == TYPE_CODE_BOOL
- || TYPE_CODE (type) == TYPE_CODE_PTR
+ else if (type->code () == TYPE_CODE_INT
+ || type->code () == TYPE_CODE_CHAR
+ || type->code () == TYPE_CODE_BOOL
+ || type->code () == TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type)
- || TYPE_CODE (type) == TYPE_CODE_ENUM)
+ || type->code () == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
{
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
- || TYPE_CODE (valtype) == TYPE_CODE_UNION
- || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
+ if (valtype->code () == TYPE_CODE_STRUCT
+ || valtype->code () == TYPE_CODE_UNION
+ || valtype->code () == TYPE_CODE_ARRAY)
{
if (aarch64_return_in_memory (gdbarch, valtype))
{
{
/* It is true when condition instruction, such as B.CON, TBZ, etc,
is being displaced stepping. */
- int cond = 0;
+ bool cond = false;
- /* PC adjustment offset after displaced stepping. */
+ /* PC adjustment offset after displaced stepping. If 0, then we don't
+ write the PC back, assuming the PC is already the right address. */
int32_t pc_adjust = 0;
};
*/
emit_bcond (dsd->insn_buf, cond, 8);
- dsd->dsc->cond = 1;
+ dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
dsd->insn_count = 1;
}
*/
emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
dsd->insn_count = 1;
- dsd->dsc->cond = 1;
+ dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
}
*/
emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
dsd->insn_count = 1;
- dsd->dsc->cond = 1;
+ dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
}
/* Implement the "displaced_step_copy_insn" gdbarch method. */
-struct displaced_step_closure *
+displaced_step_closure_up
aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
relocated instruction(s) there. */
for (i = 0; i < dsd.insn_count; i++)
{
- if (debug_displaced)
- {
- debug_printf ("displaced: writing insn ");
- debug_printf ("%.8x", dsd.insn_buf[i]);
- debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
- }
+ displaced_debug_printf ("writing insn %.8x at %s",
+ dsd.insn_buf[i],
+ paddress (gdbarch, to + i * 4));
+
write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
(ULONGEST) dsd.insn_buf[i]);
}
dsc = NULL;
}
- return dsc.release ();
+ /* This is a work around for a problem with g++ 4.8. */
+ return displaced_step_closure_up (dsc.release ());
}
/* Implement the "displaced_step_fixup" gdbarch method. */
{
aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
+ ULONGEST pc;
+
+ regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
+
+ displaced_debug_printf ("PC after stepping: %s (was %s).",
+ paddress (gdbarch, pc), paddress (gdbarch, to));
+
if (dsc->cond)
{
- ULONGEST pc;
+ displaced_debug_printf ("[Conditional] pc_adjust before: %d",
+ dsc->pc_adjust);
- regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
if (pc - to == 8)
{
/* Condition is true. */
}
else
gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
+
+ displaced_debug_printf ("[Conditional] pc_adjust after: %d",
+ dsc->pc_adjust);
}
+ displaced_debug_printf ("%s PC by %d",
+ dsc->pc_adjust ? "adjusting" : "not adjusting",
+ dsc->pc_adjust);
+
if (dsc->pc_adjust != 0)
{
- if (debug_displaced)
+ /* Make sure the previous instruction was executed (that is, the PC
+ has changed). If the PC didn't change, then discard the adjustment
+ offset. Otherwise we may skip an instruction before its execution
+ took place. */
+ if ((pc - to) == 0)
{
- debug_printf ("displaced: fixup: set PC to %s:%d\n",
- paddress (gdbarch, from), dsc->pc_adjust);
+ displaced_debug_printf ("PC did not move. Discarding PC adjustment.");
+ dsc->pc_adjust = 0;
}
+
+ displaced_debug_printf ("fixup: set PC to %s:%d",
+ paddress (gdbarch, from), dsc->pc_adjust);
+
regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
from + dsc->pc_adjust);
}
/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
-int
-aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
- struct displaced_step_closure *closure)
+bool
+aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch)
{
- return 1;
+ return true;
}
/* Get the correct target description for the given VQ value.
if (feature_core == nullptr)
return nullptr;
- struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
+ tdesc_arch_data_up tdesc_data = tdesc_data_alloc ();
/* Validate the description provides the mandatory core R registers
and allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
- valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
+ valid_p &= tdesc_numbered_register (feature_core, tdesc_data.get (),
AARCH64_X0_REGNUM + i,
aarch64_r_register_names[i]);
/* Validate the description provides the mandatory V registers
and allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
- valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
+ valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data.get (),
AARCH64_V0_REGNUM + i,
aarch64_v_register_names[i]);
/* Validate the description provides the mandatory SVE registers
and allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
- valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
+ valid_p &= tdesc_numbered_register (feature_sve, tdesc_data.get (),
AARCH64_SVE_Z0_REGNUM + i,
aarch64_sve_register_names[i]);
/* Validate the descriptor provides the mandatory PAUTH registers and
allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
- valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
+ valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data.get (),
first_pauth_regnum + i,
aarch64_pauth_register_names[i]);
}
if (!valid_p)
- {
- tdesc_data_cleanup (tdesc_data);
- return nullptr;
- }
+ return nullptr;
/* AArch64 code is always little-endian. */
info.byte_order_for_code = BFD_ENDIAN_LITTLE;
/* Hook in the ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
- info.tdesc_data = tdesc_data;
+ info.tdesc_data = tdesc_data.get ();
gdbarch_init_osabi (info, gdbarch);
dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
aarch64_execute_dwarf_cfa_vendor_op);
+ /* Permanent/Program breakpoint handling. */
+ set_gdbarch_program_breakpoint_here_p (gdbarch,
+ aarch64_program_breakpoint_here_p);
+
/* Add some default predicates. */
frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
dwarf2_append_unwinders (gdbarch);
set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
- tdesc_use_registers (gdbarch, tdesc, tdesc_data);
+ set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
+
+ tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
/* Add standard register aliases. */
for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
}
#endif
+void _initialize_aarch64_tdep ();
void
-_initialize_aarch64_tdep (void)
+_initialize_aarch64_tdep ()
{
gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
aarch64_dump_tdep);
/* AArch64 process record-replay related structures, defines etc. */
#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
- do \
- { \
- unsigned int reg_len = LENGTH; \
- if (reg_len) \
- { \
- REGS = XNEWVEC (uint32_t, reg_len); \
- memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
- } \
- } \
- while (0)
+ do \
+ { \
+ unsigned int reg_len = LENGTH; \
+ if (reg_len) \
+ { \
+ REGS = XNEWVEC (uint32_t, reg_len); \
+ memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
+ } \
+ } \
+ while (0)
#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
- do \
- { \
- unsigned int mem_len = LENGTH; \
- if (mem_len) \
- { \
- MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
- memcpy(&MEMS->len, &RECORD_BUF[0], \
- sizeof(struct aarch64_mem_r) * LENGTH); \
- } \
- } \
- while (0)
+ do \
+ { \
+ unsigned int mem_len = LENGTH; \
+ if (mem_len) \
+ { \
+ MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
+ memcpy(&MEMS->len, &RECORD_BUF[0], \
+ sizeof(struct aarch64_mem_r) * LENGTH); \
+ } \
+ } \
+ while (0)
/* AArch64 record/replay structures and enumerations. */
}
else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
{
- /* CConditional select. */
+ /* Conditional select. */
/* Data-processing (2 source). */
/* Data-processing (1 source). */
record_buf[0] = reg_rd;
uint8_t sindex, scale, selem, esize, replicate = 0;
scale = opcode_bits >> 2;
selem = ((opcode_bits & 0x02) |
- bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
+ bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
switch (scale)
- {
- case 1:
- if (size_bits & 0x01)
- return AARCH64_RECORD_UNKNOWN;
- break;
- case 2:
- if ((size_bits >> 1) & 0x01)
- return AARCH64_RECORD_UNKNOWN;
- if (size_bits & 0x01)
- {
- if (!((opcode_bits >> 1) & 0x01))
- scale = 3;
- else
- return AARCH64_RECORD_UNKNOWN;
- }
- break;
- case 3:
- if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
- {
- scale = size_bits;
- replicate = 1;
- break;
- }
- else
- return AARCH64_RECORD_UNKNOWN;
- default:
- break;
- }
+ {
+ case 1:
+ if (size_bits & 0x01)
+ return AARCH64_RECORD_UNKNOWN;
+ break;
+ case 2:
+ if ((size_bits >> 1) & 0x01)
+ return AARCH64_RECORD_UNKNOWN;
+ if (size_bits & 0x01)
+ {
+ if (!((opcode_bits >> 1) & 0x01))
+ scale = 3;
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ }
+ break;
+ case 3:
+ if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
+ {
+ scale = size_bits;
+ replicate = 1;
+ break;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ default:
+ break;
+ }
esize = 8 << scale;
if (replicate)
- for (sindex = 0; sindex < selem; sindex++)
- {
- record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
- reg_rt = (reg_rt + 1) % 32;
- }
+ for (sindex = 0; sindex < selem; sindex++)
+ {
+ record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
+ reg_rt = (reg_rt + 1) % 32;
+ }
else
- {
- for (sindex = 0; sindex < selem; sindex++)
+ {
+ for (sindex = 0; sindex < selem; sindex++)
{
if (bit (aarch64_insn_r->aarch64_insn, 22))
record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
addr_offset = addr_offset + (esize / 8);
reg_rt = (reg_rt + 1) % 32;
}
- }
+ }
}
/* Load/store multiple structure. */
else
esize = 8 << size_bits;
if (bit (aarch64_insn_r->aarch64_insn, 30))
- elements = 128 / esize;
+ elements = 128 / esize;
else
- elements = 64 / esize;
+ elements = 64 / esize;
switch (opcode_bits)
- {
- /*LD/ST4 (4 Registers). */
- case 0:
- rpt = 1;
- selem = 4;
- break;
- /*LD/ST1 (4 Registers). */
- case 2:
- rpt = 4;
- selem = 1;
- break;
- /*LD/ST3 (3 Registers). */
- case 4:
- rpt = 1;
- selem = 3;
- break;
- /*LD/ST1 (3 Registers). */
- case 6:
- rpt = 3;
- selem = 1;
- break;
- /*LD/ST1 (1 Register). */
- case 7:
- rpt = 1;
- selem = 1;
- break;
- /*LD/ST2 (2 Registers). */
- case 8:
- rpt = 1;
- selem = 2;
- break;
- /*LD/ST1 (2 Registers). */
- case 10:
- rpt = 2;
- selem = 1;
- break;
- default:
- return AARCH64_RECORD_UNSUPPORTED;
- break;
- }
+ {
+ /*LD/ST4 (4 Registers). */
+ case 0:
+ rpt = 1;
+ selem = 4;
+ break;
+ /*LD/ST1 (4 Registers). */
+ case 2:
+ rpt = 4;
+ selem = 1;
+ break;
+ /*LD/ST3 (3 Registers). */
+ case 4:
+ rpt = 1;
+ selem = 3;
+ break;
+ /*LD/ST1 (3 Registers). */
+ case 6:
+ rpt = 3;
+ selem = 1;
+ break;
+ /*LD/ST1 (1 Register). */
+ case 7:
+ rpt = 1;
+ selem = 1;
+ break;
+ /*LD/ST2 (2 Registers). */
+ case 8:
+ rpt = 1;
+ selem = 2;
+ break;
+ /*LD/ST1 (2 Registers). */
+ case 10:
+ rpt = 2;
+ selem = 1;
+ break;
+ default:
+ return AARCH64_RECORD_UNSUPPORTED;
+ break;
+ }
for (rindex = 0; rindex < rpt; rindex++)
- for (eindex = 0; eindex < elements; eindex++)
- {
- uint8_t reg_tt, sindex;
- reg_tt = (reg_rt + rindex) % 32;
- for (sindex = 0; sindex < selem; sindex++)
- {
- if (bit (aarch64_insn_r->aarch64_insn, 22))
- record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
- else
- {
- record_buf_mem[mem_index++] = esize / 8;
- record_buf_mem[mem_index++] = address + addr_offset;
- }
- addr_offset = addr_offset + (esize / 8);
- reg_tt = (reg_tt + 1) % 32;
- }
- }
+ for (eindex = 0; eindex < elements; eindex++)
+ {
+ uint8_t reg_tt, sindex;
+ reg_tt = (reg_rt + rindex) % 32;
+ for (sindex = 0; sindex < selem; sindex++)
+ {
+ if (bit (aarch64_insn_r->aarch64_insn, 22))
+ record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
+ else
+ {
+ record_buf_mem[mem_index++] = esize / 8;
+ record_buf_mem[mem_index++] = address + addr_offset;
+ }
+ addr_offset = addr_offset + (esize / 8);
+ reg_tt = (reg_tt + 1) % 32;
+ }
+ }
}
if (bit (aarch64_insn_r->aarch64_insn, 23))
aarch64_insn_r->reg_rec_count = reg_index;
aarch64_insn_r->mem_rec_count = mem_index / 2;
MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
- record_buf_mem);
+ record_buf_mem);
REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
- record_buf);
+ record_buf);
return AARCH64_RECORD_SUCCESS;
}
if (record_debug)
debug_printf ("Process record: load register (literal)\n");
if (vector_flag)
- record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
else
- record_buf[0] = reg_rt;
+ record_buf[0] = reg_rt;
aarch64_insn_r->reg_rec_count = 1;
}
/* All types of load/store pair instructions decoding. */
debug_printf ("Process record: load/store pair\n");
if (ld_flag)
- {
- if (vector_flag)
- {
- record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
- record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
- }
- else
- {
- record_buf[0] = reg_rt;
- record_buf[1] = reg_rt2;
- }
- aarch64_insn_r->reg_rec_count = 2;
- }
+ {
+ if (vector_flag)
+ {
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
+ }
+ else
+ {
+ record_buf[0] = reg_rt;
+ record_buf[1] = reg_rt2;
+ }
+ aarch64_insn_r->reg_rec_count = 2;
+ }
else
- {
- uint16_t imm7_off;
- imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
- if (!vector_flag)
- size_bits = size_bits >> 1;
- datasize = 8 << (2 + size_bits);
- offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
- offset = offset << (2 + size_bits);
- regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
- &address);
- if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
- {
- if (imm7_off & 0x40)
- address = address - offset;
- else
- address = address + offset;
- }
-
- record_buf_mem[0] = datasize / 8;
- record_buf_mem[1] = address;
- record_buf_mem[2] = datasize / 8;
- record_buf_mem[3] = address + (datasize / 8);
- aarch64_insn_r->mem_rec_count = 2;
- }
+ {
+ uint16_t imm7_off;
+ imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
+ if (!vector_flag)
+ size_bits = size_bits >> 1;
+ datasize = 8 << (2 + size_bits);
+ offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
+ offset = offset << (2 + size_bits);
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
+ {
+ if (imm7_off & 0x40)
+ address = address - offset;
+ else
+ address = address + offset;
+ }
+
+ record_buf_mem[0] = datasize / 8;
+ record_buf_mem[1] = address;
+ record_buf_mem[2] = datasize / 8;
+ record_buf_mem[3] = address + (datasize / 8);
+ aarch64_insn_r->mem_rec_count = 2;
+ }
if (bit (aarch64_insn_r->aarch64_insn, 23))
- record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
+ record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
}
/* Load/store register (unsigned immediate) instructions. */
else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
}
if (!ld_flag)
- {
- offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
- datasize = 8 << size_bits;
- regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
- &address);
- offset = offset << size_bits;
- address = address + offset;
-
- record_buf_mem[0] = datasize >> 3;
- record_buf_mem[1] = address;
- aarch64_insn_r->mem_rec_count = 1;
- }
+ {
+ offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ offset = offset << size_bits;
+ address = address + offset;
+
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
else
- {
- if (vector_flag)
- record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
- else
- record_buf[0] = reg_rt;
- aarch64_insn_r->reg_rec_count = 1;
- }
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
}
/* Load/store register (register offset) instructions. */
else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
debug_printf ("Process record: load/store (register offset)\n");
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
- if (opc & 0x01)
- ld_flag = 0x01;
- else
- ld_flag = 0x0;
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
else
- if (size_bits != 0x03)
- ld_flag = 0x01;
- else
- return AARCH64_RECORD_UNKNOWN;
+ if (size_bits != 0x03)
+ ld_flag = 0x01;
+ else
+ return AARCH64_RECORD_UNKNOWN;
if (!ld_flag)
- {
- ULONGEST reg_rm_val;
-
- regcache_raw_read_unsigned (aarch64_insn_r->regcache,
- bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
- if (bit (aarch64_insn_r->aarch64_insn, 12))
- offset = reg_rm_val << size_bits;
- else
- offset = reg_rm_val;
- datasize = 8 << size_bits;
- regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
- &address);
- address = address + offset;
- record_buf_mem[0] = datasize >> 3;
- record_buf_mem[1] = address;
- aarch64_insn_r->mem_rec_count = 1;
- }
+ {
+ ULONGEST reg_rm_val;
+
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache,
+ bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
+ if (bit (aarch64_insn_r->aarch64_insn, 12))
+ offset = reg_rm_val << size_bits;
+ else
+ offset = reg_rm_val;
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ address = address + offset;
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
else
- {
- if (vector_flag)
- record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
- else
- record_buf[0] = reg_rt;
- aarch64_insn_r->reg_rec_count = 1;
- }
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
}
/* Load/store register (immediate and unprivileged) instructions. */
else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
}
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
- if (opc & 0x01)
- ld_flag = 0x01;
- else
- ld_flag = 0x0;
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
else
- if (size_bits != 0x03)
- ld_flag = 0x01;
- else
- return AARCH64_RECORD_UNKNOWN;
+ if (size_bits != 0x03)
+ ld_flag = 0x01;
+ else
+ return AARCH64_RECORD_UNKNOWN;
if (!ld_flag)
- {
- uint16_t imm9_off;
- imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
- offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
- datasize = 8 << size_bits;
- regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
- &address);
- if (insn_bits10_11 != 0x01)
- {
- if (imm9_off & 0x0100)
- address = address - offset;
- else
- address = address + offset;
- }
- record_buf_mem[0] = datasize >> 3;
- record_buf_mem[1] = address;
- aarch64_insn_r->mem_rec_count = 1;
- }
+ {
+ uint16_t imm9_off;
+ imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
+ offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ if (insn_bits10_11 != 0x01)
+ {
+ if (imm9_off & 0x0100)
+ address = address - offset;
+ else
+ address = address + offset;
+ }
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
else
- {
- if (vector_flag)
- record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
- else
- record_buf[0] = reg_rt;
- aarch64_insn_r->reg_rec_count = 1;
- }
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
- record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
+ record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
}
/* Advanced SIMD load/store instructions. */
else
return aarch64_record_asimd_load_store (aarch64_insn_r);
MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
- record_buf_mem);
+ record_buf_mem);
REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
- record_buf);
+ record_buf);
return AARCH64_RECORD_SUCCESS;
}
record_buf[0] = AARCH64_CPSR_REGNUM;
}
/* Floating point - data processing (2-source) and
- conditional select instructions. */
+ conditional select instructions. */
else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
{
if (record_debug)
}
else
return AARCH64_RECORD_UNKNOWN;
- }
+ }
else
return AARCH64_RECORD_UNKNOWN;
- }
+ }
else
return AARCH64_RECORD_UNKNOWN;
}
projects / deliverable / binutils-gdb.git / blobdiff