/* Common target dependent code for GDB on AArch64 systems.
- Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ Copyright (C) 2009-2018 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "dis-asm.h"
#include "regcache.h"
#include "reggroups.h"
-#include "doublest.h"
#include "value.h"
#include "arch-utils.h"
#include "osabi.h"
#include "record.h"
#include "record-full.h"
-
-#include "features/aarch64.c"
-
#include "arch/aarch64-insn.h"
#include "opcode/aarch64.h"
#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
+#define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
+
+/* All possible aarch64 target descriptors. */
+struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
/* The standard register names, and all the valid aliases for them. */
static const struct
"fpcr"
};
+/* The SVE 'Z' and 'P' registers. */
+static const char *const aarch64_sve_register_names[] =
+{
+ /* These registers must appear in consecutive RAW register number
+ order and they must begin with AARCH64_SVE_Z0_REGNUM! */
+ "z0", "z1", "z2", "z3",
+ "z4", "z5", "z6", "z7",
+ "z8", "z9", "z10", "z11",
+ "z12", "z13", "z14", "z15",
+ "z16", "z17", "z18", "z19",
+ "z20", "z21", "z22", "z23",
+ "z24", "z25", "z26", "z27",
+ "z28", "z29", "z30", "z31",
+ "fpsr", "fpcr",
+ "p0", "p1", "p2", "p3",
+ "p4", "p5", "p6", "p7",
+ "p8", "p9", "p10", "p11",
+ "p12", "p13", "p14", "p15",
+ "ffr", "vg"
+};
+
/* AArch64 prologue cache structure. */
struct aarch64_prologue_cache
{
fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
}
+namespace {
+
/* Abstract instruction reader. */
class abstract_instruction_reader
{
public:
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
+ override
{
- return read_memory_unsigned_integer (memaddr, len, byte_order);
+ return read_code_unsigned_integer (memaddr, len, byte_order);
}
};
+} // namespace
+
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
int i;
/* Track X registers and D registers in prologue. */
pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
- struct pv_area *stack;
- struct cleanup *back_to;
for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
regs[i] = pv_register (i, 0);
- stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
- back_to = make_cleanup_free_pv_area (stack);
+ pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
for (; start < limit; start += 4)
{
insn = reader.read (start, 4, byte_order_for_code);
- if (aarch64_decode_insn (insn, &inst, 1) != 0)
+ if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
break;
if (inst.opcode->iclass == addsub_imm
gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
gdb_assert (!inst.operands[1].addr.offset.is_reg);
- pv_area_store (stack, pv_add_constant (regs[rn],
- inst.operands[1].addr.offset.imm),
- is64 ? 8 : 4, regs[rt]);
+ stack.store (pv_add_constant (regs[rn],
+ inst.operands[1].addr.offset.imm),
+ is64 ? 8 : 4, regs[rt]);
}
else if ((inst.opcode->iclass == ldstpair_off
|| (inst.opcode->iclass == ldstpair_indexed
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
further prologue analysis. */
- if (pv_area_store_would_trash (stack,
- pv_add_constant (regs[rn], imm)))
+ if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
break;
- if (pv_area_store_would_trash (stack,
- pv_add_constant (regs[rn], imm + 8)))
+ if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
break;
rt1 = inst.operands[0].reg.regno;
rt2 += AARCH64_X_REGISTER_COUNT;
}
- pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
- regs[rt1]);
- pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
- regs[rt2]);
+ stack.store (pv_add_constant (regs[rn], imm), 8,
+ regs[rt1]);
+ stack.store (pv_add_constant (regs[rn], imm + 8), 8,
+ regs[rt2]);
if (inst.operands[2].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
}
+ else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
+ || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
+ && (inst.opcode->op == OP_STR_POS
+ || inst.opcode->op == OP_STRF_POS)))
+ && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
+ && strcmp ("str", inst.opcode->name) == 0)
+ {
+ /* STR (immediate) */
+ unsigned int rt = inst.operands[0].reg.regno;
+ int32_t imm = inst.operands[1].addr.offset.imm;
+ unsigned int rn = inst.operands[1].addr.base_regno;
+ bool is64
+ = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
+ gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
+ || inst.operands[0].type == AARCH64_OPND_Ft);
+
+ if (inst.operands[0].type == AARCH64_OPND_Ft)
+ {
+ /* Only bottom 64-bit of each V register (D register) need
+ to be preserved. */
+ gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
+ rt += AARCH64_X_REGISTER_COUNT;
+ }
+
+ stack.store (pv_add_constant (regs[rn], imm),
+ is64 ? 8 : 4, regs[rt]);
+ if (inst.operands[1].addr.writeback)
+ regs[rn] = pv_add_constant (regs[rn], imm);
+ }
else if (inst.opcode->iclass == testbranch)
{
/* Stop analysis on branch. */
}
if (cache == NULL)
- {
- do_cleanups (back_to);
- return start;
- }
+ return start;
if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
{
{
CORE_ADDR offset;
- if (pv_area_find_reg (stack, gdbarch, i, &offset))
+ if (stack.find_reg (gdbarch, i, &offset))
cache->saved_regs[i].addr = offset;
}
int regnum = gdbarch_num_regs (gdbarch);
CORE_ADDR offset;
- if (pv_area_find_reg (stack, gdbarch, i + AARCH64_X_REGISTER_COUNT,
- &offset))
+ if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
+ &offset))
cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
}
- do_cleanups (back_to);
return start;
}
{}
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
+ override
{
SELF_CHECK (len == 4);
SELF_CHECK (memaddr % 4 == 0);
== -1);
}
}
+
+ /* Test a prologue in which STR is used and frame pointer is not
+ used. */
+ {
+ struct aarch64_prologue_cache cache;
+ cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
+
+ static const uint32_t insns[] = {
+ 0xf81d0ff3, /* str x19, [sp, #-48]! */
+ 0xb9002fe0, /* str w0, [sp, #44] */
+ 0xf90013e1, /* str x1, [sp, #32]*/
+ 0xfd000fe0, /* str d0, [sp, #24] */
+ 0xaa0203f3, /* mov x19, x2 */
+ 0xf94013e0, /* ldr x0, [sp, #32] */
+ };
+ instruction_reader_test reader (insns);
+
+ CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
+
+ SELF_CHECK (end == 4 * 5);
+
+ SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
+ SELF_CHECK (cache.framesize == 48);
+
+ for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
+ {
+ if (i == 1)
+ SELF_CHECK (cache.saved_regs[i].addr == -16);
+ else if (i == 19)
+ SELF_CHECK (cache.saved_regs[i].addr == -48);
+ else
+ SELF_CHECK (cache.saved_regs[i].addr == -1);
+ }
+
+ for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
+ {
+ int regnum = gdbarch_num_regs (gdbarch);
+
+ if (i == 0)
+ SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
+ == -24);
+ else
+ SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
+ == -1);
+ }
+ }
}
} // namespace selftests
#endif /* GDB_SELF_TEST */
case TYPE_CODE_RANGE:
case TYPE_CODE_BITSTRING:
case TYPE_CODE_REF:
+ case TYPE_CODE_RVALUE_REF:
case TYPE_CODE_CHAR:
case TYPE_CODE_BOOL:
return TYPE_LENGTH (t);
/* PCS C.1, the argument is allocated to the least significant
bits of V register. */
memcpy (reg, buf, len);
- regcache_cooked_write (regcache, regnum, reg);
+ regcache->cooked_write (regnum, reg);
if (aarch64_debug)
{
return tdep->vnb_type;
}
+/* Return the type for an AdvSISD V register. */
+
+static struct type *
+aarch64_vnv_type (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (tdep->vnv_type == NULL)
+ {
+ struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
+ TYPE_CODE_UNION);
+
+ append_composite_type_field (t, "d", aarch64_vnd_type (gdbarch));
+ append_composite_type_field (t, "s", aarch64_vns_type (gdbarch));
+ append_composite_type_field (t, "h", aarch64_vnh_type (gdbarch));
+ append_composite_type_field (t, "b", aarch64_vnb_type (gdbarch));
+ append_composite_type_field (t, "q", aarch64_vnq_type (gdbarch));
+
+ tdep->vnv_type = t;
+ }
+
+ return tdep->vnv_type;
+}
+
/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
static int
if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
+ if (reg == AARCH64_DWARF_SVE_VG)
+ return AARCH64_SVE_VG_REGNUM;
+
+ if (reg == AARCH64_DWARF_SVE_FFR)
+ return AARCH64_SVE_FFR_REGNUM;
+
+ if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
+ return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
+
+ if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
+ return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
+
return -1;
}
-\f
/* Implement the "print_insn" gdbarch method. */
aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
{
info->symbols = NULL;
- return print_insn_aarch64 (memaddr, info);
+ return default_print_insn (memaddr, info);
}
/* AArch64 BRK software debug mode instruction.
aarch64_extract_return_value (struct type *type, struct regcache *regs,
gdb_byte *valbuf)
{
- struct gdbarch *gdbarch = get_regcache_arch (regs);
+ struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
bfd_byte buf[V_REGISTER_SIZE];
int len = TYPE_LENGTH (type);
- regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
+ regs->cooked_read (AARCH64_V0_REGNUM, buf);
memcpy (valbuf, buf, len);
}
else if (TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
/* If the the type is a plain integer, then the access is
struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
int len = TYPE_LENGTH (target_type);
- regcache_cooked_read (regs, regno, buf);
+ regs->cooked_read (regno, buf);
memcpy (valbuf, buf, len);
valbuf += len;
- regcache_cooked_read (regs, regno + 1, buf);
+ regs->cooked_read (regno + 1, buf);
memcpy (valbuf, buf, len);
valbuf += len;
}
i + 1,
gdbarch_register_name (gdbarch, regno));
}
- regcache_cooked_read (regs, regno, buf);
+ regs->cooked_read (regno, buf);
memcpy (valbuf, buf, len);
valbuf += len;
/* Short vector is returned in V register. */
gdb_byte buf[V_REGISTER_SIZE];
- regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
+ regs->cooked_read (AARCH64_V0_REGNUM, buf);
memcpy (valbuf, buf, TYPE_LENGTH (type));
}
else
while (len > 0)
{
- regcache_cooked_read (regs, regno++, buf);
+ regs->cooked_read (regno++, buf);
memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
aarch64_store_return_value (struct type *type, struct regcache *regs,
const gdb_byte *valbuf)
{
- struct gdbarch *gdbarch = get_regcache_arch (regs);
+ struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
int len = TYPE_LENGTH (type);
memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
- regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
+ regs->cooked_write (AARCH64_V0_REGNUM, buf);
}
else if (TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
LONGEST val = unpack_long (type, valbuf);
store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
- regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf);
+ regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
}
else
{
while (len > 0)
{
- regcache_cooked_write (regs, regno++, valbuf);
+ regs->cooked_write (regno++, valbuf);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
for (i = 0; i < elements; i++)
{
int regno = AARCH64_V0_REGNUM + i;
- bfd_byte tmpbuf[MAX_REGISTER_SIZE];
+ bfd_byte tmpbuf[V_REGISTER_SIZE];
if (aarch64_debug)
{
}
memcpy (tmpbuf, valbuf, len);
- regcache_cooked_write (regs, regno, tmpbuf);
+ regs->cooked_write (regno, tmpbuf);
valbuf += len;
}
}
gdb_byte buf[V_REGISTER_SIZE];
memcpy (buf, valbuf, TYPE_LENGTH (type));
- regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
+ regs->cooked_write (AARCH64_V0_REGNUM, buf);
}
else
{
{
memcpy (tmpbuf, valbuf,
len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
- regcache_cooked_write (regs, regno++, tmpbuf);
+ regs->cooked_write (regno++, tmpbuf);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
static const char *
aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
static const char *const q_name[] =
{
"q0", "q1", "q2", "q3",
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
return b_name[regnum - AARCH64_B0_REGNUM];
+ if (tdep->has_sve ())
+ {
+ static const char *const sve_v_name[] =
+ {
+ "v0", "v1", "v2", "v3",
+ "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11",
+ "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19",
+ "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27",
+ "v28", "v29", "v30", "v31",
+ };
+
+ if (regnum >= AARCH64_SVE_V0_REGNUM
+ && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
+ return sve_v_name[regnum - AARCH64_SVE_V0_REGNUM];
+ }
+
internal_error (__FILE__, __LINE__,
_("aarch64_pseudo_register_name: bad register number %d"),
regnum);
static struct type *
aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
return aarch64_vnb_type (gdbarch);
+ if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
+ && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
+ return aarch64_vnv_type (gdbarch);
+
internal_error (__FILE__, __LINE__,
_("aarch64_pseudo_register_type: bad register number %d"),
regnum);
aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
return group == all_reggroup || group == vector_reggroup;
else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
return group == all_reggroup || group == vector_reggroup;
+ else if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
+ && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
+ return group == all_reggroup || group == vector_reggroup;
return group == all_reggroup;
}
+/* Helper for aarch64_pseudo_read_value. */
+
+static struct value *
+aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
+ readable_regcache *regcache, int regnum_offset,
+ int regsize, struct value *result_value)
+{
+ unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
+
+ /* Enough space for a full vector register. */
+ gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
+ gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
+
+ if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
+ mark_value_bytes_unavailable (result_value, 0,
+ TYPE_LENGTH (value_type (result_value)));
+ else
+ memcpy (value_contents_raw (result_value), reg_buf, regsize);
+
+ return result_value;
+ }
+
/* Implement the "pseudo_register_read_value" gdbarch method. */
static struct value *
-aarch64_pseudo_read_value (struct gdbarch *gdbarch,
- struct regcache *regcache,
+aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
int regnum)
{
- gdb_byte reg_buf[MAX_REGISTER_SIZE];
- struct value *result_value;
- gdb_byte *buf;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct value *result_value = allocate_value (register_type (gdbarch, regnum));
- result_value = allocate_value (register_type (gdbarch, regnum));
VALUE_LVAL (result_value) = lval_register;
VALUE_REGNUM (result_value) = regnum;
- buf = value_contents_raw (result_value);
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
- {
- enum register_status status;
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
- status = regcache_raw_read (regcache, v_regnum, reg_buf);
- if (status != REG_VALID)
- mark_value_bytes_unavailable (result_value, 0,
- TYPE_LENGTH (value_type (result_value)));
- else
- memcpy (buf, reg_buf, Q_REGISTER_SIZE);
- return result_value;
- }
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_Q0_REGNUM,
+ Q_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
- {
- enum register_status status;
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
- status = regcache_raw_read (regcache, v_regnum, reg_buf);
- if (status != REG_VALID)
- mark_value_bytes_unavailable (result_value, 0,
- TYPE_LENGTH (value_type (result_value)));
- else
- memcpy (buf, reg_buf, D_REGISTER_SIZE);
- return result_value;
- }
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_D0_REGNUM,
+ D_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
- {
- enum register_status status;
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
- status = regcache_raw_read (regcache, v_regnum, reg_buf);
- if (status != REG_VALID)
- mark_value_bytes_unavailable (result_value, 0,
- TYPE_LENGTH (value_type (result_value)));
- else
- memcpy (buf, reg_buf, S_REGISTER_SIZE);
- return result_value;
- }
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_S0_REGNUM,
+ S_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
- {
- enum register_status status;
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
- status = regcache_raw_read (regcache, v_regnum, reg_buf);
- if (status != REG_VALID)
- mark_value_bytes_unavailable (result_value, 0,
- TYPE_LENGTH (value_type (result_value)));
- else
- memcpy (buf, reg_buf, H_REGISTER_SIZE);
- return result_value;
- }
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_H0_REGNUM,
+ H_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
- {
- enum register_status status;
- unsigned v_regnum;
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_B0_REGNUM,
+ B_REGISTER_SIZE, result_value);
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
- status = regcache_raw_read (regcache, v_regnum, reg_buf);
- if (status != REG_VALID)
- mark_value_bytes_unavailable (result_value, 0,
- TYPE_LENGTH (value_type (result_value)));
- else
- memcpy (buf, reg_buf, B_REGISTER_SIZE);
- return result_value;
- }
+ if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
+ && regnum < AARCH64_SVE_V0_REGNUM + 32)
+ return aarch64_pseudo_read_value_1 (gdbarch, regcache,
+ regnum - AARCH64_SVE_V0_REGNUM,
+ V_REGISTER_SIZE, result_value);
gdb_assert_not_reached ("regnum out of bound");
}
-/* Implement the "pseudo_register_write" gdbarch method. */
+/* Helper for aarch64_pseudo_write. */
static void
-aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
- int regnum, const gdb_byte *buf)
+aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum_offset, int regsize, const gdb_byte *buf)
{
- gdb_byte reg_buf[MAX_REGISTER_SIZE];
+ unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
+
+ /* Enough space for a full vector register. */
+ gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
+ gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
/* Ensure the register buffer is zero, we want gdb writes of the
various 'scalar' pseudo registers to behavior like architectural
writes, register width bytes are written the remainder are set to
zero. */
- memset (reg_buf, 0, sizeof (reg_buf));
+ memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
+
+ memcpy (reg_buf, buf, regsize);
+ regcache->raw_write (v_regnum, reg_buf);
+}
+/* Implement the "pseudo_register_write" gdbarch method. */
+
+static void
+aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum, const gdb_byte *buf)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
- {
- /* pseudo Q registers */
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
- memcpy (reg_buf, buf, Q_REGISTER_SIZE);
- regcache_raw_write (regcache, v_regnum, reg_buf);
- return;
- }
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
+ buf);
if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
- {
- /* pseudo D registers */
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
- memcpy (reg_buf, buf, D_REGISTER_SIZE);
- regcache_raw_write (regcache, v_regnum, reg_buf);
- return;
- }
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
+ buf);
if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
- {
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
- memcpy (reg_buf, buf, S_REGISTER_SIZE);
- regcache_raw_write (regcache, v_regnum, reg_buf);
- return;
- }
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
+ buf);
if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
- {
- /* pseudo H registers */
- unsigned v_regnum;
-
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
- memcpy (reg_buf, buf, H_REGISTER_SIZE);
- regcache_raw_write (regcache, v_regnum, reg_buf);
- return;
- }
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
+ buf);
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
- {
- /* pseudo B registers */
- unsigned v_regnum;
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
+ buf);
- v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
- memcpy (reg_buf, buf, B_REGISTER_SIZE);
- regcache_raw_write (regcache, v_regnum, reg_buf);
- return;
- }
+ if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
+ && regnum < AARCH64_SVE_V0_REGNUM + 32)
+ return aarch64_pseudo_write_1 (gdbarch, regcache,
+ regnum - AARCH64_SVE_V0_REGNUM,
+ V_REGISTER_SIZE, buf);
gdb_assert_not_reached ("regnum out of bound");
}
/* Implement the "software_single_step" gdbarch method, needed to
single step through atomic sequences on AArch64. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
aarch64_software_single_step (struct regcache *regcache)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
const int insn_size = 4;
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
- VEC (CORE_ADDR) *next_pcs = NULL;
- if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
+ return {};
/* Look for a Load Exclusive instruction which begins the sequence. */
if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
- return NULL;
+ return {};
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code);
- if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
+ return {};
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
if (bc_insn_count >= 1)
- return NULL;
+ return {};
/* It is, so we'll try to set a breakpoint at the destination. */
breaks[1] = loc + inst.operands[0].imm.value;
/* We didn't find a closing Store Exclusive instruction, fall back. */
if (!closing_insn)
- return NULL;
+ return {};
/* Insert breakpoint after the end of the atomic sequence. */
breaks[0] = loc + insn_size;
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Insert the breakpoint at the end of the sequence, and one at the
destination of the conditional branch, if it exists. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
-struct displaced_step_closure
+struct aarch64_displaced_step_closure : public displaced_step_closure
{
/* It is true when condition instruction, such as B.CON, TBZ, etc,
is being displaced stepping. */
- int cond;
+ int cond = 0;
/* PC adjustment offset after displaced stepping. */
- int32_t pc_adjust;
+ int32_t pc_adjust = 0;
};
/* Data when visiting instructions for displaced stepping. */
/* Registers when doing displaced stepping. */
struct regcache *regs;
- struct displaced_step_closure *dsc;
+ aarch64_displaced_step_closure *dsc;
};
/* Implementation of aarch64_insn_visitor method "b". */
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
- struct displaced_step_closure *dsc = NULL;
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
struct aarch64_displaced_step_data dsd;
aarch64_inst inst;
- if (aarch64_decode_insn (insn, &inst, 1) != 0)
+ if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return NULL;
/* Look for a Load Exclusive instruction which begins the sequence. */
return NULL;
}
- dsc = XCNEW (struct displaced_step_closure);
+ std::unique_ptr<aarch64_displaced_step_closure> dsc
+ (new aarch64_displaced_step_closure);
dsd.base.insn_addr = from;
dsd.new_addr = to;
dsd.regs = regs;
- dsd.dsc = dsc;
+ dsd.dsc = dsc.get ();
dsd.insn_count = 0;
aarch64_relocate_instruction (insn, &visitor,
(struct aarch64_insn_data *) &dsd);
}
else
{
- xfree (dsc);
dsc = NULL;
}
- return dsc;
+ return dsc.release ();
}
/* Implement the "displaced_step_fixup" gdbarch method. */
void
aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
- struct displaced_step_closure *dsc,
+ struct displaced_step_closure *dsc_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
+ aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
+
if (dsc->cond)
{
ULONGEST pc;
return 1;
}
+/* Get the correct target description for the given VQ value.
+ If VQ is zero then it is assumed SVE is not supported.
+ (It is not possible to set VQ to zero on an SVE system). */
+
+const target_desc *
+aarch64_read_description (uint64_t vq)
+{
+ if (vq > AARCH64_MAX_SVE_VQ)
+ error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
+ AARCH64_MAX_SVE_VQ);
+
+ struct target_desc *tdesc = tdesc_aarch64_list[vq];
+
+ if (tdesc == NULL)
+ {
+ tdesc = aarch64_create_target_description (vq);
+ tdesc_aarch64_list[vq] = tdesc;
+ }
+
+ return tdesc;
+}
+
+/* Return the VQ used when creating the target description TDESC. */
+
+static uint64_t
+aarch64_get_tdesc_vq (const struct target_desc *tdesc)
+{
+ const struct tdesc_feature *feature_sve;
+
+ if (!tdesc_has_registers (tdesc))
+ return 0;
+
+ feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
+
+ if (feature_sve == nullptr)
+ return 0;
+
+ uint64_t vl = tdesc_register_bitsize (feature_sve,
+ aarch64_sve_register_names[0]) / 8;
+ return sve_vq_from_vl (vl);
+}
+
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
const struct target_desc *tdesc = info.target_desc;
int i;
int valid_p = 1;
- const struct tdesc_feature *feature;
+ const struct tdesc_feature *feature_core;
+ const struct tdesc_feature *feature_fpu;
+ const struct tdesc_feature *feature_sve;
int num_regs = 0;
int num_pseudo_regs = 0;
- /* Ensure we always have a target descriptor. */
+ /* Ensure we always have a target description. */
if (!tdesc_has_registers (tdesc))
- tdesc = tdesc_aarch64;
-
+ tdesc = aarch64_read_description (0);
gdb_assert (tdesc);
- feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
+ feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
+ feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
+ feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
- if (feature == NULL)
+ if (feature_core == NULL)
return NULL;
tdesc_data = tdesc_data_alloc ();
- /* Validate the descriptor provides the mandatory core R registers
+ /* Validate the description provides the mandatory core R registers
and allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
- valid_p &=
- tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
- aarch64_r_register_names[i]);
+ valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
+ AARCH64_X0_REGNUM + i,
+ aarch64_r_register_names[i]);
num_regs = AARCH64_X0_REGNUM + i;
- /* Look for the V registers. */
- feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
- if (feature)
+ /* Add the V registers. */
+ if (feature_fpu != NULL)
{
- /* Validate the descriptor provides the mandatory V registers
- and allocate their numbers. */
+ if (feature_sve != NULL)
+ error (_("Program contains both fpu and SVE features."));
+
+ /* Validate the description provides the mandatory V registers
+ and allocate their numbers. */
for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
- valid_p &=
- tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
- aarch64_v_register_names[i]);
+ valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
+ AARCH64_V0_REGNUM + i,
+ aarch64_v_register_names[i]);
num_regs = AARCH64_V0_REGNUM + i;
+ }
+
+ /* Add the SVE registers. */
+ if (feature_sve != NULL)
+ {
+ /* Validate the description provides the mandatory SVE registers
+ and allocate their numbers. */
+ for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
+ valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
+ AARCH64_SVE_Z0_REGNUM + i,
+ aarch64_sve_register_names[i]);
+
+ num_regs = AARCH64_SVE_Z0_REGNUM + i;
+ num_pseudo_regs += 32; /* add the Vn register pseudos. */
+ }
+ if (feature_fpu != NULL || feature_sve != NULL)
+ {
num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
tdep->lowest_pc = 0x20;
tdep->jb_pc = -1; /* Longjump support not enabled by default. */
tdep->jb_elt_size = 8;
+ tdep->vq = aarch64_get_tdesc_vq (tdesc);
set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_char_signed (gdbarch, 0);
+ set_gdbarch_wchar_signed (gdbarch, 0);
set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
/* Hook in the ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
- info.tdep_info = (void *) tdesc_data;
+ info.tdesc_data = tdesc_data;
gdbarch_init_osabi (info, gdbarch);
dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
paddress (gdbarch, tdep->lowest_pc));
}
-/* Suppress warning from -Wmissing-prototypes. */
-extern initialize_file_ftype _initialize_aarch64_tdep;
+#if GDB_SELF_TEST
+namespace selftests
+{
+static void aarch64_process_record_test (void);
+}
+#endif
void
_initialize_aarch64_tdep (void)
gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
aarch64_dump_tdep);
- initialize_tdesc_aarch64 ();
-
/* Debug this file's internals. */
add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
Set AArch64 debugging."), _("\
&setdebuglist, &showdebuglist);
#if GDB_SELF_TEST
- register_self_test (selftests::aarch64_analyze_prologue_test);
+ selftests::register_test ("aarch64-analyze-prologue",
+ selftests::aarch64_analyze_prologue_test);
+ selftests::register_test ("aarch64-process-record",
+ selftests::aarch64_process_record_test);
+ selftests::record_xml_tdesc ("aarch64.xml",
+ aarch64_create_target_description (0));
#endif
}
enum aarch64_record_result
{
AARCH64_RECORD_SUCCESS,
- AARCH64_RECORD_FAILURE,
AARCH64_RECORD_UNSUPPORTED,
AARCH64_RECORD_UNKNOWN
};
{
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
- if (opc & 0x01)
- ld_flag = 0x01;
- else
- ld_flag = 0x0;
+ {
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
+ }
else
- if (size_bits != 0x03)
- ld_flag = 0x01;
- else
- return AARCH64_RECORD_UNKNOWN;
+ {
+ if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
+ {
+ /* PRFM (immediate) */
+ return AARCH64_RECORD_SUCCESS;
+ }
+ else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
+ {
+ /* LDRSW (immediate) */
+ ld_flag = 0x1;
+ }
+ else
+ {
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
+ }
+ }
if (record_debug)
{
xfree (record->aarch64_mems);
}
+#if GDB_SELF_TEST
+namespace selftests {
+
+static void
+aarch64_process_record_test (void)
+{
+ struct gdbarch_info info;
+ uint32_t ret;
+
+ gdbarch_info_init (&info);
+ info.bfd_arch_info = bfd_scan_arch ("aarch64");
+
+ struct gdbarch *gdbarch = gdbarch_find_by_info (info);
+ SELF_CHECK (gdbarch != NULL);
+
+ insn_decode_record aarch64_record;
+
+ memset (&aarch64_record, 0, sizeof (insn_decode_record));
+ aarch64_record.regcache = NULL;
+ aarch64_record.this_addr = 0;
+ aarch64_record.gdbarch = gdbarch;
+
+ /* 20 00 80 f9 prfm pldl1keep, [x1] */
+ aarch64_record.aarch64_insn = 0xf9800020;
+ ret = aarch64_record_decode_insn_handler (&aarch64_record);
+ SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
+ SELF_CHECK (aarch64_record.reg_rec_count == 0);
+ SELF_CHECK (aarch64_record.mem_rec_count == 0);
+
+ deallocate_reg_mem (&aarch64_record);
+}
+
+} // namespace selftests
+#endif /* GDB_SELF_TEST */
+
/* Parse the current instruction and record the values of the registers and
memory that will be changed in current instruction to record_arch_list
return -1 if something is wrong. */
projects / deliverable / binutils-gdb.git / blobdiff