/* Common target dependent code for GDB on AArch64 systems.
- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+ Copyright (C) 2009-2019 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
/* AArch64 Dwarf register numbering. */
#define AARCH64_DWARF_X0 0
#define AARCH64_DWARF_SP 31
+#define AARCH64_DWARF_PAUTH_RA_STATE 34
+#define AARCH64_DWARF_PAUTH_DMASK 35
+#define AARCH64_DWARF_PAUTH_CMASK 36
#define AARCH64_DWARF_V0 64
+#define AARCH64_DWARF_SVE_VG 46
+#define AARCH64_DWARF_SVE_FFR 47
+#define AARCH64_DWARF_SVE_P0 48
+#define AARCH64_DWARF_SVE_Z0 96
/* Size of integer registers. */
#define X_REGISTER_SIZE 8
/* The maximum number of modified instructions generated for one
single-stepped instruction. */
-#define DISPLACED_MODIFIED_INSNS 1
+#define AARCH64_DISPLACED_MODIFIED_INSNS 1
/* Target-dependent structure in gdbarch. */
struct gdbarch_tdep
struct type *vns_type;
struct type *vnh_type;
struct type *vnb_type;
+ struct type *vnv_type;
/* syscall record. */
int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
+
+ /* The VQ value for SVE targets, or zero if SVE is not supported. */
+ uint64_t vq;
+
+ /* Returns true if the target supports SVE. */
+ bool has_sve () const
+ {
+ return vq != 0;
+ }
+
+ int pauth_reg_base;
+ int pauth_ra_state_regnum;
+
+ /* Returns true if the target supports pauth. */
+ bool has_pauth () const
+ {
+ return pauth_reg_base != -1;
+ }
};
-const target_desc *aarch64_read_description ();
+const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p);
extern int aarch64_process_record (struct gdbarch *gdbarch,
struct regcache *regcache, CORE_ADDR addr);