/* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+ 2003, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
This file is part of GDB.
#include "alpha-tdep.h"
+/* Instruction decoding. The notations for registers, immediates and
+ opcodes are the same as the one used in Compaq's Alpha architecture
+ handbook. */
+
+#define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
+
+/* Memory instruction format */
+#define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
+#define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
+#define MEM_DISP(insn) \
+ (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
+
+static const int lda_opcode = 0x08;
+static const int stq_opcode = 0x2d;
+
+/* Branch instruction format */
+#define BR_RA(insn) MEM_RA(insn)
+
+static const int bne_opcode = 0x3d;
+
+/* Operate instruction format */
+#define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
+#define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
+#define OPR_RA(insn) MEM_RA(insn)
+#define OPR_RC(insn) ((insn & 0x1f))
+#define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
+
+static const int subq_opcode = 0x10;
+static const int subq_function = 0x29;
+
\f
/* Return the name of the REGNO register.
floating point and 32-bit integers. */
static void
-alpha_lds (void *out, const void *in)
+alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
{
- ULONGEST mem = extract_unsigned_integer (in, 4);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ ULONGEST mem = extract_unsigned_integer (in, 4, byte_order);
ULONGEST frac = (mem >> 0) & 0x7fffff;
ULONGEST sign = (mem >> 31) & 1;
ULONGEST exp_msb = (mem >> 30) & 1;
}
reg = (sign << 63) | (exp << 52) | (frac << 29);
- store_unsigned_integer (out, 8, reg);
+ store_unsigned_integer (out, 8, byte_order, reg);
}
/* Similarly, this represents exactly the conversion performed by
the STS instruction. */
static void
-alpha_sts (void *out, const void *in)
+alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST reg, mem;
- reg = extract_unsigned_integer (in, 8);
+ reg = extract_unsigned_integer (in, 8, byte_order);
mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
- store_unsigned_integer (out, 4, mem);
+ store_unsigned_integer (out, 4, byte_order, mem);
}
/* The alpha needs a conversion between register and memory format if the
switch (TYPE_LENGTH (valtype))
{
case 4:
- alpha_sts (out, in);
+ alpha_sts (get_frame_arch (frame), out, in);
break;
default:
error (_("Cannot retrieve value from floating point register"));
switch (TYPE_LENGTH (valtype))
{
case 4:
- alpha_lds (out, in);
+ alpha_lds (get_frame_arch (frame), out, in);
break;
default:
error (_("Cannot store value in floating point register"));
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int i;
int accumulate_size = struct_return ? 8 : 0;
struct alpha_arg
write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
}
if (struct_return)
- store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, struct_addr);
+ store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
+ byte_order, struct_addr);
/* Load the argument registers. */
for (i = 0; i < required_arg_regs; i++)
alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
gdb_byte *valbuf)
{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int length = TYPE_LENGTH (valtype);
gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
ULONGEST l;
{
case 4:
regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
- alpha_sts (valbuf, raw_buffer);
+ alpha_sts (gdbarch, valbuf, raw_buffer);
break;
case 8:
default:
/* Assume everything else degenerates to an integer. */
regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
- store_unsigned_integer (valbuf, length, l);
+ store_unsigned_integer (valbuf, length, byte_order, l);
break;
}
}
switch (length)
{
case 4:
- alpha_lds (raw_buffer, valbuf);
+ alpha_lds (gdbarch, raw_buffer, valbuf);
regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
break;
/* Read an instruction from memory at PC, looking through breakpoints. */
unsigned int
-alpha_read_insn (CORE_ADDR pc)
+alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[ALPHA_INSN_SIZE];
int status;
status = target_read_memory (pc, buf, sizeof (buf));
if (status)
memory_error (status, pc);
- return extract_unsigned_integer (buf, sizeof (buf));
+ return extract_unsigned_integer (buf, sizeof (buf), byte_order);
}
/* To skip prologues, I use this predicate. Returns either PC itself
or in the gcc frame. */
for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
{
- inst = alpha_read_insn (pc + offset);
+ inst = alpha_read_insn (gdbarch, pc + offset);
if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
continue;
static int
alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR jb_addr;
gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
raw_buffer, tdep->jb_elt_size))
return 0;
- *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size);
+ *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
return 1;
}
{
int offset;
code_addr = get_frame_pc (this_frame);
- offset = tdep->dynamic_sigtramp_offset (code_addr);
+ offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
if (offset >= 0)
code_addr -= offset;
else
/* Otherwise we should be in a signal frame. */
find_pc_partial_function (pc, &name, NULL, NULL);
- if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (pc, name))
+ if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
return 1;
return 0;
nops, since this usually indicates padding between functions. */
for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
{
- unsigned int insn = alpha_read_insn (pc);
+ unsigned int insn = alpha_read_insn (gdbarch, pc);
switch (insn)
{
case 0: /* invalid insn */
int return_reg;
};
+/* If a probing loop sequence starts at PC, simulate it and compute
+ FRAME_SIZE and PC after its execution. Otherwise, return with PC and
+ FRAME_SIZE unchanged. */
+
+static void
+alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc,
+ int *frame_size)
+{
+ CORE_ADDR cur_pc = *pc;
+ int cur_frame_size = *frame_size;
+ int nb_of_iterations, reg_index, reg_probe;
+ unsigned int insn;
+
+ /* The following pattern is recognized as a probing loop:
+
+ lda REG_INDEX,NB_OF_ITERATIONS
+ lda REG_PROBE,<immediate>(sp)
+
+ LOOP_START:
+ stq zero,<immediate>(REG_PROBE)
+ subq REG_INDEX,0x1,REG_INDEX
+ lda REG_PROBE,<immediate>(REG_PROBE)
+ bne REG_INDEX, LOOP_START
+
+ lda sp,<immediate>(REG_PROBE)
+
+ If anything different is found, the function returns without
+ changing PC and FRAME_SIZE. Otherwise, PC will point immediately
+ after this sequence, and FRAME_SIZE will be updated.
+ */
+
+ /* lda REG_INDEX,NB_OF_ITERATIONS */
+
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != lda_opcode)
+ return;
+ reg_index = MEM_RA (insn);
+ nb_of_iterations = MEM_DISP (insn);
+
+ /* lda REG_PROBE,<immediate>(sp) */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != lda_opcode
+ || MEM_RB (insn) != ALPHA_SP_REGNUM)
+ return;
+ reg_probe = MEM_RA (insn);
+ cur_frame_size -= MEM_DISP (insn);
+
+ /* stq zero,<immediate>(REG_PROBE) */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != stq_opcode
+ || MEM_RA (insn) != 0x1f
+ || MEM_RB (insn) != reg_probe)
+ return;
+
+ /* subq REG_INDEX,0x1,REG_INDEX */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != subq_opcode
+ || !OPR_HAS_IMMEDIATE (insn)
+ || OPR_FUNCTION (insn) != subq_function
+ || OPR_LIT(insn) != 1
+ || OPR_RA (insn) != reg_index
+ || OPR_RC (insn) != reg_index)
+ return;
+
+ /* lda REG_PROBE,<immediate>(REG_PROBE) */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != lda_opcode
+ || MEM_RA (insn) != reg_probe
+ || MEM_RB (insn) != reg_probe)
+ return;
+ cur_frame_size -= MEM_DISP (insn) * nb_of_iterations;
+
+ /* bne REG_INDEX, LOOP_START */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != bne_opcode
+ || MEM_RA (insn) != reg_index)
+ return;
+
+ /* lda sp,<immediate>(REG_PROBE) */
+
+ cur_pc += ALPHA_INSN_SIZE;
+ insn = alpha_read_insn (gdbarch, cur_pc);
+ if (INSN_OPCODE (insn) != lda_opcode
+ || MEM_RA (insn) != ALPHA_SP_REGNUM
+ || MEM_RB (insn) != reg_probe)
+ return;
+ cur_frame_size -= MEM_DISP (insn);
+
+ *pc = cur_pc;
+ *frame_size = cur_frame_size;
+}
+
static struct alpha_heuristic_unwind_cache *
alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
void **this_prologue_cache,
for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
{
- unsigned int word = alpha_read_insn (cur_pc);
+ unsigned int word = alpha_read_insn (gdbarch, cur_pc);
if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
{
frame_reg = ALPHA_GCC_FP_REGNUM;
else if (word == 0x47fe040f) /* bis zero,sp,fp */
frame_reg = ALPHA_GCC_FP_REGNUM;
+
+ alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size);
}
/* If we haven't found a valid return address register yet, keep
{
while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
{
- unsigned int word = alpha_read_insn (cur_pc);
+ unsigned int word = alpha_read_insn (gdbarch, cur_pc);
if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
{
static CORE_ADDR
alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
unsigned int insn;
unsigned int op;
int regno;
int offset;
LONGEST rav;
- insn = alpha_read_insn (pc);
+ insn = alpha_read_insn (gdbarch, pc);
/* Opcode is top 6 bits. */
op = (insn >> 26) & 0x3f;
{
/* Branch format: target PC is:
(new PC) + (4 * sext(displacement)) */
- if (op == 0x30 || /* BR */
- op == 0x34) /* BSR */
+ if (op == 0x30 /* BR */
+ || op == 0x34) /* BSR */
{
branch_taken:
offset = (insn & 0x001fffff);
case 0x33: /* FBLE */
case 0x32: /* FBLT */
case 0x35: /* FBNE */
- regno += gdbarch_fp0_regnum (get_frame_arch (frame));
+ regno += gdbarch_fp0_regnum (gdbarch);
}
rav = get_frame_register_signed (frame, regno);
alpha_software_single_step (struct frame_info *frame)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
+ struct address_space *aspace = get_frame_address_space (frame);
CORE_ADDR pc, next_pc;
pc = get_frame_pc (frame);
next_pc = alpha_next_pc (frame, pc);
- insert_single_step_breakpoint (gdbarch, next_pc);
+ insert_single_step_breakpoint (gdbarch, aspace, next_pc);
return 1;
}
projects / deliverable / binutils-gdb.git / blobdiff