/* Target-dependent code for AMD64.
- Copyright (C) 2001-2017 Free Software Foundation, Inc.
+ Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
#include "i387-tdep.h"
#include "x86-xstate.h"
#include <algorithm>
-
-#include "features/i386/amd64.c"
-#include "features/i386/amd64-avx.c"
-#include "features/i386/amd64-mpx.c"
-#include "features/i386/amd64-avx-mpx.c"
-#include "features/i386/amd64-avx512.c"
-
-#include "features/i386/x32.c"
-#include "features/i386/x32-avx.c"
-#include "features/i386/x32-avx512.c"
-
+#include "target-descriptions.h"
+#include "arch/amd64.h"
+#include "producer.h"
#include "ax.h"
#include "ax-gdb.h"
+#include "common/byte-vector.h"
/* Note that the AMD64 architecture was previously known as x86-64.
The latter is (forever) engraved into the canonical system name as
"xmm28", "xmm29", "xmm30", "xmm31"
};
+static const char *amd64_pkeys_names[] = {
+ "pkru"
+};
+
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
static struct value *
amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
- struct regcache *regcache,
+ readable_regcache *regcache,
int regnum)
{
gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
{
/* Special handling for AH, BH, CH, DH. */
- status = regcache_raw_read (regcache,
- gpnum - AMD64_NUM_LOWER_BYTE_REGS,
- raw_buf);
+ status = regcache->raw_read (gpnum - AMD64_NUM_LOWER_BYTE_REGS,
+ raw_buf);
if (status == REG_VALID)
memcpy (buf, raw_buf + 1, 1);
else
}
else
{
- status = regcache_raw_read (regcache, gpnum, raw_buf);
+ status = regcache->raw_read (gpnum, raw_buf);
if (status == REG_VALID)
memcpy (buf, raw_buf, 1);
else
{
int gpnum = regnum - tdep->eax_regnum;
/* Extract (always little endian). */
- status = regcache_raw_read (regcache, gpnum, raw_buf);
+ status = regcache->raw_read (gpnum, raw_buf);
if (status == REG_VALID)
memcpy (buf, raw_buf, 4);
else
if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
|| code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
|| code == TYPE_CODE_CHAR
- || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
+ || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
&& (len == 1 || len == 2 || len == 4 || len == 8))
theclass[0] = AMD64_INTEGER;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[8];
+ /* BND registers can be in arbitrary values at the moment of the
+ inferior call. This can cause boundary violations that are not
+ due to a real bug or even desired by the user. The best to be done
+ is set the BND registers to allow access to the whole memory, INIT
+ state, before pushing the inferior call. */
+ i387_reset_bnd_regs (gdbarch, regcache);
+
/* Pass arguments. */
sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
{
/* The number of opcode bytes. */
int opcode_len;
- /* The offset of the rex prefix or -1 if not present. */
- int rex_offset;
+ /* The offset of the REX/VEX instruction encoding prefix or -1 if
+ not present. */
+ int enc_prefix_offset;
/* The offset to the first opcode byte. */
int opcode_offset;
/* The offset to the modrm byte or -1 if not present. */
gdb_byte *raw_insn;
};
-struct displaced_step_closure
+struct amd64_displaced_step_closure : public displaced_step_closure
{
+ amd64_displaced_step_closure (int insn_buf_len)
+ : insn_buf (insn_buf_len, 0)
+ {}
+
/* For rip-relative insns, saved copy of the reg we use instead of %rip. */
- int tmp_used;
+ int tmp_used = 0;
int tmp_regno;
ULONGEST tmp_save;
/* Details of the instruction. */
struct amd64_insn insn_details;
- /* Amount of space allocated to insn_buf. */
- int max_len;
-
- /* The possibly modified insn.
- This is a variable-length field. */
- gdb_byte insn_buf[1];
+ /* The possibly modified insn. */
+ gdb::byte_vector insn_buf;
};
/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
return REX_PREFIX_P (pfx);
}
+/* True if PFX is the start of the 2-byte VEX prefix. */
+
+static bool
+vex2_prefix_p (gdb_byte pfx)
+{
+ return pfx == 0xc5;
+}
+
+/* True if PFX is the start of the 3-byte VEX prefix. */
+
+static bool
+vex3_prefix_p (gdb_byte pfx)
+{
+ return pfx == 0xc4;
+}
+
/* Skip the legacy instruction prefixes in INSN.
We assume INSN is properly sentineled so we don't have to worry
about falling off the end of the buffer. */
details->raw_insn = insn;
details->opcode_len = -1;
- details->rex_offset = -1;
+ details->enc_prefix_offset = -1;
details->opcode_offset = -1;
details->modrm_offset = -1;
/* Skip legacy instruction prefixes. */
insn = amd64_skip_prefixes (insn);
- /* Skip REX instruction prefix. */
+ /* Skip REX/VEX instruction encoding prefixes. */
if (rex_prefix_p (*insn))
{
- details->rex_offset = insn - start;
+ details->enc_prefix_offset = insn - start;
++insn;
}
+ else if (vex2_prefix_p (*insn))
+ {
+ /* Don't record the offset in this case because this prefix has
+ no REX.B equivalent. */
+ insn += 2;
+ }
+ else if (vex3_prefix_p (*insn))
+ {
+ details->enc_prefix_offset = insn - start;
+ insn += 3;
+ }
details->opcode_offset = insn - start;
We set base = pc + insn_length so we can leave disp unchanged. */
static void
-fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
+fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
{
const struct amd64_insn *insn_details = &dsc->insn_details;
++insn;
/* Compute the rip-relative address. */
- insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
- dsc->max_len, from);
+ insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
+ dsc->insn_buf.size (), from);
rip_base = from + insn_length;
/* We need a register to hold the address.
arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
- /* REX.B should be unset as we were using rip-relative addressing,
- but ensure it's unset anyway, tmp_regno is not r8-r15. */
- if (insn_details->rex_offset != -1)
- dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
+ /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
+ static constexpr gdb_byte VEX3_NOT_B = 0x20;
+
+ /* REX.B should be unset (VEX.!B set) as we were using rip-relative
+ addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
+ is not r8-r15. */
+ if (insn_details->enc_prefix_offset != -1)
+ {
+ gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
+ if (rex_prefix_p (pfx[0]))
+ pfx[0] &= ~REX_B;
+ else if (vex3_prefix_p (pfx[0]))
+ pfx[1] |= VEX3_NOT_B;
+ else
+ gdb_assert_not_reached ("unhandled prefix");
+ }
regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
dsc->tmp_regno = tmp_regno;
static void
fixup_displaced_copy (struct gdbarch *gdbarch,
- struct displaced_step_closure *dsc,
+ amd64_displaced_step_closure *dsc,
CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
{
const struct amd64_insn *details = &dsc->insn_details;
/* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
continually watch for running off the end of the buffer. */
int fixup_sentinel_space = len;
- struct displaced_step_closure *dsc
- = ((struct displaced_step_closure *)
- xmalloc (sizeof (*dsc) + len + fixup_sentinel_space));
+ amd64_displaced_step_closure *dsc
+ = new amd64_displaced_step_closure (len + fixup_sentinel_space);
gdb_byte *buf = &dsc->insn_buf[0];
struct amd64_insn *details = &dsc->insn_details;
- dsc->tmp_used = 0;
- dsc->max_len = len + fixup_sentinel_space;
-
read_memory (from, buf, len);
/* Set up the sentinel space so we don't have to worry about running
void
amd64_displaced_step_fixup (struct gdbarch *gdbarch,
- struct displaced_step_closure *dsc,
+ struct displaced_step_closure *dsc_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
+ amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* The offset we applied to the instruction's address. */
ULONGEST insn_offset = to - from;
- gdb_byte *insn = dsc->insn_buf;
+ gdb_byte *insn = dsc->insn_buf.data ();
const struct amd64_insn *insn_details = &dsc->insn_details;
if (debug_displaced)
amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_assert (len >= tdep->sizeof_fpregset);
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_assert (len >= tdep->sizeof_fpregset);
};
void
-amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
+ const target_desc *default_tdesc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct target_desc *tdesc = info.target_desc;
tdep->fpregset = &amd64_fpregset;
if (! tdesc_has_registers (tdesc))
- tdesc = tdesc_amd64;
+ tdesc = default_tdesc;
tdep->tdesc = tdesc;
tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
AMD64_GSBASE_REGNUM, "gs_base");
}
+ if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
+ {
+ tdep->pkeys_register_names = amd64_pkeys_names;
+ tdep->pkru_regnum = AMD64_PKRU_REGNUM;
+ tdep->num_pkeys_regs = 1;
+ }
+
tdep->num_byte_regs = 20;
tdep->num_word_regs = 16;
tdep->num_dword_regs = 16;
}
void
-amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
+ const target_desc *default_tdesc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- const struct target_desc *tdesc = info.target_desc;
- amd64_init_abi (info, gdbarch);
-
- if (! tdesc_has_registers (tdesc))
- tdesc = tdesc_x32;
- tdep->tdesc = tdesc;
+ amd64_init_abi (info, gdbarch, default_tdesc);
tdep->num_dword_regs = 17;
set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
const struct target_desc *
amd64_target_description (uint64_t xcr0)
{
- switch (xcr0 & X86_XSTATE_ALL_MASK)
- {
- case X86_XSTATE_MPX_AVX512_MASK:
- case X86_XSTATE_AVX512_MASK:
- return tdesc_amd64_avx512;
- case X86_XSTATE_MPX_MASK:
- return tdesc_amd64_mpx;
- case X86_XSTATE_AVX_MPX_MASK:
- return tdesc_amd64_avx_mpx;
- case X86_XSTATE_AVX_MASK:
- return tdesc_amd64_avx;
- default:
- return tdesc_amd64;
- }
-}
+ static target_desc *amd64_tdescs \
+ [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
+ target_desc **tdesc;
+
+ tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
+ [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
-/* Provide a prototype to silence -Wmissing-prototypes. */
-void _initialize_amd64_tdep (void);
+ if (*tdesc == NULL)
+ *tdesc = amd64_create_target_description (xcr0, false, false);
+
+ return *tdesc;
+}
void
_initialize_amd64_tdep (void)
{
- initialize_tdesc_amd64 ();
- initialize_tdesc_amd64_avx ();
- initialize_tdesc_amd64_mpx ();
- initialize_tdesc_amd64_avx_mpx ();
- initialize_tdesc_amd64_avx512 ();
+#if GDB_SELF_TEST
+ struct
+ {
+ const char *xml;
+ uint64_t mask;
+ } xml_masks[] = {
+ { "i386/amd64.xml", X86_XSTATE_SSE_MASK },
+ { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK },
+ { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK },
+ { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
+ { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
+ { "i386/amd64-avx-mpx-avx512-pku.xml",
+ X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
+ };
- initialize_tdesc_x32 ();
- initialize_tdesc_x32_avx ();
- initialize_tdesc_x32_avx512 ();
+ for (auto &a : xml_masks)
+ {
+ auto tdesc = amd64_target_description (a.mask);
+
+ selftests::record_xml_tdesc (a.xml, tdesc);
+ }
+#endif /* GDB_SELF_TEST */
}
\f
amd64_supply_fxsave (struct regcache *regcache, int regnum,
const void *fxsave)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
i387_supply_fxsave (regcache, regnum, fxsave);
amd64_supply_xsave (struct regcache *regcache, int regnum,
const void *xsave)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
i387_supply_xsave (regcache, regnum, xsave);
amd64_collect_fxsave (const struct regcache *regcache, int regnum,
void *fxsave)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_byte *regs = (gdb_byte *) fxsave;
amd64_collect_xsave (const struct regcache *regcache, int regnum,
void *xsave, int gcore)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
gdb_byte *regs = (gdb_byte *) xsave;
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