/* Target-dependent code for AMD64.
- Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation,
- Inc. Contributed by Jiri Smid, SuSE Labs.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
+
+ Contributed by Jiri Smid, SuSE Labs.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "arch-utils.h"
/* Register information. */
-struct amd64_register_info
-{
- char *name;
- struct type **type;
-};
-
-static struct amd64_register_info amd64_register_info[] =
+static const char *amd64_register_names[] =
{
- { "rax", &builtin_type_int64 },
- { "rbx", &builtin_type_int64 },
- { "rcx", &builtin_type_int64 },
- { "rdx", &builtin_type_int64 },
- { "rsi", &builtin_type_int64 },
- { "rdi", &builtin_type_int64 },
- { "rbp", &builtin_type_void_data_ptr },
- { "rsp", &builtin_type_void_data_ptr },
+ "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
/* %r8 is indeed register number 8. */
- { "r8", &builtin_type_int64 },
- { "r9", &builtin_type_int64 },
- { "r10", &builtin_type_int64 },
- { "r11", &builtin_type_int64 },
- { "r12", &builtin_type_int64 },
- { "r13", &builtin_type_int64 },
- { "r14", &builtin_type_int64 },
- { "r15", &builtin_type_int64 },
- { "rip", &builtin_type_void_func_ptr },
- { "eflags", &builtin_type_int32 },
- { "cs", &builtin_type_int32 },
- { "ss", &builtin_type_int32 },
- { "ds", &builtin_type_int32 },
- { "es", &builtin_type_int32 },
- { "fs", &builtin_type_int32 },
- { "gs", &builtin_type_int32 },
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
/* %st0 is register number 24. */
- { "st0", &builtin_type_i387_ext },
- { "st1", &builtin_type_i387_ext },
- { "st2", &builtin_type_i387_ext },
- { "st3", &builtin_type_i387_ext },
- { "st4", &builtin_type_i387_ext },
- { "st5", &builtin_type_i387_ext },
- { "st6", &builtin_type_i387_ext },
- { "st7", &builtin_type_i387_ext },
- { "fctrl", &builtin_type_int32 },
- { "fstat", &builtin_type_int32 },
- { "ftag", &builtin_type_int32 },
- { "fiseg", &builtin_type_int32 },
- { "fioff", &builtin_type_int32 },
- { "foseg", &builtin_type_int32 },
- { "fooff", &builtin_type_int32 },
- { "fop", &builtin_type_int32 },
+ "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
+ "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
/* %xmm0 is register number 40. */
- { "xmm0", &builtin_type_v4sf },
- { "xmm1", &builtin_type_v4sf },
- { "xmm2", &builtin_type_v4sf },
- { "xmm3", &builtin_type_v4sf },
- { "xmm4", &builtin_type_v4sf },
- { "xmm5", &builtin_type_v4sf },
- { "xmm6", &builtin_type_v4sf },
- { "xmm7", &builtin_type_v4sf },
- { "xmm8", &builtin_type_v4sf },
- { "xmm9", &builtin_type_v4sf },
- { "xmm10", &builtin_type_v4sf },
- { "xmm11", &builtin_type_v4sf },
- { "xmm12", &builtin_type_v4sf },
- { "xmm13", &builtin_type_v4sf },
- { "xmm14", &builtin_type_v4sf },
- { "xmm15", &builtin_type_v4sf },
- { "mxcsr", &builtin_type_int32 }
+ "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
+ "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
+ "mxcsr",
};
/* Total number of registers. */
-#define AMD64_NUM_REGS \
- (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
+#define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
/* Return the name of register REGNUM. */
-static const char *
-amd64_register_name (int regnum)
+const char *
+amd64_register_name (struct gdbarch *gdbarch, int regnum)
{
if (regnum >= 0 && regnum < AMD64_NUM_REGS)
- return amd64_register_info[regnum].name;
+ return amd64_register_names[regnum];
return NULL;
}
/* Return the GDB type object for the "standard" data type of data in
register REGNUM. */
-static struct type *
+struct type *
amd64_register_type (struct gdbarch *gdbarch, int regnum)
{
- gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
-
- return *amd64_register_info[regnum].type;
+ if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM)
+ return builtin_type_int64;
+ if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM)
+ return builtin_type_void_data_ptr;
+ if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM)
+ return builtin_type_int64;
+ if (regnum == AMD64_RIP_REGNUM)
+ return builtin_type_void_func_ptr;
+ if (regnum == AMD64_EFLAGS_REGNUM)
+ return i386_eflags_type;
+ if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM)
+ return builtin_type_int32;
+ if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7)
+ return builtin_type_i387_ext;
+ if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7)
+ return builtin_type_int32;
+ if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15)
+ return i386_sse_type (gdbarch);
+ if (regnum == AMD64_MXCSR_REGNUM)
+ return i386_mxcsr_type;
+
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
}
/* DWARF Register Number Mapping as defined in the System V psABI,
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
- AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
+
+ /* Control and Status Flags Register. */
+ AMD64_EFLAGS_REGNUM,
+
+ /* Selector Registers. */
+ AMD64_ES_REGNUM,
+ AMD64_CS_REGNUM,
+ AMD64_SS_REGNUM,
+ AMD64_DS_REGNUM,
+ AMD64_FS_REGNUM,
+ AMD64_GS_REGNUM,
+ -1,
+ -1,
+
+ /* Segment Base Address Registers. */
+ -1,
+ -1,
+ -1,
+ -1,
+
+ /* Special Selector Registers. */
+ -1,
+ -1,
+
+ /* Floating Point Control Registers. */
+ AMD64_MXCSR_REGNUM,
+ AMD64_FCTRL_REGNUM,
+ AMD64_FSTAT_REGNUM
};
static const int amd64_dwarf_regmap_len =
number used by GDB. */
static int
-amd64_dwarf_reg_to_regnum (int reg)
+amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
int regnum = -1;
return regnum;
}
-/* Return nonzero if a value of type TYPE stored in register REGNUM
- needs any special handling. */
-
-static int
-amd64_convert_register_p (int regnum, struct type *type)
-{
- return i386_fp_regnum_p (regnum);
-}
\f
/* Register classes as defined in the psABI. */
range types, used by languages such as Ada, are also in the INTEGER
class. */
if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
- || code == TYPE_CODE_RANGE
+ || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
|| code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
&& (len == 1 || len == 2 || len == 4 || len == 8))
class[0] = AMD64_INTEGER;
static enum return_value_convention
amd64_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache,
- void *readbuf, const void *writebuf)
+ gdb_byte *readbuf, const gdb_byte *writebuf)
{
enum amd64_reg_class class[2];
int len = TYPE_LENGTH (type);
if (readbuf)
regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
- ((gdb_byte *)readbuf) + i * 8);
+ readbuf + i * 8);
if (writebuf)
regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
- ((const gdb_byte *)writebuf) + i * 8);
+ writebuf + i * 8);
}
return RETURN_VALUE_REGISTER_CONVENTION;
int frameless_p;
};
-/* Allocate and initialize a frame cache. */
+/* Initialize a frame cache. */
-static struct amd64_frame_cache *
-amd64_alloc_frame_cache (void)
+static void
+amd64_init_frame_cache (struct amd64_frame_cache *cache)
{
- struct amd64_frame_cache *cache;
int i;
- cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
-
/* Base address. */
cache->base = 0;
cache->sp_offset = -8;
/* Frameless until proven otherwise. */
cache->frameless_p = 1;
+}
+/* Allocate and initialize a frame cache. */
+
+static struct amd64_frame_cache *
+amd64_alloc_frame_cache (void)
+{
+ struct amd64_frame_cache *cache;
+
+ cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
+ amd64_init_frame_cache (cache);
return cache;
}
/* Return PC of first real instruction. */
static CORE_ADDR
-amd64_skip_prologue (CORE_ADDR start_pc)
+amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
{
struct amd64_frame_cache cache;
CORE_ADDR pc;
+ amd64_init_frame_cache (&cache);
pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
if (cache.frameless_p)
return start_pc;
cache = amd64_alloc_frame_cache ();
*this_cache = cache;
- cache->pc = frame_func_unwind (next_frame);
+ cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
if (cache->pc != 0)
amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
int regnum, int *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+ int *realnump, gdb_byte *valuep)
{
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
struct amd64_frame_cache *cache =
amd64_frame_cache (next_frame, this_cache);
gdb_assert (regnum >= 0);
- if (regnum == SP_REGNUM && cache->saved_sp)
+ if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
{
*optimizedp = 0;
*lvalp = not_lval;
{
/* Read the value in from memory. */
read_memory (*addrp, valuep,
- register_size (current_gdbarch, regnum));
+ register_size (gdbarch, regnum));
}
return;
}
amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
{
struct amd64_frame_cache *cache;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
CORE_ADDR addr;
gdb_byte buf[8];
int i;
void **this_cache,
int regnum, int *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+ int *realnump, gdb_byte *valuep)
{
/* Make sure we've initialized the cache. */
amd64_sigtramp_frame_cache (next_frame, this_cache);
set_gdbarch_frame_align (gdbarch, amd64_frame_align);
set_gdbarch_frame_red_zone_size (gdbarch, 128);
- set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
+ set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
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