/* Target-dependent code for AMD64.
- Copyright (C) 2001-2015 Free Software Foundation, Inc.
+ Copyright (C) 2001-2016 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
#include "disasm.h"
#include "amd64-tdep.h"
#include "i387-tdep.h"
+#include "x86-xstate.h"
#include "features/i386/amd64.c"
#include "features/i386/amd64-avx.c"
if (reg >= 0 && reg < amd64_dwarf_regmap_len)
regnum = amd64_dwarf_regmap[reg];
- if (regnum == -1)
- warning (_("Unmapped DWARF Register #%d encountered."), reg);
- else if (ymm0_regnum >= 0
+ if (ymm0_regnum >= 0
&& i386_xmm_regnum_p (gdbarch, regnum))
regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
}
+/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
+
+static int
+amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
+ struct agent_expr *ax, int regnum)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (i386_byte_regnum_p (gdbarch, regnum))
+ {
+ int gpnum = regnum - tdep->al_regnum;
+
+ if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
+ ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
+ else
+ ax_reg_mask (ax, gpnum);
+ return 0;
+ }
+ else if (i386_dword_regnum_p (gdbarch, regnum))
+ {
+ int gpnum = regnum - tdep->eax_regnum;
+
+ ax_reg_mask (ax, gpnum);
+ return 0;
+ }
+ else
+ return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
+}
+
\f
/* Register classes as defined in the psABI. */
AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
};
- struct value **stack_args = alloca (nargs * sizeof (struct value *));
+ struct value **stack_args = XALLOCAVEC (struct value *, nargs);
int num_stack_args = 0;
int num_elements = 0;
int element = 0;
/* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
continually watch for running off the end of the buffer. */
int fixup_sentinel_space = len;
- struct displaced_step_closure *dsc =
- xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
+ struct displaced_step_closure *dsc
+ = ((struct displaced_step_closure *)
+ xmalloc (sizeof (*dsc) + len + fixup_sentinel_space));
gdb_byte *buf = &dsc->insn_buf[0];
struct amd64_insn *details = &dsc->insn_details;
int len, classification;
len = gdbarch_max_insn_length (gdbarch);
- buf = alloca (len);
+ buf = (gdb_byte *) alloca (len);
read_code (addr, buf, len);
amd64_get_insn_details (buf, &details);
regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
- retaddr = (retaddr - insn_offset) & 0xffffffffUL;
+ retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
if (debug_displaced)
int len = gdbarch_max_insn_length (gdbarch);
/* Extra space for sentinels. */
int fixup_sentinel_space = len;
- gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
+ gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
struct amd64_insn insn_details;
int offset = 0;
LONGEST rel32, newrel;
static struct amd64_frame_cache *
amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
{
- volatile struct gdb_exception ex;
struct amd64_frame_cache *cache;
if (*this_cache)
- return *this_cache;
+ return (struct amd64_frame_cache *) *this_cache;
cache = amd64_alloc_frame_cache ();
*this_cache = cache;
- TRY_CATCH (ex, RETURN_MASK_ERROR)
+ TRY
{
amd64_frame_cache_1 (this_frame, cache);
}
- if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
- throw_exception (ex);
+ CATCH (ex, RETURN_MASK_ERROR)
+ {
+ if (ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
+ }
+ END_CATCH
return cache;
}
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- volatile struct gdb_exception ex;
struct amd64_frame_cache *cache;
CORE_ADDR addr;
gdb_byte buf[8];
int i;
if (*this_cache)
- return *this_cache;
+ return (struct amd64_frame_cache *) *this_cache;
cache = amd64_alloc_frame_cache ();
- TRY_CATCH (ex, RETURN_MASK_ERROR)
+ TRY
{
get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
cache->base_p = 1;
}
- if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
- throw_exception (ex);
+ CATCH (ex, RETURN_MASK_ERROR)
+ {
+ if (ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
+ }
+ END_CATCH
*this_cache = cache;
return cache;
/* Normal frames, but in a function epilogue. */
-/* The epilogue is defined here as the 'ret' instruction, which will
+/* Implement the stack_frame_destroyed_p gdbarch method.
+
+ The epilogue is defined here as the 'ret' instruction, which will
follow any instruction such as 'leave' or 'pop %ebp' that destroys
the function's stack frame. */
static int
-amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
gdb_byte insn;
struct compunit_symtab *cust;
void **this_prologue_cache)
{
if (frame_relative_level (this_frame) == 0)
- return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
- get_frame_pc (this_frame));
+ return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
+ get_frame_pc (this_frame));
else
return 0;
}
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- volatile struct gdb_exception ex;
struct amd64_frame_cache *cache;
gdb_byte buf[8];
if (*this_cache)
- return *this_cache;
+ return (struct amd64_frame_cache *) *this_cache;
cache = amd64_alloc_frame_cache ();
*this_cache = cache;
- TRY_CATCH (ex, RETURN_MASK_ERROR)
+ TRY
{
/* Cache base will be %esp plus cache->sp_offset (-8). */
get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
cache->base_p = 1;
}
- if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
- throw_exception (ex);
+ CATCH (ex, RETURN_MASK_ERROR)
+ {
+ if (ex.error != NOT_AVAILABLE_ERROR)
+ throw_exception (ex);
+ }
+ END_CATCH
return cache;
}
amd64_pseudo_register_read_value);
set_gdbarch_pseudo_register_write (gdbarch,
amd64_pseudo_register_write);
+ set_gdbarch_ax_pseudo_register_collect (gdbarch,
+ amd64_ax_pseudo_register_collect);
set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
set_gdbarch_ptr_bit (gdbarch, 32);
}
+/* Return the target description for a specified XSAVE feature mask. */
+
+const struct target_desc *
+amd64_target_description (uint64_t xcr0)
+{
+ switch (xcr0 & X86_XSTATE_ALL_MASK)
+ {
+ case X86_XSTATE_MPX_AVX512_MASK:
+ case X86_XSTATE_AVX512_MASK:
+ return tdesc_amd64_avx512;
+ case X86_XSTATE_MPX_MASK:
+ return tdesc_amd64_mpx;
+ case X86_XSTATE_AVX_MASK:
+ return tdesc_amd64_avx;
+ default:
+ return tdesc_amd64;
+ }
+}
+
/* Provide a prototype to silence -Wmissing-prototypes. */
void _initialize_amd64_tdep (void);
if (fxsave
&& gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
{
- const gdb_byte *regs = fxsave;
+ const gdb_byte *regs = (const gdb_byte *) fxsave;
if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
if (xsave
&& gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
{
- const gdb_byte *regs = xsave;
+ const gdb_byte *regs = (const gdb_byte *) xsave;
if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- gdb_byte *regs = fxsave;
+ gdb_byte *regs = (gdb_byte *) fxsave;
i387_collect_fxsave (regcache, regnum, fxsave);
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- gdb_byte *regs = xsave;
+ gdb_byte *regs = (gdb_byte *) xsave;
i387_collect_xsave (regcache, regnum, xsave, gcore);
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