-/* Target dependent code for ARC arhitecture, for GDB.
+/* Target dependent code for ARC architecture, for GDB.
Copyright 2005-2019 Free Software Foundation, Inc.
Contributed by Synopsys Inc.
/* ARC header files. */
#include "opcode/arc.h"
-#include "../opcodes/arc-dis.h"
+#include "opcodes/arc-dis.h"
#include "arc-tdep.h"
/* Standard headers. */
/* Get register with base address of memory operation. */
-int
+static int
arc_insn_get_memory_base_reg (const struct arc_instruction &insn)
{
/* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */
/* Get offset of a memory operation INSN. */
-CORE_ADDR
+static CORE_ADDR
arc_insn_get_memory_offset (const struct arc_instruction &insn)
{
/* POP_S and PUSH_S have offset as an implicit argument in a
/* Dump INSN into gdb_stdlog. */
-void
+static void
arc_insn_dump (const struct arc_instruction &insn)
{
struct gdbarch *gdbarch = target_gdbarch ();
/* Store of some register. May or may not update base address register. */
if (insn.insn_class == STORE || insn.insn_class == PUSH)
{
- /* There is definetely at least one operand - register/value being
+ /* There is definitely at least one operand - register/value being
stored. */
gdb_assert (insn.operands_count > 0);
If CACHE is not NULL, then it will be filled with information about saved
registers.
- There are several variations of prologue which GDB may encouter. "Full"
+ There are several variations of prologue which GDB may encounter. "Full"
prologue looks like this:
sub sp,sp,<imm> ; Space for variadic arguments.
store, that doesn't update SP. Like this:
- sub sp,sp,8 ; Create space for calee-saved registers.
+ sub sp,sp,8 ; Create space for callee-saved registers.
st r13,[sp,4] ; Store callee saved registers (up to R26/GP).
st r14,[sp,0]
int
arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info)
{
- /* Standard BFD "machine number" field allows libocodes disassembler to
+ /* Standard BFD "machine number" field allows libopcodes disassembler to
distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM
and HS, which have some difference between. There are two ways to specify
what is the target core:
Returns TRUE if input tdesc was valid and in this case it will assign TDESC
and TDESC_DATA output parameters. */
-static int
+static bool
arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
struct tdesc_arch_data **tdesc_data)
{
{
arc_print (_("Error: ARC v2 target description supplied for "
"non-ARCv2 target.\n"));
- return FALSE;
+ return false;
}
is_reduced_rf = false;
{
arc_print (_("Error: ARC v2 target description supplied for "
"non-ARCv2 target.\n"));
- return FALSE;
+ return false;
}
is_reduced_rf = true;
{
arc_print (_("Error: ARCompact target description supplied "
"for non-ARCompact target.\n"));
- return FALSE;
+ return false;
}
is_reduced_rf = false;
{
arc_print (_("Error: Couldn't find core register feature in "
"supplied target description."));
- return FALSE;
+ return false;
}
}
}
arc_print (_("Error: Cannot find required register `%s' in "
"feature `%s'.\n"), core_regs[i], core_feature_name);
tdesc_data_cleanup (tdesc_data_loc);
- return FALSE;
+ return false;
}
}
- /* Mandatory AUX registeres are intentionally few and are common between
+ /* Mandatory AUX registers are intentionally few and are common between
ARCompact and ARC v2, so same code can be used for both. */
feature = tdesc_find_feature (tdesc_loc, aux_minimal_feature_name);
if (feature == NULL)
arc_print (_("Error: Cannot find required feature `%s' in supplied "
"target description.\n"), aux_minimal_feature_name);
tdesc_data_cleanup (tdesc_data_loc);
- return FALSE;
+ return false;
}
for (int i = ARC_FIRST_AUX_REGNUM; i <= ARC_LAST_AUX_REGNUM; i++)
"in feature `%s'.\n"),
name, tdesc_feature_name (feature));
tdesc_data_cleanup (tdesc_data_loc);
- return FALSE;
+ return false;
}
}
*tdesc = tdesc_loc;
*tdesc_data = tdesc_data_loc;
- return TRUE;
+ return true;
}
/* Implement the type_align gdbarch function. */