/* Common target-dependent functionality for RISC-V
- Copyright (C) 2018 Free Software Foundation, Inc.
+ Copyright (C) 2018-2020 Free Software Foundation, Inc.
This file is part of GDB.
#ifndef ARCH_RISCV_H
#define ARCH_RISCV_H
-#include "common/tdesc.h"
+#include "gdbsupport/tdesc.h"
/* The set of RISC-V architectural features that we track that impact how
we configure the actual gdbarch instance. We hold one of these in the
that there are no f-registers. No other value is valid. */
int flen = 0;
- /* This indicates if hardware floating point abi is in use. If the FLEN
- field is 0 then this value _must_ be false. If the FLEN field is
- non-zero and this field is false then this indicates the target has
- floating point registers, but is still using the soft-float abi. If
- this field is true then the hardware floating point abi is in use, and
- values are passed in f-registers matching the size of FLEN. */
- bool hw_float_abi = false;
+ /* Equality operator. */
+ bool operator== (const struct riscv_gdbarch_features &rhs) const
+ {
+ return (xlen == rhs.xlen && flen == rhs.flen);
+ }
+
+ /* Inequality operator. */
+ bool operator!= (const struct riscv_gdbarch_features &rhs) const
+ {
+ return !((*this) == rhs);
+ }
+
+ /* Used by std::unordered_map to hash feature sets. */
+ std::size_t hash () const noexcept
+ {
+ std::size_t val = ((xlen & 0x1f) << 5 | (flen & 0x1f) << 0);
+ return val;
+ }
};
/* Create and return a target description that is compatible with