Introduce switch_to_inferior_no_thread

[deliverable/binutils-gdb.git] / gdb / arch / riscv.h

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index be41828eff67a1f5af59ad08e970b9706e76f0cf..016a5fcd2f0ee31a151e0b3e37e8fe4676608fa2 100644 (file)
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -1,6 +1,6 @@
 /* Common target-dependent functionality for RISC-V
 
-   Copyright (C) 2018 Free Software Foundation, Inc.
+   Copyright (C) 2018-2020 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -20,7 +20,7 @@
 #ifndef ARCH_RISCV_H
 #define ARCH_RISCV_H
 
-#include "common/tdesc.h"
+#include "gdbsupport/tdesc.h"
 
 /* The set of RISC-V architectural features that we track that impact how
    we configure the actual gdbarch instance.  We hold one of these in the
@@ -46,19 +46,10 @@ struct riscv_gdbarch_features
      that there are no f-registers.  No other value is valid.  */
   int flen = 0;
 
-  /* This indicates if hardware floating point abi is in use.  If the FLEN
-     field is 0 then this value _must_ be false.  If the FLEN field is
-     non-zero and this field is false then this indicates the target has
-     floating point registers, but is still using the soft-float abi.  If
-     this field is true then the hardware floating point abi is in use, and
-     values are passed in f-registers matching the size of FLEN.  */
-  bool hw_float_abi = false;
-
   /* Equality operator.  */
   bool operator== (const struct riscv_gdbarch_features &rhs) const
   {
-    return (xlen == rhs.xlen && flen == rhs.flen
-           && hw_float_abi == rhs.hw_float_abi);
+    return (xlen == rhs.xlen && flen == rhs.flen);
   }
 
   /* Inequality operator.  */
@@ -66,6 +57,13 @@ struct riscv_gdbarch_features
   {
     return !((*this) == rhs);
   }
+
+  /* Used by std::unordered_map to hash feature sets.  */
+  std::size_t hash () const noexcept
+  {
+    std::size_t val = ((xlen & 0x1f) << 5 | (flen & 0x1f) << 0);
+    return val;
+  }
 };
 
 /* Create and return a target description that is compatible with