/* GNU/Linux on ARM native support.
- Copyright 1999 Free Software Foundation, Inc.
+ Copyright (C) 1999-2015 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "inferior.h"
#include "gdbcore.h"
-#include "gdb_string.h"
-
+#include "regcache.h"
+#include "target.h"
+#include "linux-nat.h"
+#include "target-descriptions.h"
+#include "auxv.h"
+#include "observer.h"
+#include "gdbthread.h"
+
+#include "arm-tdep.h"
+#include "arm-linux-tdep.h"
+#include "aarch32-linux-nat.h"
+
+#include <elf/common.h>
#include <sys/user.h>
-#include <sys/ptrace.h>
+#include "nat/gdb_ptrace.h"
#include <sys/utsname.h>
+#include <sys/procfs.h>
+
+#include "nat/linux-ptrace.h"
+
+/* Prototypes for supply_gregset etc. */
+#include "gregset.h"
+
+/* Defines ps_err_e, struct ps_prochandle. */
+#include "gdb_proc_service.h"
+
+#ifndef PTRACE_GET_THREAD_AREA
+#define PTRACE_GET_THREAD_AREA 22
+#endif
+
+#ifndef PTRACE_GETWMMXREGS
+#define PTRACE_GETWMMXREGS 18
+#define PTRACE_SETWMMXREGS 19
+#endif
+
+#ifndef PTRACE_GETVFPREGS
+#define PTRACE_GETVFPREGS 27
+#define PTRACE_SETVFPREGS 28
+#endif
+
+#ifndef PTRACE_GETHBPREGS
+#define PTRACE_GETHBPREGS 29
+#define PTRACE_SETHBPREGS 30
+#endif
extern int arm_apcs_32;
-#define typeNone 0x00
-#define typeSingle 0x01
-#define typeDouble 0x02
-#define typeExtended 0x03
-#define FPWORDS 28
-#define CPSR_REGNUM 16
-
-typedef union tagFPREG
- {
- unsigned int fSingle;
- unsigned int fDouble[2];
- unsigned int fExtended[3];
- }
-FPREG;
-
-typedef struct tagFPA11
- {
- FPREG fpreg[8]; /* 8 floating point registers */
- unsigned int fpsr; /* floating point status register */
- unsigned int fpcr; /* floating point control register */
- unsigned char fType[8]; /* type of floating point value held in
- floating point registers. */
- int initflag; /* NWFPE initialization flag. */
- }
-FPA11;
-
-/* The following variables are used to determine the version of the
- underlying Linux operating system. Examples:
-
- Linux 2.0.35 Linux 2.2.12
- os_version = 0x00020023 os_version = 0x0002020c
- os_major = 2 os_major = 2
- os_minor = 0 os_minor = 2
- os_release = 35 os_release = 12
-
- Note: os_version = (os_major << 16) | (os_minor << 8) | os_release
-
- These are initialized using get_linux_version() from
- _initialize_arm_linux_nat(). */
-
-static unsigned int os_version, os_major, os_minor, os_release;
+/* Get the whole floating point state of the process and store it
+ into regcache. */
static void
-fetch_nw_fpe_single (unsigned int fn, FPA11 * fpa11, unsigned int *pmem)
+fetch_fpregs (struct regcache *regcache)
{
- unsigned int mem[3];
+ int ret, regno, tid;
+ gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE];
- mem[0] = fpa11->fpreg[fn].fSingle;
- mem[1] = 0;
- mem[2] = 0;
- supply_register (F0_REGNUM + fn, (char *) &mem[0]);
-}
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
-static void
-fetch_nw_fpe_double (unsigned int fn, FPA11 * fpa11, unsigned int *pmem)
-{
- unsigned int mem[3];
+ /* Read the floating point state. */
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
- mem[0] = fpa11->fpreg[fn].fDouble[1];
- mem[1] = fpa11->fpreg[fn].fDouble[0];
- mem[2] = 0;
- supply_register (F0_REGNUM + fn, (char *) &mem[0]);
-}
+ iov.iov_base = &fp;
+ iov.iov_len = ARM_LINUX_SIZEOF_NWFPE;
-static void
-fetch_nw_fpe_none (unsigned int fn, FPA11 * fpa11, unsigned int *pmem)
-{
- unsigned int mem[3] =
- {0, 0, 0};
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov);
+ }
+ else
+ ret = ptrace (PT_GETFPREGS, tid, 0, fp);
- supply_register (F0_REGNUM + fn, (char *) &mem[0]);
-}
+ if (ret < 0)
+ {
+ warning (_("Unable to fetch the floating point registers."));
+ return;
+ }
-static void
-fetch_nw_fpe_extended (unsigned int fn, FPA11 * fpa11, unsigned int *pmem)
-{
- unsigned int mem[3];
+ /* Fetch fpsr. */
+ regcache_raw_supply (regcache, ARM_FPS_REGNUM,
+ fp + NWFPE_FPSR_OFFSET);
- mem[0] = fpa11->fpreg[fn].fExtended[0]; /* sign & exponent */
- mem[1] = fpa11->fpreg[fn].fExtended[2]; /* ls bits */
- mem[2] = fpa11->fpreg[fn].fExtended[1]; /* ms bits */
- supply_register (F0_REGNUM + fn, (char *) &mem[0]);
+ /* Fetch the floating point registers. */
+ for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
+ supply_nwfpe_register (regcache, regno, fp);
}
+/* Save the whole floating point state of the process using
+ the contents from regcache. */
+
static void
-store_nw_fpe_single (unsigned int fn, FPA11 * fpa11)
+store_fpregs (const struct regcache *regcache)
{
- unsigned int mem[3];
+ int ret, regno, tid;
+ gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE];
+
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
+
+ /* Read the floating point state. */
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ elf_fpregset_t fpregs;
+ struct iovec iov;
+
+ iov.iov_base = &fpregs;
+ iov.iov_len = sizeof (fpregs);
+
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov);
+ }
+ else
+ ret = ptrace (PT_GETFPREGS, tid, 0, fp);
+
+ if (ret < 0)
+ {
+ warning (_("Unable to fetch the floating point registers."));
+ return;
+ }
+
+ /* Store fpsr. */
+ if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM))
+ regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET);
+
+ /* Store the floating point registers. */
+ for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
+ if (REG_VALID == regcache_register_status (regcache, regno))
+ collect_nwfpe_register (regcache, regno, fp);
+
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
+
+ iov.iov_base = &fp;
+ iov.iov_len = ARM_LINUX_SIZEOF_NWFPE;
+
+ ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp);
- read_register_gen (F0_REGNUM + fn, (char *) &mem[0]);
- fpa11->fpreg[fn].fSingle = mem[0];
- fpa11->fType[fn] = typeSingle;
+ if (ret < 0)
+ {
+ warning (_("Unable to store floating point registers."));
+ return;
+ }
}
+/* Fetch all general registers of the process and store into
+ regcache. */
+
static void
-store_nw_fpe_double (unsigned int fn, FPA11 * fpa11)
+fetch_regs (struct regcache *regcache)
{
- unsigned int mem[3];
+ int ret, regno, tid;
+ elf_gregset_t regs;
- read_register_gen (F0_REGNUM + fn, (char *) &mem[0]);
- fpa11->fpreg[fn].fDouble[1] = mem[0];
- fpa11->fpreg[fn].fDouble[0] = mem[1];
- fpa11->fType[fn] = typeDouble;
-}
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
-void
-store_nw_fpe_extended (unsigned int fn, FPA11 * fpa11)
-{
- unsigned int mem[3];
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
- read_register_gen (F0_REGNUM + fn, (char *) &mem[0]);
- fpa11->fpreg[fn].fExtended[0] = mem[0]; /* sign & exponent */
- fpa11->fpreg[fn].fExtended[2] = mem[1]; /* ls bits */
- fpa11->fpreg[fn].fExtended[1] = mem[2]; /* ms bits */
- fpa11->fType[fn] = typeDouble;
-}
+ iov.iov_base = ®s;
+ iov.iov_len = sizeof (regs);
-/* Get the whole floating point state of the process and store the
- floating point stack into registers[]. */
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_GETREGS, tid, 0, ®s);
+
+ if (ret < 0)
+ {
+ warning (_("Unable to fetch general registers."));
+ return;
+ }
+
+ aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32);
+}
static void
-fetch_fpregs (void)
+store_regs (const struct regcache *regcache)
{
- int ret, regno;
- FPA11 fp;
+ int ret, regno, tid;
+ elf_gregset_t regs;
+
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
+
+ /* Fetch the general registers. */
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
+
+ iov.iov_base = ®s;
+ iov.iov_len = sizeof (regs);
+
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_GETREGS, tid, 0, ®s);
- /* Read the floating point state. */
- ret = ptrace (PT_GETFPREGS, inferior_pid, 0, &fp);
if (ret < 0)
{
- warning ("Unable to fetch the floating point state.");
+ warning (_("Unable to fetch general registers."));
return;
}
- /* Fetch fpsr. */
- supply_register (FPS_REGNUM, (char *) &fp.fpsr);
+ aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32);
- /* Fetch the floating point registers. */
- for (regno = F0_REGNUM; regno <= F7_REGNUM; regno++)
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
{
- int fn = regno - F0_REGNUM;
- unsigned int *p = (unsigned int *) ®isters[REGISTER_BYTE (regno)];
+ struct iovec iov;
- switch (fp.fType[fn])
- {
- case typeSingle:
- fetch_nw_fpe_single (fn, &fp, p);
- break;
-
- case typeDouble:
- fetch_nw_fpe_double (fn, &fp, p);
- break;
+ iov.iov_base = ®s;
+ iov.iov_len = sizeof (regs);
- case typeExtended:
- fetch_nw_fpe_extended (fn, &fp, p);
- break;
+ ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_SETREGS, tid, 0, ®s);
- default:
- fetch_nw_fpe_none (fn, &fp, p);
- }
+ if (ret < 0)
+ {
+ warning (_("Unable to store general registers."));
+ return;
}
}
-/* Save the whole floating point state of the process using
- the contents from registers[]. */
+/* Fetch all WMMX registers of the process and store into
+ regcache. */
+
+#define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4)
static void
-store_fpregs (void)
+fetch_wmmx_regs (struct regcache *regcache)
{
- int ret, regno;
- unsigned int mem[3];
- FPA11 fp;
+ char regbuf[IWMMXT_REGS_SIZE];
+ int ret, regno, tid;
- /* Store fpsr. */
- if (register_valid[FPS_REGNUM])
- read_register_gen (FPS_REGNUM, (char *) &fp.fpsr);
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
- /* Store the floating point registers. */
- for (regno = F0_REGNUM; regno <= F7_REGNUM; regno++)
+ ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf);
+ if (ret < 0)
{
- if (register_valid[regno])
- {
- unsigned int fn = regno - F0_REGNUM;
- switch (fp.fType[fn])
- {
- case typeSingle:
- store_nw_fpe_single (fn, &fp);
- break;
-
- case typeDouble:
- store_nw_fpe_double (fn, &fp);
- break;
-
- case typeExtended:
- store_nw_fpe_extended (fn, &fp);
- break;
- }
- }
+ warning (_("Unable to fetch WMMX registers."));
+ return;
}
- ret = ptrace (PTRACE_SETFPREGS, inferior_pid, 0, &fp);
+ for (regno = 0; regno < 16; regno++)
+ regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM,
+ ®buf[regno * 8]);
+
+ for (regno = 0; regno < 2; regno++)
+ regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM,
+ ®buf[16 * 8 + regno * 4]);
+
+ for (regno = 0; regno < 4; regno++)
+ regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM,
+ ®buf[16 * 8 + 2 * 4 + regno * 4]);
+}
+
+static void
+store_wmmx_regs (const struct regcache *regcache)
+{
+ char regbuf[IWMMXT_REGS_SIZE];
+ int ret, regno, tid;
+
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
+
+ ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf);
if (ret < 0)
{
- warning ("Unable to store floating point state.");
+ warning (_("Unable to fetch WMMX registers."));
return;
}
-}
-/* Fetch all general registers of the process and store into
- registers[]. */
+ for (regno = 0; regno < 16; regno++)
+ if (REG_VALID == regcache_register_status (regcache,
+ regno + ARM_WR0_REGNUM))
+ regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM,
+ ®buf[regno * 8]);
-static void
-fetch_regs (void)
-{
- int ret, regno;
- struct pt_regs regs;
+ for (regno = 0; regno < 2; regno++)
+ if (REG_VALID == regcache_register_status (regcache,
+ regno + ARM_WCSSF_REGNUM))
+ regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM,
+ ®buf[16 * 8 + regno * 4]);
+
+ for (regno = 0; regno < 4; regno++)
+ if (REG_VALID == regcache_register_status (regcache,
+ regno + ARM_WCGR0_REGNUM))
+ regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM,
+ ®buf[16 * 8 + 2 * 4 + regno * 4]);
+
+ ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf);
- ret = ptrace (PTRACE_GETREGS, inferior_pid, 0, ®s);
if (ret < 0)
{
- warning ("Unable to fetch general registers.");
+ warning (_("Unable to store WMMX registers."));
return;
}
+}
- for (regno = A1_REGNUM; regno < PC_REGNUM; regno++)
- supply_register (regno, (char *) ®s.uregs[regno]);
+static void
+fetch_vfp_regs (struct regcache *regcache)
+{
+ gdb_byte regbuf[VFP_REGS_SIZE];
+ int ret, regno, tid;
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
- if (arm_apcs_32)
- supply_register (PS_REGNUM, (char *) ®s.uregs[CPSR_REGNUM]);
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
+
+ iov.iov_base = regbuf;
+ iov.iov_len = VFP_REGS_SIZE;
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
+ }
else
- supply_register (PS_REGNUM, (char *) ®s.uregs[PC_REGNUM]);
+ ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf);
- regs.uregs[PC_REGNUM] = ADDR_BITS_REMOVE (regs.uregs[PC_REGNUM]);
- supply_register (PC_REGNUM, (char *) ®s.uregs[PC_REGNUM]);
-}
+ if (ret < 0)
+ {
+ warning (_("Unable to fetch VFP registers."));
+ return;
+ }
-/* Store all general registers of the process from the values in
- registers[]. */
+ aarch32_vfp_regcache_supply (regcache, regbuf,
+ tdep->vfp_register_count);
+}
static void
-store_regs (void)
+store_vfp_regs (const struct regcache *regcache)
{
- int ret, regno;
- struct pt_regs regs;
+ gdb_byte regbuf[VFP_REGS_SIZE];
+ int ret, regno, tid;
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* Get the thread id for the ptrace call. */
+ tid = ptid_get_lwp (inferior_ptid);
+
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
+ {
+ struct iovec iov;
+
+ iov.iov_base = regbuf;
+ iov.iov_len = VFP_REGS_SIZE;
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf);
- ret = ptrace (PTRACE_GETREGS, inferior_pid, 0, ®s);
if (ret < 0)
{
- warning ("Unable to fetch general registers.");
+ warning (_("Unable to fetch VFP registers (for update)."));
return;
}
- for (regno = A1_REGNUM; regno <= PC_REGNUM; regno++)
+ aarch32_vfp_regcache_collect (regcache, regbuf,
+ tdep->vfp_register_count);
+
+ if (have_ptrace_getregset == TRIBOOL_TRUE)
{
- if (register_valid[regno])
- read_register_gen (regno, (char *) ®s.uregs[regno]);
- }
+ struct iovec iov;
- ret = ptrace (PTRACE_SETREGS, inferior_pid, 0, ®s);
+ iov.iov_base = regbuf;
+ iov.iov_len = VFP_REGS_SIZE;
+ ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov);
+ }
+ else
+ ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf);
if (ret < 0)
{
- warning ("Unable to store general registers.");
+ warning (_("Unable to store VFP registers."));
return;
}
}
regno == -1, otherwise fetch all general registers or all floating
point registers depending upon the value of regno. */
-void
-fetch_inferior_registers (int regno)
+static void
+arm_linux_fetch_inferior_registers (struct target_ops *ops,
+ struct regcache *regcache, int regno)
{
- if ((regno < F0_REGNUM) || (regno > FPS_REGNUM))
- fetch_regs ();
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (((regno >= F0_REGNUM) && (regno <= FPS_REGNUM)) || (regno == -1))
- fetch_fpregs ();
+ if (-1 == regno)
+ {
+ fetch_regs (regcache);
+ fetch_fpregs (regcache);
+ if (tdep->have_wmmx_registers)
+ fetch_wmmx_regs (regcache);
+ if (tdep->vfp_register_count > 0)
+ fetch_vfp_regs (regcache);
+ }
+ else
+ {
+ if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
+ fetch_regs (regcache);
+ else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM)
+ fetch_fpregs (regcache);
+ else if (tdep->have_wmmx_registers
+ && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM)
+ fetch_wmmx_regs (regcache);
+ else if (tdep->vfp_register_count > 0
+ && regno >= ARM_D0_REGNUM
+ && regno <= ARM_D0_REGNUM + tdep->vfp_register_count)
+ fetch_vfp_regs (regcache);
+ }
}
/* Store registers back into the inferior. Store all registers if
regno == -1, otherwise store all general registers or all floating
point registers depending upon the value of regno. */
+static void
+arm_linux_store_inferior_registers (struct target_ops *ops,
+ struct regcache *regcache, int regno)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (-1 == regno)
+ {
+ store_regs (regcache);
+ store_fpregs (regcache);
+ if (tdep->have_wmmx_registers)
+ store_wmmx_regs (regcache);
+ if (tdep->vfp_register_count > 0)
+ store_vfp_regs (regcache);
+ }
+ else
+ {
+ if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
+ store_regs (regcache);
+ else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM))
+ store_fpregs (regcache);
+ else if (tdep->have_wmmx_registers
+ && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM)
+ store_wmmx_regs (regcache);
+ else if (tdep->vfp_register_count > 0
+ && regno >= ARM_D0_REGNUM
+ && regno <= ARM_D0_REGNUM + tdep->vfp_register_count)
+ store_vfp_regs (regcache);
+ }
+}
+
+/* Wrapper functions for the standard regset handling, used by
+ thread debugging. */
+
+void
+fill_gregset (const struct regcache *regcache,
+ gdb_gregset_t *gregsetp, int regno)
+{
+ arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0);
+}
+
+void
+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
+{
+ arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0);
+}
+
void
-store_inferior_registers (int regno)
+fill_fpregset (const struct regcache *regcache,
+ gdb_fpregset_t *fpregsetp, int regno)
{
- if ((regno < F0_REGNUM) || (regno > FPS_REGNUM))
- store_regs ();
+ arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0);
+}
+
+/* Fill GDB's register array with the floating-point register values
+ in *fpregsetp. */
- if (((regno >= F0_REGNUM) && (regno <= FPS_REGNUM)) || (regno == -1))
- store_fpregs ();
+void
+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+{
+ arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0);
}
-#ifdef GET_LONGJMP_TARGET
+/* Fetch the thread-local storage pointer for libthread_db. */
-/* Figure out where the longjmp will land. We expect that we have
- just entered longjmp and haven't yet altered r0, r1, so the
- arguments are still in the registers. (A1_REGNUM) points at the
- jmp_buf structure from which we extract the pc (JB_PC) that we will
- land at. The pc is copied into ADDR. This routine returns true on
- success. */
+ps_err_e
+ps_get_thread_area (const struct ps_prochandle *ph,
+ lwpid_t lwpid, int idx, void **base)
+{
+ if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
+ return PS_ERR;
-#define LONGJMP_TARGET_SIZE sizeof(int)
-#define JB_ELEMENT_SIZE sizeof(int)
-#define JB_SL 18
-#define JB_FP 19
-#define JB_SP 20
-#define JB_PC 21
+ /* IDX is the bias from the thread pointer to the beginning of the
+ thread descriptor. It has to be subtracted due to implementation
+ quirks in libthread_db. */
+ *base = (void *) ((char *)*base - idx);
-int
-arm_get_longjmp_target (CORE_ADDR * pc)
+ return PS_OK;
+}
+
+static const struct target_desc *
+arm_linux_read_description (struct target_ops *ops)
{
- CORE_ADDR jb_addr;
- char buf[LONGJMP_TARGET_SIZE];
+ CORE_ADDR arm_hwcap = 0;
+
+ if (have_ptrace_getregset == TRIBOOL_UNKNOWN)
+ {
+ elf_gregset_t gpregs;
+ struct iovec iov;
+ int tid = ptid_get_lwp (inferior_ptid);
+
+ iov.iov_base = &gpregs;
+ iov.iov_len = sizeof (gpregs);
+
+ /* Check if PTRACE_GETREGSET works. */
+ if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0)
+ have_ptrace_getregset = TRIBOOL_FALSE;
+ else
+ have_ptrace_getregset = TRIBOOL_TRUE;
+ }
- jb_addr = read_register (A1_REGNUM);
+ if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1)
+ {
+ return ops->beneath->to_read_description (ops->beneath);
+ }
- if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
- LONGJMP_TARGET_SIZE))
- return 0;
+ if (arm_hwcap & HWCAP_IWMMXT)
+ return tdesc_arm_with_iwmmxt;
+
+ if (arm_hwcap & HWCAP_VFP)
+ {
+ int pid;
+ char *buf;
+ const struct target_desc * result = NULL;
+
+ /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support
+ Neon with VFPv3-D32. */
+ if (arm_hwcap & HWCAP_NEON)
+ result = tdesc_arm_with_neon;
+ else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
+ result = tdesc_arm_with_vfpv3;
+ else
+ result = tdesc_arm_with_vfpv2;
+
+ /* Now make sure that the kernel supports reading these
+ registers. Support was added in 2.6.30. */
+ pid = ptid_get_lwp (inferior_ptid);
+ errno = 0;
+ buf = alloca (VFP_REGS_SIZE);
+ if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
+ && errno == EIO)
+ result = NULL;
+
+ return result;
+ }
+
+ return ops->beneath->to_read_description (ops->beneath);
+}
+
+/* Information describing the hardware breakpoint capabilities. */
+struct arm_linux_hwbp_cap
+{
+ gdb_byte arch;
+ gdb_byte max_wp_length;
+ gdb_byte wp_count;
+ gdb_byte bp_count;
+};
+
+/* Since we cannot dynamically allocate subfields of arm_linux_process_info,
+ assume a maximum number of supported break-/watchpoints. */
+#define MAX_BPTS 16
+#define MAX_WPTS 16
+
+/* Get hold of the Hardware Breakpoint information for the target we are
+ attached to. Returns NULL if the kernel doesn't support Hardware
+ breakpoints at all, or a pointer to the information structure. */
+static const struct arm_linux_hwbp_cap *
+arm_linux_get_hwbp_cap (void)
+{
+ /* The info structure we return. */
+ static struct arm_linux_hwbp_cap info;
+
+ /* Is INFO in a good state? -1 means that no attempt has been made to
+ initialize INFO; 0 means an attempt has been made, but it failed; 1
+ means INFO is in an initialized state. */
+ static int available = -1;
+
+ if (available == -1)
+ {
+ int tid;
+ unsigned int val;
+
+ tid = ptid_get_lwp (inferior_ptid);
+ if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0)
+ available = 0;
+ else
+ {
+ info.arch = (gdb_byte)((val >> 24) & 0xff);
+ info.max_wp_length = (gdb_byte)((val >> 16) & 0xff);
+ info.wp_count = (gdb_byte)((val >> 8) & 0xff);
+ info.bp_count = (gdb_byte)(val & 0xff);
+
+ if (info.wp_count > MAX_WPTS)
+ {
+ warning (_("arm-linux-gdb supports %d hardware watchpoints but target \
+ supports %d"), MAX_WPTS, info.wp_count);
+ info.wp_count = MAX_WPTS;
+ }
+
+ if (info.bp_count > MAX_BPTS)
+ {
+ warning (_("arm-linux-gdb supports %d hardware breakpoints but target \
+ supports %d"), MAX_BPTS, info.bp_count);
+ info.bp_count = MAX_BPTS;
+ }
+ available = (info.arch != 0);
+ }
+ }
+
+ return available == 1 ? &info : NULL;
+}
+
+/* How many hardware breakpoints are available? */
+static int
+arm_linux_get_hw_breakpoint_count (void)
+{
+ const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap ();
+ return cap != NULL ? cap->bp_count : 0;
+}
+
+/* How many hardware watchpoints are available? */
+static int
+arm_linux_get_hw_watchpoint_count (void)
+{
+ const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap ();
+ return cap != NULL ? cap->wp_count : 0;
+}
+
+/* Have we got a free break-/watch-point available for use? Returns -1 if
+ there is not an appropriate resource available, otherwise returns 1. */
+static int
+arm_linux_can_use_hw_breakpoint (struct target_ops *self,
+ enum bptype type,
+ int cnt, int ot)
+{
+ if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
+ || type == bp_access_watchpoint || type == bp_watchpoint)
+ {
+ int count = arm_linux_get_hw_watchpoint_count ();
+
+ if (count == 0)
+ return 0;
+ else if (cnt + ot > count)
+ return -1;
+ }
+ else if (type == bp_hardware_breakpoint)
+ {
+ int count = arm_linux_get_hw_breakpoint_count ();
+
+ if (count == 0)
+ return 0;
+ else if (cnt > count)
+ return -1;
+ }
+ else
+ gdb_assert (FALSE);
- *pc = extract_address (buf, LONGJMP_TARGET_SIZE);
return 1;
}
-#endif /* GET_LONGJMP_TARGET */
+/* Enum describing the different types of ARM hardware break-/watch-points. */
+typedef enum
+{
+ arm_hwbp_break = 0,
+ arm_hwbp_load = 1,
+ arm_hwbp_store = 2,
+ arm_hwbp_access = 3
+} arm_hwbp_type;
+
+/* Type describing an ARM Hardware Breakpoint Control register value. */
+typedef unsigned int arm_hwbp_control_t;
+
+/* Structure used to keep track of hardware break-/watch-points. */
+struct arm_linux_hw_breakpoint
+{
+ /* Address to break on, or being watched. */
+ unsigned int address;
+ /* Control register for break-/watch- point. */
+ arm_hwbp_control_t control;
+};
+
+/* Structure containing arrays of per process hardware break-/watchpoints
+ for caching address and control information.
+
+ The Linux ptrace interface to hardware break-/watch-points presents the
+ values in a vector centred around 0 (which is used fo generic information).
+ Positive indicies refer to breakpoint addresses/control registers, negative
+ indices to watchpoint addresses/control registers.
+
+ The Linux vector is indexed as follows:
+ -((i << 1) + 2): Control register for watchpoint i.
+ -((i << 1) + 1): Address register for watchpoint i.
+ 0: Information register.
+ ((i << 1) + 1): Address register for breakpoint i.
+ ((i << 1) + 2): Control register for breakpoint i.
+
+ This structure is used as a per-thread cache of the state stored by the
+ kernel, so that we don't need to keep calling into the kernel to find a
+ free breakpoint.
+
+ We treat break-/watch-points with their enable bit clear as being deleted.
+ */
+struct arm_linux_debug_reg_state
+{
+ /* Hardware breakpoints for this process. */
+ struct arm_linux_hw_breakpoint bpts[MAX_BPTS];
+ /* Hardware watchpoints for this process. */
+ struct arm_linux_hw_breakpoint wpts[MAX_WPTS];
+};
+
+/* Per-process arch-specific data we want to keep. */
+struct arm_linux_process_info
+{
+ /* Linked list. */
+ struct arm_linux_process_info *next;
+ /* The process identifier. */
+ pid_t pid;
+ /* Hardware break-/watchpoints state information. */
+ struct arm_linux_debug_reg_state state;
+
+};
+
+/* Per-thread arch-specific data we want to keep. */
+struct arch_lwp_info
+{
+ /* Non-zero if our copy differs from what's recorded in the thread. */
+ char bpts_changed[MAX_BPTS];
+ char wpts_changed[MAX_WPTS];
+};
+
+static struct arm_linux_process_info *arm_linux_process_list = NULL;
+
+/* Find process data for process PID. */
+
+static struct arm_linux_process_info *
+arm_linux_find_process_pid (pid_t pid)
+{
+ struct arm_linux_process_info *proc;
+
+ for (proc = arm_linux_process_list; proc; proc = proc->next)
+ if (proc->pid == pid)
+ return proc;
+
+ return NULL;
+}
+
+/* Add process data for process PID. Returns newly allocated info
+ object. */
+
+static struct arm_linux_process_info *
+arm_linux_add_process (pid_t pid)
+{
+ struct arm_linux_process_info *proc;
-/*
- Dynamic Linking on ARM Linux
- ----------------------------
+ proc = xcalloc (1, sizeof (*proc));
+ proc->pid = pid;
- Note: PLT = procedure linkage table
- GOT = global offset table
+ proc->next = arm_linux_process_list;
+ arm_linux_process_list = proc;
+
+ return proc;
+}
+
+/* Get data specific info for process PID, creating it if necessary.
+ Never returns NULL. */
+
+static struct arm_linux_process_info *
+arm_linux_process_info_get (pid_t pid)
+{
+ struct arm_linux_process_info *proc;
+
+ proc = arm_linux_find_process_pid (pid);
+ if (proc == NULL)
+ proc = arm_linux_add_process (pid);
+
+ return proc;
+}
+
+/* Called whenever GDB is no longer debugging process PID. It deletes
+ data structures that keep track of debug register state. */
+
+static void
+arm_linux_forget_process (pid_t pid)
+{
+ struct arm_linux_process_info *proc, **proc_link;
+
+ proc = arm_linux_process_list;
+ proc_link = &arm_linux_process_list;
+
+ while (proc != NULL)
+ {
+ if (proc->pid == pid)
+ {
+ *proc_link = proc->next;
+
+ xfree (proc);
+ return;
+ }
+
+ proc_link = &proc->next;
+ proc = *proc_link;
+ }
+}
+
+/* Get hardware break-/watchpoint state for process PID. */
+
+static struct arm_linux_debug_reg_state *
+arm_linux_get_debug_reg_state (pid_t pid)
+{
+ return &arm_linux_process_info_get (pid)->state;
+}
+
+/* Initialize an ARM hardware break-/watch-point control register value.
+ BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the
+ type of break-/watch-point; ENABLE indicates whether the point is enabled.
+ */
+static arm_hwbp_control_t
+arm_hwbp_control_initialize (unsigned byte_address_select,
+ arm_hwbp_type hwbp_type,
+ int enable)
+{
+ gdb_assert ((byte_address_select & ~0xffU) == 0);
+ gdb_assert (hwbp_type != arm_hwbp_break
+ || ((byte_address_select & 0xfU) != 0));
+
+ return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable;
+}
+
+/* Does the breakpoint control value CONTROL have the enable bit set? */
+static int
+arm_hwbp_control_is_enabled (arm_hwbp_control_t control)
+{
+ return control & 0x1;
+}
+
+/* Change a breakpoint control word so that it is in the disabled state. */
+static arm_hwbp_control_t
+arm_hwbp_control_disable (arm_hwbp_control_t control)
+{
+ return control & ~0x1;
+}
+
+/* Initialise the hardware breakpoint structure P. The breakpoint will be
+ enabled, and will point to the placed address of BP_TGT. */
+static void
+arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt,
+ struct arm_linux_hw_breakpoint *p)
+{
+ unsigned mask;
+ CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address;
+
+ /* We have to create a mask for the control register which says which bits
+ of the word pointed to by address to break on. */
+ if (arm_pc_is_thumb (gdbarch, address))
+ {
+ mask = 0x3;
+ address &= ~1;
+ }
+ else
+ {
+ mask = 0xf;
+ address &= ~3;
+ }
- As much as possible, ELF dynamic linking defers the resolution of
- jump/call addresses until the last minute. The technique used is
- inspired by the i386 ELF design, and is based on the following
- constraints.
+ p->address = (unsigned int) address;
+ p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1);
+}
- 1) The calling technique should not force a change in the assembly
- code produced for apps; it MAY cause changes in the way assembly
- code is produced for position independent code (i.e. shared
- libraries).
+/* Get the ARM hardware breakpoint type from the TYPE value we're
+ given when asked to set a watchpoint. */
+static arm_hwbp_type
+arm_linux_get_hwbp_type (enum target_hw_bp_type type)
+{
+ if (type == hw_read)
+ return arm_hwbp_load;
+ else if (type == hw_write)
+ return arm_hwbp_store;
+ else
+ return arm_hwbp_access;
+}
- 2) The technique must be such that all executable areas must not be
- modified; and any modified areas must not be executed.
+/* Initialize the hardware breakpoint structure P for a watchpoint at ADDR
+ to LEN. The type of watchpoint is given in RW. */
+static void
+arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct arm_linux_hw_breakpoint *p)
+{
+ const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap ();
+ unsigned mask;
- To do this, there are three steps involved in a typical jump:
+ gdb_assert (cap != NULL);
+ gdb_assert (cap->max_wp_length != 0);
- 1) in the code
- 2) through the PLT
- 3) using a pointer from the GOT
+ mask = (1 << len) - 1;
- When the executable or library is first loaded, each GOT entry is
- initialized to point to the code which implements dynamic name
- resolution and code finding. This is normally a function in the
- program interpreter (on ARM Linux this is usually ld-linux.so.2,
- but it does not have to be). On the first invocation, the function
- is located and the GOT entry is replaced with the real function
- address. Subsequent calls go through steps 1, 2 and 3 and end up
- calling the real code.
+ p->address = (unsigned int) addr;
+ p->control = arm_hwbp_control_initialize (mask,
+ arm_linux_get_hwbp_type (type), 1);
+}
- 1) In the code:
+/* Are two break-/watch-points equal? */
+static int
+arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1,
+ const struct arm_linux_hw_breakpoint *p2)
+{
+ return p1->address == p2->address && p1->control == p2->control;
+}
- b function_call
- bl function_call
+/* Callback to mark a watch-/breakpoint to be updated in all threads of
+ the current process. */
- This is typical ARM code using the 26 bit relative branch or branch
- and link instructions. The target of the instruction
- (function_call is usually the address of the function to be called.
- In position independent code, the target of the instruction is
- actually an entry in the PLT when calling functions in a shared
- library. Note that this call is identical to a normal function
- call, only the target differs.
+struct update_registers_data
+{
+ int watch;
+ int index;
+};
- 2) In the PLT:
+static int
+update_registers_callback (struct lwp_info *lwp, void *arg)
+{
+ struct update_registers_data *data = (struct update_registers_data *) arg;
- The PLT is a synthetic area, created by the linker. It exists in
- both executables and libraries. It is an array of stubs, one per
- imported function call. It looks like this:
+ if (lwp->arch_private == NULL)
+ lwp->arch_private = XCNEW (struct arch_lwp_info);
- PLT[0]:
- str lr, [sp, #-4]! @push the return address (lr)
- ldr lr, [pc, #16] @load from 6 words ahead
- add lr, pc, lr @form an address for GOT[0]
- ldr pc, [lr, #8]! @jump to the contents of that addr
+ /* The actual update is done later just before resuming the lwp,
+ we just mark that the registers need updating. */
+ if (data->watch)
+ lwp->arch_private->wpts_changed[data->index] = 1;
+ else
+ lwp->arch_private->bpts_changed[data->index] = 1;
- The return address (lr) is pushed on the stack and used for
- calculations. The load on the second line loads the lr with
- &GOT[3] - . - 20. The addition on the third leaves:
+ /* If the lwp isn't stopped, force it to momentarily pause, so
+ we can update its breakpoint registers. */
+ if (!lwp->stopped)
+ linux_stop_lwp (lwp);
- lr = (&GOT[3] - . - 20) + (. + 8)
- lr = (&GOT[3] - 12)
- lr = &GOT[0]
+ return 0;
+}
- On the fourth line, the pc and lr are both updated, so that:
+/* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT
+ =1) BPT for thread TID. */
+static void
+arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt,
+ int watchpoint)
+{
+ int pid;
+ ptid_t pid_ptid;
+ gdb_byte count, i;
+ struct arm_linux_hw_breakpoint* bpts;
+ struct update_registers_data data;
- pc = GOT[2]
- lr = &GOT[0] + 8
- = &GOT[2]
+ pid = ptid_get_pid (inferior_ptid);
+ pid_ptid = pid_to_ptid (pid);
- NOTE: PLT[0] borrows an offset .word from PLT[1]. This is a little
- "tight", but allows us to keep all the PLT entries the same size.
+ if (watchpoint)
+ {
+ count = arm_linux_get_hw_watchpoint_count ();
+ bpts = arm_linux_get_debug_reg_state (pid)->wpts;
+ }
+ else
+ {
+ count = arm_linux_get_hw_breakpoint_count ();
+ bpts = arm_linux_get_debug_reg_state (pid)->bpts;
+ }
- PLT[n+1]:
- ldr ip, [pc, #4] @load offset from gotoff
- add ip, pc, ip @add the offset to the pc
- ldr pc, [ip] @jump to that address
- gotoff: .word GOT[n+3] - .
+ for (i = 0; i < count; ++i)
+ if (!arm_hwbp_control_is_enabled (bpts[i].control))
+ {
+ data.watch = watchpoint;
+ data.index = i;
+ bpts[i] = *bpt;
+ iterate_over_lwps (pid_ptid, update_registers_callback, &data);
+ break;
+ }
+
+ gdb_assert (i != count);
+}
- The load on the first line, gets an offset from the fourth word of
- the PLT entry. The add on the second line makes ip = &GOT[n+3],
- which contains either a pointer to PLT[0] (the fixup trampoline) or
- a pointer to the actual code.
+/* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint
+ (WATCHPOINT = 1) BPT for thread TID. */
+static void
+arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt,
+ int watchpoint)
+{
+ int pid;
+ gdb_byte count, i;
+ ptid_t pid_ptid;
+ struct arm_linux_hw_breakpoint* bpts;
+ struct update_registers_data data;
- 3) In the GOT:
+ pid = ptid_get_pid (inferior_ptid);
+ pid_ptid = pid_to_ptid (pid);
- The GOT contains helper pointers for both code (PLT) fixups and
- data fixups. The first 3 entries of the GOT are special. The next
- M entries (where M is the number of entries in the PLT) belong to
- the PLT fixups. The next D (all remaining) entries belong to
- various data fixups. The actual size of the GOT is 3 + M + D.
+ if (watchpoint)
+ {
+ count = arm_linux_get_hw_watchpoint_count ();
+ bpts = arm_linux_get_debug_reg_state (pid)->wpts;
+ }
+ else
+ {
+ count = arm_linux_get_hw_breakpoint_count ();
+ bpts = arm_linux_get_debug_reg_state (pid)->bpts;
+ }
- The GOT is also a synthetic area, created by the linker. It exists
- in both executables and libraries. When the GOT is first
- initialized , all the GOT entries relating to PLT fixups are
- pointing to code back at PLT[0].
+ for (i = 0; i < count; ++i)
+ if (arm_linux_hw_breakpoint_equal (bpt, bpts + i))
+ {
+ data.watch = watchpoint;
+ data.index = i;
+ bpts[i].control = arm_hwbp_control_disable (bpts[i].control);
+ iterate_over_lwps (pid_ptid, update_registers_callback, &data);
+ break;
+ }
+
+ gdb_assert (i != count);
+}
- The special entries in the GOT are:
+/* Insert a Hardware breakpoint. */
+static int
+arm_linux_insert_hw_breakpoint (struct target_ops *self,
+ struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+{
+ struct lwp_info *lp;
+ struct arm_linux_hw_breakpoint p;
- GOT[0] = linked list pointer used by the dynamic loader
- GOT[1] = pointer to the reloc table for this module
- GOT[2] = pointer to the fixup/resolver code
+ if (arm_linux_get_hw_breakpoint_count () == 0)
+ return -1;
- The first invocation of function call comes through and uses the
- fixup/resolver code. On the entry to the fixup/resolver code:
+ arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p);
- ip = &GOT[n+3]
- lr = &GOT[2]
- stack[0] = return address (lr) of the function call
- [r0, r1, r2, r3] are still the arguments to the function call
+ arm_linux_insert_hw_breakpoint1 (&p, 0);
- This is enough information for the fixup/resolver code to work
- with. Before the fixup/resolver code returns, it actually calls
- the requested function and repairs &GOT[n+3]. */
+ return 0;
+}
-CORE_ADDR
-arm_skip_solib_resolver (CORE_ADDR pc)
+/* Remove a hardware breakpoint. */
+static int
+arm_linux_remove_hw_breakpoint (struct target_ops *self,
+ struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
{
- /* FIXME */
+ struct lwp_info *lp;
+ struct arm_linux_hw_breakpoint p;
+
+ if (arm_linux_get_hw_breakpoint_count () == 0)
+ return -1;
+
+ arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p);
+
+ arm_linux_remove_hw_breakpoint1 (&p, 0);
+
return 0;
}
-int
-arm_linux_register_u_addr (int blockend, int regnum)
+/* Are we able to use a hardware watchpoint for the LEN bytes starting at
+ ADDR? */
+static int
+arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
+ CORE_ADDR addr, int len)
{
- return blockend + REGISTER_BYTE (regnum);
+ const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap ();
+ CORE_ADDR max_wp_length, aligned_addr;
+
+ /* Can not set watchpoints for zero or negative lengths. */
+ if (len <= 0)
+ return 0;
+
+ /* Need to be able to use the ptrace interface. */
+ if (cap == NULL || cap->wp_count == 0)
+ return 0;
+
+ /* Test that the range [ADDR, ADDR + LEN) fits into the largest address
+ range covered by a watchpoint. */
+ max_wp_length = (CORE_ADDR)cap->max_wp_length;
+ aligned_addr = addr & ~(max_wp_length - 1);
+
+ if (aligned_addr + max_wp_length < addr + len)
+ return 0;
+
+ /* The current ptrace interface can only handle watchpoints that are a
+ power of 2. */
+ if ((len & (len - 1)) != 0)
+ return 0;
+
+ /* All tests passed so we must be able to set a watchpoint. */
+ return 1;
}
-int
-arm_linux_kernel_u_size (void)
+/* Insert a Hardware breakpoint. */
+static int
+arm_linux_insert_watchpoint (struct target_ops *self,
+ CORE_ADDR addr, int len,
+ enum target_hw_bp_type rw,
+ struct expression *cond)
{
- return (sizeof (struct user));
+ struct lwp_info *lp;
+ struct arm_linux_hw_breakpoint p;
+
+ if (arm_linux_get_hw_watchpoint_count () == 0)
+ return -1;
+
+ arm_linux_hw_watchpoint_initialize (addr, len, rw, &p);
+
+ arm_linux_insert_hw_breakpoint1 (&p, 1);
+
+ return 0;
}
-/* Extract from an array REGBUF containing the (raw) register state
- a function return value of type TYPE, and copy that, in virtual format,
- into VALBUF. */
+/* Remove a hardware breakpoint. */
+static int
+arm_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr,
+ int len, enum target_hw_bp_type rw,
+ struct expression *cond)
+{
+ struct lwp_info *lp;
+ struct arm_linux_hw_breakpoint p;
-void
-arm_linux_extract_return_value (struct type *type,
- char regbuf[REGISTER_BYTES],
- char *valbuf)
+ if (arm_linux_get_hw_watchpoint_count () == 0)
+ return -1;
+
+ arm_linux_hw_watchpoint_initialize (addr, len, rw, &p);
+
+ arm_linux_remove_hw_breakpoint1 (&p, 1);
+
+ return 0;
+}
+
+/* What was the data address the target was stopped on accessing. */
+static int
+arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
+{
+ siginfo_t siginfo;
+ int slot;
+
+ if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
+ return 0;
+
+ /* This must be a hardware breakpoint. */
+ if (siginfo.si_signo != SIGTRAP
+ || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+ return 0;
+
+ /* We must be able to set hardware watchpoints. */
+ if (arm_linux_get_hw_watchpoint_count () == 0)
+ return 0;
+
+ slot = siginfo.si_errno;
+
+ /* If we are in a positive slot then we're looking at a breakpoint and not
+ a watchpoint. */
+ if (slot >= 0)
+ return 0;
+
+ *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
+ return 1;
+}
+
+/* Has the target been stopped by hitting a watchpoint? */
+static int
+arm_linux_stopped_by_watchpoint (struct target_ops *ops)
{
- /* ScottB: This needs to be looked at to handle the different
- floating point emulators on ARM Linux. Right now the code
- assumes that fetch inferior registers does the right thing for
- GDB. I suspect this won't handle NWFPE registers correctly, nor
- will the default ARM version (arm_extract_return_value()). */
+ CORE_ADDR addr;
+ return arm_linux_stopped_data_address (ops, &addr);
+}
- int regnum = (TYPE_CODE_FLT == TYPE_CODE (type)) ? F0_REGNUM : A1_REGNUM;
- memcpy (valbuf, ®buf[REGISTER_BYTE (regnum)], TYPE_LENGTH (type));
+static int
+arm_linux_watchpoint_addr_within_range (struct target_ops *target,
+ CORE_ADDR addr,
+ CORE_ADDR start, int length)
+{
+ return start <= addr && start + length - 1 >= addr;
}
-static unsigned int
-get_linux_version (unsigned int *vmajor,
- unsigned int *vminor,
- unsigned int *vrelease)
+/* Handle thread creation. We need to copy the breakpoints and watchpoints
+ in the parent thread to the child thread. */
+static void
+arm_linux_new_thread (struct lwp_info *lp)
{
- struct utsname info;
- char *pmajor, *pminor, *prelease, *tail;
+ int i;
+ struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
+
+ /* Mark that all the hardware breakpoint/watchpoint register pairs
+ for this thread need to be initialized. */
- if (-1 == uname (&info))
+ for (i = 0; i < MAX_BPTS; i++)
{
- warning ("Unable to determine Linux version.");
- return -1;
+ info->bpts_changed[i] = 1;
+ info->wpts_changed[i] = 1;
}
- pmajor = strtok (info.release, ".");
- pminor = strtok (NULL, ".");
- prelease = strtok (NULL, ".");
+ lp->arch_private = info;
+}
- *vmajor = (unsigned int) strtoul (pmajor, &tail, 0);
- *vminor = (unsigned int) strtoul (pminor, &tail, 0);
- *vrelease = (unsigned int) strtoul (prelease, &tail, 0);
+/* Called when resuming a thread.
+ The hardware debug registers are updated when there is any change. */
- return ((*vmajor << 16) | (*vminor << 8) | *vrelease);
+static void
+arm_linux_prepare_to_resume (struct lwp_info *lwp)
+{
+ int pid, i;
+ struct arm_linux_hw_breakpoint *bpts, *wpts;
+ struct arch_lwp_info *arm_lwp_info = lwp->arch_private;
+
+ pid = ptid_get_lwp (lwp->ptid);
+ bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts;
+ wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts;
+
+ /* NULL means this is the main thread still going through the shell,
+ or, no watchpoint has been set yet. In that case, there's
+ nothing to do. */
+ if (arm_lwp_info == NULL)
+ return;
+
+ for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++)
+ if (arm_lwp_info->bpts_changed[i])
+ {
+ errno = 0;
+ if (arm_hwbp_control_is_enabled (bpts[i].control))
+ if (ptrace (PTRACE_SETHBPREGS, pid,
+ (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0)
+ perror_with_name (_("Unexpected error setting breakpoint"));
+
+ if (bpts[i].control != 0)
+ if (ptrace (PTRACE_SETHBPREGS, pid,
+ (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0)
+ perror_with_name (_("Unexpected error setting breakpoint"));
+
+ arm_lwp_info->bpts_changed[i] = 0;
+ }
+
+ for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++)
+ if (arm_lwp_info->wpts_changed[i])
+ {
+ errno = 0;
+ if (arm_hwbp_control_is_enabled (wpts[i].control))
+ if (ptrace (PTRACE_SETHBPREGS, pid,
+ (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0)
+ perror_with_name (_("Unexpected error setting watchpoint"));
+
+ if (wpts[i].control != 0)
+ if (ptrace (PTRACE_SETHBPREGS, pid,
+ (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0)
+ perror_with_name (_("Unexpected error setting watchpoint"));
+
+ arm_lwp_info->wpts_changed[i] = 0;
+ }
}
+/* linux_nat_new_fork hook. */
+
+static void
+arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid)
+{
+ pid_t parent_pid;
+ struct arm_linux_debug_reg_state *parent_state;
+ struct arm_linux_debug_reg_state *child_state;
+
+ /* NULL means no watchpoint has ever been set in the parent. In
+ that case, there's nothing to do. */
+ if (parent->arch_private == NULL)
+ return;
+
+ /* GDB core assumes the child inherits the watchpoints/hw
+ breakpoints of the parent, and will remove them all from the
+ forked off process. Copy the debug registers mirrors into the
+ new process so that all breakpoints and watchpoints can be
+ removed together. */
+
+ parent_pid = ptid_get_pid (parent->ptid);
+ parent_state = arm_linux_get_debug_reg_state (parent_pid);
+ child_state = arm_linux_get_debug_reg_state (child_pid);
+ *child_state = *parent_state;
+}
+
+void _initialize_arm_linux_nat (void);
+
void
_initialize_arm_linux_nat (void)
{
- os_version = get_linux_version (&os_major, &os_minor, &os_release);
+ struct target_ops *t;
+
+ /* Fill in the generic GNU/Linux methods. */
+ t = linux_target ();
+
+ /* Add our register access methods. */
+ t->to_fetch_registers = arm_linux_fetch_inferior_registers;
+ t->to_store_registers = arm_linux_store_inferior_registers;
+
+ /* Add our hardware breakpoint and watchpoint implementation. */
+ t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint;
+ t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint;
+ t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint;
+ t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint;
+ t->to_insert_watchpoint = arm_linux_insert_watchpoint;
+ t->to_remove_watchpoint = arm_linux_remove_watchpoint;
+ t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint;
+ t->to_stopped_data_address = arm_linux_stopped_data_address;
+ t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range;
+
+ t->to_read_description = arm_linux_read_description;
+
+ /* Register the target. */
+ linux_nat_add_target (t);
+
+ /* Handle thread creation and exit. */
+ linux_nat_set_new_thread (t, arm_linux_new_thread);
+ linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume);
+
+ /* Handle process creation and exit. */
+ linux_nat_set_new_fork (t, arm_linux_new_fork);
+ linux_nat_set_forget_process (t, arm_linux_forget_process);
}
projects / deliverable / binutils-gdb.git / blobdiff