You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
-#include <ctype.h> /* XXX for isupper () */
+#include <ctype.h> /* XXX for isupper (). */
#include "defs.h"
#include "frame.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "gdb_string.h"
-#include "dis-asm.h" /* For register styles. */
+#include "dis-asm.h" /* For register styles. */
#include "regcache.h"
#include "reggroups.h"
#include "doublest.h"
#include "prologue-value.h"
#include "target-descriptions.h"
#include "user-regs.h"
+#include "observer.h"
#include "arm-tdep.h"
#include "gdb/sim-arm.h"
MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
-#define MSYMBOL_SET_SPECIAL(msym) \
+#define MSYMBOL_SET_SPECIAL(msym) \
MSYMBOL_TARGET_FLAG_1 (msym) = 1
#define MSYMBOL_IS_SPECIAL(msym) \
struct obj_section *sec;
struct minimal_symbol *sym;
char type;
+ struct displaced_step_closure* dsc
+ = get_displaced_step_closure_by_addr(memaddr);
+
+ /* If checking the mode of displaced instruction in copy area, the mode
+ should be determined by instruction on the original address. */
+ if (dsc)
+ {
+ if (debug_displaced)
+ fprintf_unfiltered (gdb_stdlog,
+ "displaced: check mode of %.8lx instead of %.8lx\n",
+ (unsigned long) dsc->insn_addr,
+ (unsigned long) memaddr);
+ memaddr = dsc->insn_addr;
+ }
/* If bit 0 of the address is set, assume this is a Thumb address. */
if (IS_THUMB_ADDR (memaddr))
}
/* Return 1 if PC is the start of a compiler helper function which
- can be safely ignored during prologue skipping. */
+ can be safely ignored during prologue skipping. IS_THUMB is true
+ if the function is known to be a Thumb function due to the way it
+ is being called. */
static int
-skip_prologue_function (CORE_ADDR pc)
+skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
{
+ enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
struct minimal_symbol *msym;
- const char *name;
msym = lookup_minimal_symbol_by_pc (pc);
- if (msym == NULL || SYMBOL_VALUE_ADDRESS (msym) != pc)
- return 0;
+ if (msym != NULL
+ && SYMBOL_VALUE_ADDRESS (msym) == pc
+ && SYMBOL_LINKAGE_NAME (msym) != NULL)
+ {
+ const char *name = SYMBOL_LINKAGE_NAME (msym);
- name = SYMBOL_LINKAGE_NAME (msym);
- if (name == NULL)
- return 0;
+ /* The GNU linker's Thumb call stub to foo is named
+ __foo_from_thumb. */
+ if (strstr (name, "_from_thumb") != NULL)
+ name += 2;
- /* The GNU linker's Thumb call stub to foo is named
- __foo_from_thumb. */
- if (strstr (name, "_from_thumb") != NULL)
- name += 2;
+ /* On soft-float targets, __truncdfsf2 is called to convert promoted
+ arguments to their argument types in non-prototyped
+ functions. */
+ if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
+ return 1;
+ if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
+ return 1;
- /* On soft-float targets, __truncdfsf2 is called to convert promoted
- arguments to their argument types in non-prototyped
- functions. */
- if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
- return 1;
- if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
- return 1;
+ /* Internal functions related to thread-local storage. */
+ if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
+ return 1;
+ if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
+ return 1;
+ }
+ else
+ {
+ /* If we run against a stripped glibc, we may be unable to identify
+ special functions by name. Check for one important case,
+ __aeabi_read_tp, by comparing the *code* against the default
+ implementation (this is hand-written ARM assembler in glibc). */
- /* Internal functions related to thread-local storage. */
- if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
- return 1;
- if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
- return 1;
+ if (!is_thumb
+ && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
+ == 0xe3e00a0f /* mov r0, #0xffff0fff */
+ && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
+ == 0xe240f01f) /* sub pc, r0, #31 */
+ return 1;
+ }
return 0;
}
if (bit (inst2, 12) == 0)
nextpc = nextpc & 0xfffffffc;
- if (!skip_prologue_function (nextpc))
+ if (!skip_prologue_function (gdbarch, nextpc,
+ bit (inst2, 12) != 0))
break;
}
- else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, { registers } */
+ else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
+ { registers } */
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
{
pv_t addr = regs[bits (insn, 0, 3)];
regs[bits (insn, 0, 3)] = addr;
}
- else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */
+ else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
+ [Rn, #+/-imm]{!} */
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
{
int regno1 = bits (inst2, 12, 15);
/* Ignore stores of argument registers to the stack. */
;
- else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
+ else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
+ { registers } */
&& (inst2 & 0x8000) == 0x0000
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
/* Ignore block loads from the stack, potentially copying
parameters from memory. */
;
- else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */
+ else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
+ [Rn, #+/-imm] */
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
/* Similarly ignore dual loads from the stack. */
;
}
else
{
- unsigned int insn
- = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
-
- if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
- {
- address = bits (insn, 0, 11);
- *destreg = bits (insn, 12, 15);
- *offset = 4;
- }
- else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
- {
- low = EXTRACT_MOVW_MOVT_IMM_A (insn);
+ unsigned int insn
+ = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
- insn
- = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
+ if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
+ {
+ address = bits (insn, 0, 11);
+ *destreg = bits (insn, 12, 15);
+ *offset = 4;
+ }
+ else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
+ {
+ low = EXTRACT_MOVW_MOVT_IMM_A (insn);
- if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
- high = EXTRACT_MOVW_MOVT_IMM_A (insn);
+ insn
+ = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
- address = (high << 16 | low);
- *destreg = bits (insn, 12, 15);
- *offset = 8;
- }
+ if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
+ {
+ high = EXTRACT_MOVW_MOVT_IMM_A (insn);
+ *destreg = bits (insn, 12, 15);
+ *offset = 8;
+ address = (high << 16 | low);
+ }
+ }
}
return address;
}
/* Try to skip a sequence of instructions used for stack protector. If PC
- points to the first instruction of this sequence, return the address of first
- instruction after this sequence, otherwise, return original PC.
+ points to the first instruction of this sequence, return the address of
+ first instruction after this sequence, otherwise, return original PC.
On arm, this sequence of instructions is composed of mainly three steps,
Step 1: load symbol __stack_chk_guard,
instruction sequence is not for stack protector. If symbol is
removed, we conservatively think this sequence is for stack protector. */
if (stack_chk_guard
- && strcmp (SYMBOL_LINKAGE_NAME(stack_chk_guard), "__stack_chk_guard"))
+ && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
+ strlen ("__stack_chk_guard")) != 0)
return pc;
if (is_thumb)
[stfe f6, [sp, #-12]!]
[stfe f5, [sp, #-12]!]
[stfe f4, [sp, #-12]!]
- sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
+ sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
static CORE_ADDR
arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to provide
that bound, then use an arbitrary large number as the upper bound. */
- /* Like arm_scan_prologue, stop no later than pc + 64. */
+ /* Like arm_scan_prologue, stop no later than pc + 64. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
limit_pc = pc + 64; /* Magic. */
break;
}
- return skip_pc; /* End of prologue */
+ return skip_pc; /* End of prologue. */
}
/* *INDENT-OFF* */
R7 -> 0 local variables (16 bytes)
SP -> -12 additional stack space (12 bytes)
The frame size would thus be 36 bytes, and the frame offset would be
- 12 bytes. The frame register is R7.
+ 12 bytes. The frame register is R7.
The comments for thumb_skip_prolog() describe the algorithm we use
to detect the end of the prolog. */
return 0;
default:
- internal_error (__FILE__, __LINE__, "bad value in switch");
+ internal_error (__FILE__, __LINE__, _("bad value in switch"));
}
}
regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
continue;
}
- else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
+ else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
+ [sp, #-4]! */
{
if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
break;
for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
if (mask & (1 << regno))
{
- regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
+ regs[ARM_SP_REGNUM]
+ = pv_add_constant (regs[ARM_SP_REGNUM], -4);
pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
}
}
/* No need to add this to saved_regs -- it's just an arg reg. */
continue;
}
- else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
+ else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
+ { registers } */
&& pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
{
/* No need to add this to saved_regs -- it's just arg regs. */
imm = (imm >> rot) | (imm << (32 - rot));
regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
}
- else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
+ else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
+ [sp, -#c]! */
&& gdbarch_tdep (gdbarch)->have_fpa_registers)
{
if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
}
- else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
+ else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
+ [sp!] */
&& gdbarch_tdep (gdbarch)->have_fpa_registers)
{
int n_saved_fp_regs;
the stack. */
CORE_ADDR dest = BranchDest (current_pc, insn);
- if (skip_prologue_function (dest))
+ if (skip_prologue_function (gdbarch, dest, 0))
continue;
else
break;
}
else if ((insn & 0xf0000000) != 0xe0000000)
- break; /* Condition not true, exit early */
+ break; /* Condition not true, exit early. */
else if (arm_instruction_changes_pc (insn))
/* Don't scan past anything that might change control flow. */
break;
if (cache->prev_sp == 0)
return;
+ /* Use function start address as part of the frame ID. If we cannot
+ identify the start address (due to missing symbol information),
+ fall back to just using the current PC. */
func = get_frame_func (this_frame);
+ if (!func)
+ func = pc;
+
id = frame_id_build (cache->prev_sp, func);
*this_id = id;
}
default_frame_sniffer
};
+/* Maintain a list of ARM exception table entries per objfile, similar to the
+ list of mapping symbols. We only cache entries for standard ARM-defined
+ personality routines; the cache will contain only the frame unwinding
+ instructions associated with the entry (not the descriptors). */
+
+static const struct objfile_data *arm_exidx_data_key;
+
+struct arm_exidx_entry
+{
+ bfd_vma addr;
+ gdb_byte *entry;
+};
+typedef struct arm_exidx_entry arm_exidx_entry_s;
+DEF_VEC_O(arm_exidx_entry_s);
+
+struct arm_exidx_data
+{
+ VEC(arm_exidx_entry_s) **section_maps;
+};
+
+static void
+arm_exidx_data_free (struct objfile *objfile, void *arg)
+{
+ struct arm_exidx_data *data = arg;
+ unsigned int i;
+
+ for (i = 0; i < objfile->obfd->section_count; i++)
+ VEC_free (arm_exidx_entry_s, data->section_maps[i]);
+}
+
+static inline int
+arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
+ const struct arm_exidx_entry *rhs)
+{
+ return lhs->addr < rhs->addr;
+}
+
+static struct obj_section *
+arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
+{
+ struct obj_section *osect;
+
+ ALL_OBJFILE_OSECTIONS (objfile, osect)
+ if (bfd_get_section_flags (objfile->obfd,
+ osect->the_bfd_section) & SEC_ALLOC)
+ {
+ bfd_vma start, size;
+ start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
+ size = bfd_get_section_size (osect->the_bfd_section);
+
+ if (start <= vma && vma < start + size)
+ return osect;
+ }
+
+ return NULL;
+}
+
+/* Parse contents of exception table and exception index sections
+ of OBJFILE, and fill in the exception table entry cache.
+
+ For each entry that refers to a standard ARM-defined personality
+ routine, extract the frame unwinding instructions (from either
+ the index or the table section). The unwinding instructions
+ are normalized by:
+ - extracting them from the rest of the table data
+ - converting to host endianness
+ - appending the implicit 0xb0 ("Finish") code
+
+ The extracted and normalized instructions are stored for later
+ retrieval by the arm_find_exidx_entry routine. */
+
+static void
+arm_exidx_new_objfile (struct objfile *objfile)
+{
+ struct cleanup *cleanups = make_cleanup (null_cleanup, NULL);
+ struct arm_exidx_data *data;
+ asection *exidx, *extab;
+ bfd_vma exidx_vma = 0, extab_vma = 0;
+ bfd_size_type exidx_size = 0, extab_size = 0;
+ gdb_byte *exidx_data = NULL, *extab_data = NULL;
+ LONGEST i;
+
+ /* If we've already touched this file, do nothing. */
+ if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
+ return;
+
+ /* Read contents of exception table and index. */
+ exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
+ if (exidx)
+ {
+ exidx_vma = bfd_section_vma (objfile->obfd, exidx);
+ exidx_size = bfd_get_section_size (exidx);
+ exidx_data = xmalloc (exidx_size);
+ make_cleanup (xfree, exidx_data);
+
+ if (!bfd_get_section_contents (objfile->obfd, exidx,
+ exidx_data, 0, exidx_size))
+ {
+ do_cleanups (cleanups);
+ return;
+ }
+ }
+
+ extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
+ if (extab)
+ {
+ extab_vma = bfd_section_vma (objfile->obfd, extab);
+ extab_size = bfd_get_section_size (extab);
+ extab_data = xmalloc (extab_size);
+ make_cleanup (xfree, extab_data);
+
+ if (!bfd_get_section_contents (objfile->obfd, extab,
+ extab_data, 0, extab_size))
+ {
+ do_cleanups (cleanups);
+ return;
+ }
+ }
+
+ /* Allocate exception table data structure. */
+ data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
+ set_objfile_data (objfile, arm_exidx_data_key, data);
+ data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
+ objfile->obfd->section_count,
+ VEC(arm_exidx_entry_s) *);
+
+ /* Fill in exception table. */
+ for (i = 0; i < exidx_size / 8; i++)
+ {
+ struct arm_exidx_entry new_exidx_entry;
+ bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
+ bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
+ bfd_vma addr = 0, word = 0;
+ int n_bytes = 0, n_words = 0;
+ struct obj_section *sec;
+ gdb_byte *entry = NULL;
+
+ /* Extract address of start of function. */
+ idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
+ idx += exidx_vma + i * 8;
+
+ /* Find section containing function and compute section offset. */
+ sec = arm_obj_section_from_vma (objfile, idx);
+ if (sec == NULL)
+ continue;
+ idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
+
+ /* Determine address of exception table entry. */
+ if (val == 1)
+ {
+ /* EXIDX_CANTUNWIND -- no exception table entry present. */
+ }
+ else if ((val & 0xff000000) == 0x80000000)
+ {
+ /* Exception table entry embedded in .ARM.exidx
+ -- must be short form. */
+ word = val;
+ n_bytes = 3;
+ }
+ else if (!(val & 0x80000000))
+ {
+ /* Exception table entry in .ARM.extab. */
+ addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
+ addr += exidx_vma + i * 8 + 4;
+
+ if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
+ {
+ word = bfd_h_get_32 (objfile->obfd,
+ extab_data + addr - extab_vma);
+ addr += 4;
+
+ if ((word & 0xff000000) == 0x80000000)
+ {
+ /* Short form. */
+ n_bytes = 3;
+ }
+ else if ((word & 0xff000000) == 0x81000000
+ || (word & 0xff000000) == 0x82000000)
+ {
+ /* Long form. */
+ n_bytes = 2;
+ n_words = ((word >> 16) & 0xff);
+ }
+ else if (!(word & 0x80000000))
+ {
+ bfd_vma pers;
+ struct obj_section *pers_sec;
+ int gnu_personality = 0;
+
+ /* Custom personality routine. */
+ pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
+ pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
+
+ /* Check whether we've got one of the variants of the
+ GNU personality routines. */
+ pers_sec = arm_obj_section_from_vma (objfile, pers);
+ if (pers_sec)
+ {
+ static const char *personality[] =
+ {
+ "__gcc_personality_v0",
+ "__gxx_personality_v0",
+ "__gcj_personality_v0",
+ "__gnu_objc_personality_v0",
+ NULL
+ };
+
+ CORE_ADDR pc = pers + obj_section_offset (pers_sec);
+ int k;
+
+ for (k = 0; personality[k]; k++)
+ if (lookup_minimal_symbol_by_pc_name
+ (pc, personality[k], objfile))
+ {
+ gnu_personality = 1;
+ break;
+ }
+ }
+
+ /* If so, the next word contains a word count in the high
+ byte, followed by the same unwind instructions as the
+ pre-defined forms. */
+ if (gnu_personality
+ && addr + 4 <= extab_vma + extab_size)
+ {
+ word = bfd_h_get_32 (objfile->obfd,
+ extab_data + addr - extab_vma);
+ addr += 4;
+ n_bytes = 3;
+ n_words = ((word >> 24) & 0xff);
+ }
+ }
+ }
+ }
+
+ /* Sanity check address. */
+ if (n_words)
+ if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
+ n_words = n_bytes = 0;
+
+ /* The unwind instructions reside in WORD (only the N_BYTES least
+ significant bytes are valid), followed by N_WORDS words in the
+ extab section starting at ADDR. */
+ if (n_bytes || n_words)
+ {
+ gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
+ n_bytes + n_words * 4 + 1);
+
+ while (n_bytes--)
+ *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
+
+ while (n_words--)
+ {
+ word = bfd_h_get_32 (objfile->obfd,
+ extab_data + addr - extab_vma);
+ addr += 4;
+
+ *p++ = (gdb_byte) ((word >> 24) & 0xff);
+ *p++ = (gdb_byte) ((word >> 16) & 0xff);
+ *p++ = (gdb_byte) ((word >> 8) & 0xff);
+ *p++ = (gdb_byte) (word & 0xff);
+ }
+
+ /* Implied "Finish" to terminate the list. */
+ *p++ = 0xb0;
+ }
+
+ /* Push entry onto vector. They are guaranteed to always
+ appear in order of increasing addresses. */
+ new_exidx_entry.addr = idx;
+ new_exidx_entry.entry = entry;
+ VEC_safe_push (arm_exidx_entry_s,
+ data->section_maps[sec->the_bfd_section->index],
+ &new_exidx_entry);
+ }
+
+ do_cleanups (cleanups);
+}
+
+/* Search for the exception table entry covering MEMADDR. If one is found,
+ return a pointer to its data. Otherwise, return 0. If START is non-NULL,
+ set *START to the start of the region covered by this entry. */
+
+static gdb_byte *
+arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
+{
+ struct obj_section *sec;
+
+ sec = find_pc_section (memaddr);
+ if (sec != NULL)
+ {
+ struct arm_exidx_data *data;
+ VEC(arm_exidx_entry_s) *map;
+ struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
+ unsigned int idx;
+
+ data = objfile_data (sec->objfile, arm_exidx_data_key);
+ if (data != NULL)
+ {
+ map = data->section_maps[sec->the_bfd_section->index];
+ if (!VEC_empty (arm_exidx_entry_s, map))
+ {
+ struct arm_exidx_entry *map_sym;
+
+ idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
+ arm_compare_exidx_entries);
+
+ /* VEC_lower_bound finds the earliest ordered insertion
+ point. If the following symbol starts at this exact
+ address, we use that; otherwise, the preceding
+ exception table entry covers this address. */
+ if (idx < VEC_length (arm_exidx_entry_s, map))
+ {
+ map_sym = VEC_index (arm_exidx_entry_s, map, idx);
+ if (map_sym->addr == map_key.addr)
+ {
+ if (start)
+ *start = map_sym->addr + obj_section_addr (sec);
+ return map_sym->entry;
+ }
+ }
+
+ if (idx > 0)
+ {
+ map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
+ if (start)
+ *start = map_sym->addr + obj_section_addr (sec);
+ return map_sym->entry;
+ }
+ }
+ }
+ }
+
+ return NULL;
+}
+
+/* Given the current frame THIS_FRAME, and its associated frame unwinding
+ instruction list from the ARM exception table entry ENTRY, allocate and
+ return a prologue cache structure describing how to unwind this frame.
+
+ Return NULL if the unwinding instruction list contains a "spare",
+ "reserved" or "refuse to unwind" instruction as defined in section
+ "9.3 Frame unwinding instructions" of the "Exception Handling ABI
+ for the ARM Architecture" document. */
+
+static struct arm_prologue_cache *
+arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
+{
+ CORE_ADDR vsp = 0;
+ int vsp_valid = 0;
+
+ struct arm_prologue_cache *cache;
+ cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
+ cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+
+ for (;;)
+ {
+ gdb_byte insn;
+
+ /* Whenever we reload SP, we actually have to retrieve its
+ actual value in the current frame. */
+ if (!vsp_valid)
+ {
+ if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
+ {
+ int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
+ vsp = get_frame_register_unsigned (this_frame, reg);
+ }
+ else
+ {
+ CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
+ vsp = get_frame_memory_unsigned (this_frame, addr, 4);
+ }
+
+ vsp_valid = 1;
+ }
+
+ /* Decode next unwind instruction. */
+ insn = *entry++;
+
+ if ((insn & 0xc0) == 0)
+ {
+ int offset = insn & 0x3f;
+ vsp += (offset << 2) + 4;
+ }
+ else if ((insn & 0xc0) == 0x40)
+ {
+ int offset = insn & 0x3f;
+ vsp -= (offset << 2) + 4;
+ }
+ else if ((insn & 0xf0) == 0x80)
+ {
+ int mask = ((insn & 0xf) << 8) | *entry++;
+ int i;
+
+ /* The special case of an all-zero mask identifies
+ "Refuse to unwind". We return NULL to fall back
+ to the prologue analyzer. */
+ if (mask == 0)
+ return NULL;
+
+ /* Pop registers r4..r15 under mask. */
+ for (i = 0; i < 12; i++)
+ if (mask & (1 << i))
+ {
+ cache->saved_regs[4 + i].addr = vsp;
+ vsp += 4;
+ }
+
+ /* Special-case popping SP -- we need to reload vsp. */
+ if (mask & (1 << (ARM_SP_REGNUM - 4)))
+ vsp_valid = 0;
+ }
+ else if ((insn & 0xf0) == 0x90)
+ {
+ int reg = insn & 0xf;
+
+ /* Reserved cases. */
+ if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
+ return NULL;
+
+ /* Set SP from another register and mark VSP for reload. */
+ cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
+ vsp_valid = 0;
+ }
+ else if ((insn & 0xf0) == 0xa0)
+ {
+ int count = insn & 0x7;
+ int pop_lr = (insn & 0x8) != 0;
+ int i;
+
+ /* Pop r4..r[4+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[4 + i].addr = vsp;
+ vsp += 4;
+ }
+
+ /* If indicated by flag, pop LR as well. */
+ if (pop_lr)
+ {
+ cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
+ vsp += 4;
+ }
+ }
+ else if (insn == 0xb0)
+ {
+ /* We could only have updated PC by popping into it; if so, it
+ will show up as address. Otherwise, copy LR into PC. */
+ if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
+ cache->saved_regs[ARM_PC_REGNUM]
+ = cache->saved_regs[ARM_LR_REGNUM];
+
+ /* We're done. */
+ break;
+ }
+ else if (insn == 0xb1)
+ {
+ int mask = *entry++;
+ int i;
+
+ /* All-zero mask and mask >= 16 is "spare". */
+ if (mask == 0 || mask >= 16)
+ return NULL;
+
+ /* Pop r0..r3 under mask. */
+ for (i = 0; i < 4; i++)
+ if (mask & (1 << i))
+ {
+ cache->saved_regs[i].addr = vsp;
+ vsp += 4;
+ }
+ }
+ else if (insn == 0xb2)
+ {
+ ULONGEST offset = 0;
+ unsigned shift = 0;
+
+ do
+ {
+ offset |= (*entry & 0x7f) << shift;
+ shift += 7;
+ }
+ while (*entry++ & 0x80);
+
+ vsp += 0x204 + (offset << 2);
+ }
+ else if (insn == 0xb3)
+ {
+ int start = *entry >> 4;
+ int count = (*entry++) & 0xf;
+ int i;
+
+ /* Only registers D0..D15 are valid here. */
+ if (start + count >= 16)
+ return NULL;
+
+ /* Pop VFP double-precision registers D[start]..D[start+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
+ vsp += 8;
+ }
+
+ /* Add an extra 4 bytes for FSTMFDX-style stack. */
+ vsp += 4;
+ }
+ else if ((insn & 0xf8) == 0xb8)
+ {
+ int count = insn & 0x7;
+ int i;
+
+ /* Pop VFP double-precision registers D[8]..D[8+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
+ vsp += 8;
+ }
+
+ /* Add an extra 4 bytes for FSTMFDX-style stack. */
+ vsp += 4;
+ }
+ else if (insn == 0xc6)
+ {
+ int start = *entry >> 4;
+ int count = (*entry++) & 0xf;
+ int i;
+
+ /* Only registers WR0..WR15 are valid. */
+ if (start + count >= 16)
+ return NULL;
+
+ /* Pop iwmmx registers WR[start]..WR[start+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
+ vsp += 8;
+ }
+ }
+ else if (insn == 0xc7)
+ {
+ int mask = *entry++;
+ int i;
+
+ /* All-zero mask and mask >= 16 is "spare". */
+ if (mask == 0 || mask >= 16)
+ return NULL;
+
+ /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
+ for (i = 0; i < 4; i++)
+ if (mask & (1 << i))
+ {
+ cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
+ vsp += 4;
+ }
+ }
+ else if ((insn & 0xf8) == 0xc0)
+ {
+ int count = insn & 0x7;
+ int i;
+
+ /* Pop iwmmx registers WR[10]..WR[10+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
+ vsp += 8;
+ }
+ }
+ else if (insn == 0xc8)
+ {
+ int start = *entry >> 4;
+ int count = (*entry++) & 0xf;
+ int i;
+
+ /* Only registers D0..D31 are valid. */
+ if (start + count >= 16)
+ return NULL;
+
+ /* Pop VFP double-precision registers
+ D[16+start]..D[16+start+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
+ vsp += 8;
+ }
+ }
+ else if (insn == 0xc9)
+ {
+ int start = *entry >> 4;
+ int count = (*entry++) & 0xf;
+ int i;
+
+ /* Pop VFP double-precision registers D[start]..D[start+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
+ vsp += 8;
+ }
+ }
+ else if ((insn & 0xf8) == 0xd0)
+ {
+ int count = insn & 0x7;
+ int i;
+
+ /* Pop VFP double-precision registers D[8]..D[8+count]. */
+ for (i = 0; i <= count; i++)
+ {
+ cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
+ vsp += 8;
+ }
+ }
+ else
+ {
+ /* Everything else is "spare". */
+ return NULL;
+ }
+ }
+
+ /* If we restore SP from a register, assume this was the frame register.
+ Otherwise just fall back to SP as frame register. */
+ if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
+ cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
+ else
+ cache->framereg = ARM_SP_REGNUM;
+
+ /* Determine offset to previous frame. */
+ cache->framesize
+ = vsp - get_frame_register_unsigned (this_frame, cache->framereg);
+
+ /* We already got the previous SP. */
+ cache->prev_sp = vsp;
+
+ return cache;
+}
+
+/* Unwinding via ARM exception table entries. Note that the sniffer
+ already computes a filled-in prologue cache, which is then used
+ with the same arm_prologue_this_id and arm_prologue_prev_register
+ routines also used for prologue-parsing based unwinding. */
+
+static int
+arm_exidx_unwind_sniffer (const struct frame_unwind *self,
+ struct frame_info *this_frame,
+ void **this_prologue_cache)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
+ CORE_ADDR addr_in_block, exidx_region, func_start;
+ struct arm_prologue_cache *cache;
+ gdb_byte *entry;
+
+ /* See if we have an ARM exception table entry covering this address. */
+ addr_in_block = get_frame_address_in_block (this_frame);
+ entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
+ if (!entry)
+ return 0;
+
+ /* The ARM exception table does not describe unwind information
+ for arbitrary PC values, but is guaranteed to be correct only
+ at call sites. We have to decide here whether we want to use
+ ARM exception table information for this frame, or fall back
+ to using prologue parsing. (Note that if we have DWARF CFI,
+ this sniffer isn't even called -- CFI is always preferred.)
+
+ Before we make this decision, however, we check whether we
+ actually have *symbol* information for the current frame.
+ If not, prologue parsing would not work anyway, so we might
+ as well use the exception table and hope for the best. */
+ if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
+ {
+ int exc_valid = 0;
+
+ /* If the next frame is "normal", we are at a call site in this
+ frame, so exception information is guaranteed to be valid. */
+ if (get_next_frame (this_frame)
+ && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
+ exc_valid = 1;
+
+ /* We also assume exception information is valid if we're currently
+ blocked in a system call. The system library is supposed to
+ ensure this, so that e.g. pthread cancellation works. */
+ if (arm_frame_is_thumb (this_frame))
+ {
+ LONGEST insn;
+
+ if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
+ byte_order_for_code, &insn)
+ && (insn & 0xff00) == 0xdf00 /* svc */)
+ exc_valid = 1;
+ }
+ else
+ {
+ LONGEST insn;
+
+ if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
+ byte_order_for_code, &insn)
+ && (insn & 0x0f000000) == 0x0f000000 /* svc */)
+ exc_valid = 1;
+ }
+
+ /* Bail out if we don't know that exception information is valid. */
+ if (!exc_valid)
+ return 0;
+
+ /* The ARM exception index does not mark the *end* of the region
+ covered by the entry, and some functions will not have any entry.
+ To correctly recognize the end of the covered region, the linker
+ should have inserted dummy records with a CANTUNWIND marker.
+
+ Unfortunately, current versions of GNU ld do not reliably do
+ this, and thus we may have found an incorrect entry above.
+ As a (temporary) sanity check, we only use the entry if it
+ lies *within* the bounds of the function. Note that this check
+ might reject perfectly valid entries that just happen to cover
+ multiple functions; therefore this check ought to be removed
+ once the linker is fixed. */
+ if (func_start > exidx_region)
+ return 0;
+ }
+
+ /* Decode the list of unwinding instructions into a prologue cache.
+ Note that this may fail due to e.g. a "refuse to unwind" code. */
+ cache = arm_exidx_fill_cache (this_frame, entry);
+ if (!cache)
+ return 0;
+
+ *this_prologue_cache = cache;
+ return 1;
+}
+
+struct frame_unwind arm_exidx_unwind = {
+ NORMAL_FRAME,
+ arm_prologue_this_id,
+ arm_prologue_prev_register,
+ NULL,
+ arm_exidx_unwind_sniffer
+};
+
static struct arm_prologue_cache *
arm_make_stub_cache (struct frame_info *this_frame)
{
static struct frame_id
arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
{
- return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
+ return frame_id_build (get_frame_register_unsigned (this_frame,
+ ARM_SP_REGNUM),
get_frame_pc (this_frame));
}
exception of return itself, updates the stack pointer, we need to
scan backwards for at most one instruction. Try either a 16-bit or
a 32-bit instruction. This is just a heuristic, so we do not worry
- too much about false positives.*/
+ too much about false positives. */
if (!found_stack_adjust)
{
{
int nbits;
for (nbits = 0; val != 0; nbits++)
- val &= val - 1; /* delete rightmost 1-bit in val */
+ val &= val - 1; /* Delete rightmost 1-bit in val. */
return nbits;
}
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
unsigned short inst1;
- CORE_ADDR nextpc = pc + 2; /* default is next instruction */
+ CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
unsigned long offset;
ULONGEST status, itstate;
while (itstate != 0 && ! condition_true (itstate >> 4, status))
{
- inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
+ inst1 = read_memory_unsigned_integer (pc, 2,
+ byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
}
while (itstate != 0 && ! condition_true (itstate >> 4, status))
{
- inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
+ inst1 = read_memory_unsigned_integer (pc, 2,
+ byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
}
the instruction after the IT block. */
do
{
- inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
+ inst1 = read_memory_unsigned_integer (pc, 2,
+ byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
}
The value returned has the execution state of the next instruction
encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
- address.
-*/
+ address. */
+
static CORE_ADDR
arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
{
return nextpc;
}
- /* Multiply into PC */
+ /* Multiply into PC. */
c = (status & FLAG_C) ? 1 : 0;
rn = bits (this_instr, 16, 19);
operand1 = (rn == 15) ? pc_val + 8
operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
& 0xffffffff;
}
- else /* operand 2 is a shifted register */
- operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
+ else /* operand 2 is a shifted register. */
+ operand2 = shifted_reg_val (frame, this_instr, c,
+ pc_val, status);
switch (bits (this_instr, 21, 24))
{
known boundary. */
if (! definite)
{
- buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
+ buf = extend_buffer_earlier (buf, bpaddr, buf_len,
+ bpaddr - boundary);
if (buf == NULL)
return bpaddr;
buf_len = bpaddr - boundary;
arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
Depending on the type of instruction, it is then copied to a scratch
location, possibly in a modified form. The copy_* set of functions
- performs such modification, as necessary. A breakpoint is placed after
+ performs such modification, as necessary. A breakpoint is placed after
the modified instruction in the scratch space to return control to GDB.
Note in particular that instructions which modify the PC will no longer
do so after modification.
if (displaced_in_arm_mode (regs))
/* Note: If bits 0/1 are set, this branch would be unpredictable for
architecture versions < 6. */
- regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3);
+ regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
+ val & ~(ULONGEST) 0x3);
else
- regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1);
+ regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
+ val & ~(ULONGEST) 0x1);
}
/* Write to the PC as from a branch-exchange instruction. */
/* This function is used to concisely determine if an instruction INSN
references PC. Register fields of interest in INSN should have the
- corresponding fields of BITMASK set to 0b1111. The function returns return 1
- if any of these fields in INSN reference the PC (also 0b1111, r15), else it
- returns 0. */
+ corresponding fields of BITMASK set to 0b1111. The function
+ returns return 1 if any of these fields in INSN reference the PC
+ (also 0b1111, r15), else it returns 0. */
static int
insn_references_pc (uint32_t insn, uint32_t bitmask)
/* Preload instructions with register offset. */
static int
-copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
+copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
+ struct regcache *regs,
struct displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog, "displaced: copying %s register insn "
- "%.8lx\n", (link) ? "blx" : "bx", (unsigned long) insn);
+ "%.8lx\n", (link) ? "blx" : "bx",
+ (unsigned long) insn);
/* Implement {BX,BLX}<cond> <reg>" as:
return 0;
}
-/* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
+/* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
static void
cleanup_alu_imm (struct gdbarch *gdbarch,
static int
copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs,
+ struct displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
unsigned int rm = bits (insn, 0, 3);
/* To write PC we can do:
- scratch+0: str pc, temp (*temp = scratch + 8 + offset)
- scratch+4: ldr r4, temp
- scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
- scratch+12: add r4, r4, #8 (r4 = offset)
- scratch+16: add r0, r0, r4
- scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
- scratch+24: <temp>
+ Before this sequence of instructions:
+ r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
+ r2 is the Rn value got from dispalced_read_reg.
+
+ Insn1: push {pc} Write address of STR instruction + offset on stack
+ Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
+ Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
+ = addr(Insn1) + offset - addr(Insn3) - 8
+ = offset - 16
+ Insn4: add r4, r4, #8 r4 = offset - 8
+ Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
+ = from + offset
+ Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
Otherwise we don't know what value to write for PC, since the offset is
- architecture-dependent (sometimes PC+8, sometimes PC+12). */
+ architecture-dependent (sometimes PC+8, sometimes PC+12). More details
+ of this can be found in Section "Saving from r15" in
+ http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
if (load || rt != 15)
{
{
/* We need to use r4 as scratch. Make sure it's restored afterwards. */
dsc->u.ldst.restore_r4 = 1;
-
- dsc->modinsn[0] = 0xe58ff014; /* str pc, [pc, #20]. */
- dsc->modinsn[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
+ dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
+ dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
int rn = bits (insn, 16, 19);
CORE_ADDR from = dsc->insn_addr;
- /* Block transfers which don't mention PC can be run directly out-of-line. */
+ /* Block transfers which don't mention PC can be run directly
+ out-of-line. */
if (rn != 15 && (insn & 0x8000) == 0)
return copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
if (rn == 15)
{
- warning (_("displaced: Unpredictable LDM or STM with base register r15"));
+ warning (_("displaced: Unpredictable LDM or STM with "
+ "base register r15"));
return copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
}
struct displaced_step_closure *dsc)
{
if (debug_displaced)
- fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn %.8lx\n",
+ fprintf_unfiltered (gdb_stdlog,
+ "displaced: copying undefined insn %.8lx\n",
(unsigned long) insn);
dsc->modinsn[0] = insn;
static int
decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs,
+ struct displaced_step_closure *dsc)
{
if (bit (insn, 27) == 0)
return decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
static int
decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs,
+ struct displaced_step_closure *dsc)
{
unsigned int op2 = bits (insn, 4, 6);
unsigned int op = bits (insn, 21, 22);
case 0x3:
if (op == 0x1)
- return copy_bx_blx_reg (gdbarch, insn, regs, dsc); /* blx register. */
+ return copy_bx_blx_reg (gdbarch, insn,
+ regs, dsc); /* blx register. */
else
return copy_undef (gdbarch, insn, dsc);
static int
decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs,
+ struct displaced_step_closure *dsc)
{
unsigned int opcode = bits (insn, 20, 24);
return copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
}
+static void
+thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
+ CORE_ADDR to, struct regcache *regs,
+ struct displaced_step_closure *dsc)
+{
+ error (_("Displaced stepping is only supported in ARM mode"));
+}
+
void
-arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
- CORE_ADDR from, CORE_ADDR to, struct regcache *regs,
+arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
+ CORE_ADDR to, struct regcache *regs,
struct displaced_step_closure *dsc)
{
int err = 0;
-
- if (!displaced_in_arm_mode (regs))
- error (_("Displaced stepping is only supported in ARM mode"));
+ enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
+ uint32_t insn;
/* Most displaced instructions use a 1-instruction scratch space, so set this
here and override below if/when necessary. */
dsc->cleanup = NULL;
dsc->wrote_to_pc = 0;
+ if (!displaced_in_arm_mode (regs))
+ return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc);
+
+ insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
+ if (debug_displaced)
+ fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
+ "at %.8lx\n", (unsigned long) insn,
+ (unsigned long) from);
+
if ((insn & 0xf0000000) == 0xf0000000)
err = decode_unconditional (gdbarch, insn, regs, dsc);
else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
{
struct displaced_step_closure *dsc
= xmalloc (sizeof (struct displaced_step_closure));
- enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
- uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
-
- if (debug_displaced)
- fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx "
- "at %.8lx\n", (unsigned long) insn,
- (unsigned long) from);
-
- arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc);
+ arm_process_displaced_insn (gdbarch, from, to, regs, dsc);
arm_displaced_init_closure (gdbarch, from, to, dsc);
return dsc;
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
- Even this may only true if the condition predicate is true. The
+ Even this may only true if the condition predicate is true. The
following use a condition predicate of ALWAYS so it is always TRUE.
There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
break;
default:
- internal_error
- (__FILE__, __LINE__,
- _("arm_extract_return_value: Floating point model not supported"));
+ internal_error (__FILE__, __LINE__,
+ _("arm_extract_return_value: "
+ "Floating point model not supported"));
break;
}
}
for (i = 0; i < TYPE_NFIELDS (type); i++)
{
enum type_code field_type_code;
- field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
+ field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
+ i)));
/* Is it a floating point type field? */
if (field_type_code == TYPE_CODE_FLT)
break;
default:
- internal_error
- (__FILE__, __LINE__,
- _("arm_store_return_value: Floating point model not supported"));
+ internal_error (__FILE__, __LINE__,
+ _("arm_store_return_value: Floating "
+ "point model not supported"));
break;
}
}
gdbarch_info_init (&info);
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, "could not update architecture");
+ internal_error (__FILE__, __LINE__, _("could not update architecture"));
}
static void
{
struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
- fprintf_filtered (file, _("\
-The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
+ fprintf_filtered (file,
+ _("The current execution mode assumed "
+ "(when symbols are unavailable) is \"%s\".\n"),
arm_fallback_mode_string);
}
{
struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
- fprintf_filtered (file, _("\
-The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
+ fprintf_filtered (file,
+ _("The current execution mode assumed "
+ "(even when symbols are available) is \"%s\".\n"),
arm_force_mode_string);
}
arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
- /* FPS register's type is INT, but belongs to float_group. */
+ /* FPS register's type is INT, but belongs to float_reggroup. Beside
+ this, FPS register belongs to save_regroup, restore_reggroup, and
+ all_reggroup, of course. */
if (regnum == ARM_FPS_REGNUM)
- return (group == float_reggroup);
+ return (group == float_reggroup
+ || group == save_reggroup
+ || group == restore_reggroup
+ || group == all_reggroup);
else
return default_register_reggroup_p (gdbarch, regnum, group);
}
not. */
attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
Tag_CPU_arch);
- attr_profile = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
+ attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
+ OBJ_ATTR_PROC,
Tag_CPU_arch_profile);
/* GCC specifies the profile for v6-M; RealView only
specifies the profile for architectures starting with
/* Add some default predicates. */
frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
dwarf2_append_unwinders (gdbarch);
+ frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
/* Now we have tuned the configuration, set a few final things,
arm_objfile_data_key
= register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
+ /* Add ourselves to objfile event chain. */
+ observer_attach_new_objfile (arm_exidx_new_objfile);
+ arm_exidx_data_key
+ = register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
+
/* Register an ELF OS ABI sniffer for ARM binaries. */
gdbarch_register_osabi_sniffer (bfd_arch_arm,
bfd_target_elf_flavour,
_("Show the disassembly style."),
helptext,
set_disassembly_style_sfunc,
- NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
+ NULL, /* FIXME: i18n: The disassembly style is
+ \"%s\". */
&setarmcmdlist, &showarmcmdlist);
add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
_("Show usage of ARM 32-bit mode."),
_("When off, a 26-bit PC will be used."),
NULL,
- NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
+ NULL, /* FIXME: i18n: Usage of ARM 32-bit
+ mode is %s. */
&setarmcmdlist, &showarmcmdlist);
/* Add a command to allow the user to force the FPU model. */
projects / deliverable / binutils-gdb.git / blobdiff